Shifting register unit, scanning driving circuit thereof, display panel and display device
By designing the input and output circuits of the shift register unit and controlling the node potential and trigger signal, the problem of output signal falling steps in GOA circuit design is solved, achieving stable display effects and high-quality image output.
Patent Information
- Application Number
- CN202422321434.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2034-09-23
AI Technical Summary
In the existing GOA circuit design, the output circuit signal has a step-down phenomenon, which affects the display effect and image quality.
A shift register unit is designed, including a first input circuit, a second input circuit, a first control circuit, a first output circuit, and a second output circuit. By controlling the potential of the node and the trigger signal, it is ensured that the output signal can rely on the first output circuit to output a constant voltage signal or rely on the second output circuit to output a low-level clock signal in the falling phase, thereby avoiding output steps.
It effectively avoids the step phenomenon of the output signal, improves the display stability and image quality, and reduces the falling edge time of the output signal.
Smart Images
Figure CN223401389U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit and a scan driving circuit thereof, a display panel, and a display device. Background Art
[0002] The GOA circuit, or gate driver circuit, is a crucial component of display panels, controlling the switching of gate lines within the display panel, thereby controlling the display of pixels. In existing GOA circuit designs, the output signal from the output circuit exhibits a step-down phenomenon. This step-down phenomenon can affect display quality, resulting in image degradation or display instability. Utility Model Content
[0003] The present disclosure provides a shift register unit and a scan driving circuit thereof, a display panel and a display device, so as to solve the technical problem that in the existing COA circuit design, a signal outputted by an output circuit may have a falling edge step.
[0004] In a first aspect, the present disclosure provides a shift register unit, comprising:
[0005] a first input circuit, a control terminal of which is connected to the first clock signal, an input terminal of which is connected to the trigger signal, and an output terminal of which is connected to the first node;
[0006] a second input circuit, configured to write the first constant voltage signal or the first clock signal into the second node according to the first clock signal and the trigger signal;
[0007] a first control circuit configured to input the first clock signal or the second clock signal to the third node based on the potential of the second node and a trigger signal, or to input the first clock signal or the second clock signal to the third node based on the potentials of both the second node and the first node;
[0008] a first output circuit, having a control terminal connected to the first node and an input terminal connected to the first constant voltage signal, and configured to output the first constant voltage signal when the level of the first node is valid;
[0009] The second output circuit has a control terminal connected to the third node and an input terminal connected to the first clock signal, and is configured to output the first clock signal when the level of the third node is valid.
[0010] In some embodiments, the first input circuit includes: a first transistor, a control terminal of which is connected to the first clock signal, an input terminal of which is connected to the trigger signal, and an output terminal of which is connected to the first node.
[0011] In some embodiments, the second input circuit includes: a second transistor, a control terminal of which is connected to the first clock signal, an input terminal of which is connected to the first constant voltage signal, and an output terminal of which is connected to the second node; and
[0012] The third transistor has a control terminal connected to the trigger signal, an input terminal connected to the first clock signal, and an output terminal connected to the second node.
[0013] In some embodiments, the shift register unit further includes: a second control circuit, a control end of which is connected to the first node, an input end of which is connected to the second clock signal, and an output end of which is connected to the first node, for pulling down the level at the first node when the first input circuit writes a valid level to the first node, or when the first input circuit does not input a voltage to the first node and the level at the first node and the second clock signal are at a valid level.
[0014] In some embodiments, the second control circuit includes: a fourth transistor having a control terminal connected to the first node and an input terminal connected to the second clock signal;
[0015] A first capacitor, one end of the first capacitor is connected to the output end of the fourth transistor, and the other end of the first capacitor is connected to the first node.
[0016] In some embodiments, the first control circuit includes:
[0017] a first control subcircuit, configured to input a second clock signal to a third node according to a potential of the second node;
[0018] The second control subcircuit is configured to input the first clock signal to the third node according to the trigger signal or the potential of the first node.
[0019] In some embodiments, the first control subcircuit includes:
[0020] a fifth transistor, having a control terminal connected to the second node, an input terminal connected to the second clock signal, and an output terminal connected to the fourth node;
[0021] a sixth transistor, a control terminal of which is connected to the second clock signal, an input terminal of which is connected to the fourth node, and an output terminal of which is connected to the third node;
[0022] The second capacitor has a first end connected to the second node and a second end connected to the fourth node.
[0023] In some embodiments, the second control subcircuit includes: a seventh transistor, a control terminal of which is connected to the trigger signal or the first node, an input terminal of which is connected to the first clock signal, and an output terminal of which is connected to the third node.
[0024] In some embodiments, the first output circuit includes: an eighth transistor, a control terminal of which is connected to the first node, an input terminal of which is connected to the first constant voltage signal, and an output terminal of which serves as the output terminal of the first output circuit.
[0025] In some embodiments, the second output circuit includes:
[0026] a ninth transistor, having a control terminal connected to the third node, an input terminal connected to the first clock signal, and an output terminal serving as an output terminal of the second output circuit;
[0027] A third capacitor has a first end connected to the third node and a second end connected to the input end of the ninth transistor.
[0028] In a second aspect, the present disclosure provides a scan driving circuit, comprising a plurality of cascaded shift register units as described in any one of the first aspects.
[0029] In a third aspect, the present disclosure provides a display panel comprising the scan drive circuit of the third aspect.
[0030] In a fourth aspect, the present disclosure provides a display device comprising the display panel according to the fourth aspect.
[0031] The present disclosure provides a shift register and a driving method thereof, a scan driving circuit, and a display device. The shift register unit includes a first input circuit, a control end of which is connected to a first clock signal, an input end of which is connected to a trigger signal, and an output end of which is connected to a first node; a second input circuit, used to write a first constant voltage signal or a first clock signal to a second node according to the first clock signal and the trigger signal; a first control circuit, used to input the first clock signal or the second clock signal to a third node according to the potential of the second node and the trigger signal, or to input the first clock signal or the second clock signal to the third node according to the potentials of the second node and the first node; a first output circuit, a control end of which is connected to the first node, an input end of which is connected to the first constant voltage signal, and is configured to output the first constant voltage signal when the level of the first node is valid; a second output circuit, a control end of which is connected to the third node, an input end of which is connected to the first clock signal, and is configured to output the first clock signal when the level of the third node is valid. Therefore, the output signal of the shift register unit provided by the present invention can rely on the first output circuit to output the first constant voltage signal or rely on the second output circuit to output the low-level first clock signal in the falling phase. When the trigger signal is valid, the first output circuit can output the first constant voltage signal to avoid output steps. Similarly, when the third node is valid and the first clock signal is at a low level, the second output circuit outputs the low level of the first clock signal. Because the falling edge data Tf of the first clock signal is small, the low level can also be output quickly through the second output circuit to avoid output steps. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Hereinafter, the present disclosure will be described in more detail based on embodiments and with reference to the accompanying drawings:
[0033] Figure 1 A circuit diagram of a shift register unit provided by an embodiment of the present utility model;
[0034] Figure 2 Another circuit diagram of a shift register unit provided by an embodiment of the present utility model;
[0035] Figure 3 The timing state diagram of each signal in the shift register provided by the embodiment of the utility model
[0036] Figure 4 This is the timing status diagram of each signal in the scan drive circuit.
[0037] Reference numerals: first input circuit 100, second input circuit 200, first control circuit 300, first control sub-circuit 310, second control sub-circuit 320, first output circuit 400, second output circuit 500, second control circuit 600, first node N1, second node N2, third node N3, fourth node N4, trigger signal STV, first clock signal CLK1, second clock signal CLK2, first constant voltage signal VGL, first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, eighth transistor T8, ninth transistor T9, first capacitor C1, second capacitor C2, third capacitor C3. DETAILED DESCRIPTION
[0038] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, and to fully understand and implement how the present disclosure applies technical means to solve technical problems and achieve the corresponding technical effects, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The embodiments of the present disclosure and the various features in the embodiments can be combined with each other without conflict, and the technical solutions formed are all within the scope of protection of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present disclosure.
[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0040] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.
[0041] Example 1
[0042] Reference Figure 1 and Figure 2 An embodiment of the present disclosure provides a shift register unit, including a first input circuit 100, a second input circuit 200, a first control circuit 300, a first output circuit 400, and a second output circuit 500. The control end of the first input circuit 100 is connected to the first clock signal CLK1, the input end of the first input circuit 100 is connected to the trigger signal STV, and the output end of the first input circuit 100 is connected to the first node N1; the second input circuit 200 is used to write the first constant voltage signal VGL or the first clock signal CLK1 into the second node N2 according to the first clock signal CLK1 and the trigger signal STV; the first control circuit 300 is used to (refer to Figure 1 ) inputs the first clock signal CLK1 or the second clock signal CLK2 to the third node N3 according to the potential of the second node N2 and the trigger signal STV, or (refer to Figure 2 ) Input the first clock signal CLK1 or the second clock signal CLK2 to the third node N3 according to the potentials of the second node N2 and the first node N1; the control end of the first output circuit 400 is connected to the first node N1, the input end of the first output circuit 400 is connected to the first constant voltage signal VGL, and is configured to output the first constant voltage signal VGL when the level of the first node N1 is valid; the control end of the second output circuit 500 is connected to the third node N3, the input end of the second output circuit 500 is connected to the first clock signal CLK1, and is configured to output the first clock signal CLK1 when the level of the third node N3 is valid.
[0043] In some embodiments, as Figure 1 and Figure 2 As shown, the first input circuit 100 includes a first transistor T1 , a control terminal of the first transistor T1 is connected to the first clock signal CLK1 , an input terminal of the first transistor T1 is connected to the trigger signal STV, and an output terminal of the first transistor T1 is connected to the first node N1 .
[0044] In some embodiments, as Figure 1 and Figure 2 As shown, the second input circuit 200 includes a second transistor T2 and a third transistor T3. The control terminal of the second transistor T2 is connected to the first clock signal CLK1, the input terminal of the second transistor T2 is connected to the first constant voltage signal VGL, and the output terminal of the second transistor T2 is connected to the second node N2. The control terminal of the third transistor T3 is connected to the trigger signal STV, the input terminal of the third transistor T3 is connected to the first clock signal CLK1, and the output terminal of the third transistor T3 is connected to the second node N2.
[0045] In some embodiments, as Figure 1 and Figure 2 As shown, the first control circuit 300 includes a first control sub-circuit 310 and a second control sub-circuit 320. The first control sub-circuit 310 is configured to input the second clock signal CLK2 to the third node N3 according to the potential of the second node N2. The second control sub-circuit 320 is configured to input the first clock signal CLK1 to the third node N3 according to the trigger signal STV or the potential of the first node N1.
[0046] In some embodiments, as Figure 1 and Figure 2 As shown, the first control subcircuit 310 includes a fifth transistor T5, a sixth transistor T6, and a second capacitor C2. The control terminal of the fifth transistor T5 is connected to the second node N2, the input terminal of the fifth transistor T5 is connected to the second clock signal CLK2, and the output terminal of the fifth transistor T5 is connected to the fourth node N4; the control terminal of the sixth transistor T6 is connected to the second clock signal CLK2, the input terminal of the sixth transistor T6 is connected to the fourth node N4, and the output terminal of the sixth transistor T6 is connected to the third node N3; the first terminal of the second capacitor C2 is connected to the second node N2, and the second terminal of the second capacitor C2 is connected to the fourth node N4.
[0047] In some embodiments, as Figure 1 As shown, the second control subcircuit 320 includes a seventh transistor T7 , a control terminal of the seventh transistor T7 being connected to the trigger signal STV, an input terminal of the seventh transistor T7 being connected to the first clock signal CLK1 , and an output terminal of the seventh transistor T7 being connected to the third node N3 .
[0048] In some embodiments, as Figure 2As shown, the second control subcircuit 320 includes a seventh transistor T7 , a control terminal of the seventh transistor T7 is connected to the first node N1 , an input terminal of the seventh transistor T7 is connected to the first clock signal CLK1 , and an output terminal of the seventh transistor T7 is connected to the third node N3 .
[0049] In some embodiments, as Figure 1 and Figure 2 As shown, the first output circuit 400 includes an eighth transistor T8 , a control terminal of the eighth transistor T8 is connected to the first node N1 , an input terminal of the eighth transistor T8 is connected to the first constant voltage signal VGL, and an output terminal of the eighth transistor T8 serves as an output terminal of the first output circuit 400 .
[0050] In some embodiments, as Figure 1 and Figure 2 As shown, the second output circuit 500 includes a ninth transistor T9 and a third capacitor C3. The control terminal of the ninth transistor T9 is connected to the third node N3, the input terminal of the ninth transistor T9 is connected to the first clock signal CLK1, and the output terminal of the ninth transistor T9 serves as the output terminal of the second output circuit 500. A first terminal of the third capacitor C3 is connected to the third node N3, and a second terminal of the third capacitor C3 is connected to the input terminal of the ninth transistor T9.
[0051] In some embodiments, as Figure 1 and Figure 2 As shown, the shift register unit further includes a second control circuit 600, a control terminal of the second control circuit 600 being connected to the first node N1, an input terminal of the second control circuit 600 being connected to the second clock signal CLK2, and an output terminal of the second control circuit 600 being connected to the first node N1. The second control circuit 600 is configured to pull down the level at the first node N1 when the first input circuit 100 writes a valid level to the first node N1, or when the first input circuit 100 does not input a voltage to the first node N1 and the level at the first node N1 and the second clock signal CLK2 are at a valid level.
[0052] In some embodiments, as Figure 1 and Figure 2 As shown, the second control circuit 600 includes a fourth transistor T4 and a first capacitor C1. The control terminal of the fourth transistor T4 is connected to the first node N1, and the input terminal of the fourth transistor T4 is connected to the second clock signal CLK2. The first terminal of the first capacitor C1 is connected to the output terminal of the fourth transistor T4, and the second terminal of the first capacitor C1 is connected to the first node N1.
[0053] This embodiment provides a driving method for the shift register unit of the above embodiment. The timing state diagram of each signal in the shift register of the above embodiment is as follows: Figure 3 As shown, the driving method includes:
[0054] The first level of the trigger signal STV in the first phase t3 changes to the second level in the second phase t4, and the second level is different from the first level;
[0055] In the second phase t4, the first clock signal CLK1 is at the second level, and the second clock signal CLK2 is at the first level.
[0056] The trigger signal STV passes through the first input circuit 100 so that the first node N1 is at a valid level.
[0057] The first clock signal CLK1 and the first constant voltage signal VGL make the second node N2 at the active level through the second input circuit 200;
[0058] The first clock signal CLK1 and the second clock signal CLK2 enable the third node N3 to be at an active level through the first control circuit 300;
[0059] The first clock signal CLK1 is outputted through the second output circuit 500 and the first constant voltage signal VGL is outputted through the first output circuit 400 . The output signal of the shift register unit changes from the first level to the second level in the first phase t3 .
[0060] In one embodiment, the second control circuit 600 includes a fourth transistor T4 and a first capacitor C1. The control terminal of the fourth transistor T4 is connected to the first node N1, and the input terminal of the fourth transistor T4 is connected to the second clock signal CLK2. One terminal of the first capacitor C1 is connected to the output terminal of the fourth transistor T4, and the other terminal of the first capacitor C1 is connected to the first node N1.
[0061] The second stage t4 is followed by a third stage t5, wherein:
[0062] In the third stage t5, the trigger signal STV and the second clock signal CLK2 are both at the second level, the first clock signal CLK1 is at the first level, and the second clock signal CLK2 makes the first node N1 at a valid level through the second control circuit 600; the first clock signal CLK1 makes the second node N2 at an invalid level through the second input circuit 200, and the first clock signal CLK1 makes the third node N3 at an invalid level through the first control circuit 300, the first constant voltage signal VGL is output through the first output circuit 400, and the shift register unit outputs the second level.
[0063] In one embodiment, when the first node N1 is at an active level, the first clock signal CLK1 causes the third node N3 to be at an inactive level via the second control sub-circuit 320 in the first control circuit 300 .
[0064] In one embodiment, the third stage t5 is followed by a fourth stage t6, wherein:
[0065] In the fourth stage t6, the trigger signal STV is at the second level, the first clock signal CLK1 and the second clock signal CLK2 are both at the first level; the second clock signal CLK2 makes the first node N1 at an invalid level through the second control circuit 600; the first clock signal CLK1 makes the second node N2 at an invalid level through the second input circuit 200, and the first control circuit 300 makes the third node N3 at an invalid level; the output signal of the shift register unit maintains the second level.
[0066] In one embodiment, a fifth stage t1 is further included before the first stage t3;
[0067] In the fifth stage t1, the trigger signal STV and the second clock signal CLK2 are at the first level, the first clock signal CLK1 is at the second level, the trigger signal STV makes the first node N1 at an invalid level through the first input circuit 100, the first constant voltage signal VGL makes the second node N2 at a valid level through the second input circuit 200, the second output circuit 500 makes the third node N3 at a valid level, the first clock signal CLK1 is output through the second output circuit 500, and the output of the shift register unit is at the second level.
[0068] In one embodiment, a sixth stage t2 is further included before the first stage t3 and after the fifth stage t1;
[0069] In the sixth stage t2, the trigger signal STV and the first clock signal CLK1 are at the first level, and the second clock signal CLK2 is at the second level; the second control circuit 600 controls the first node N1 to be maintained at an invalid level, and the first control circuit 300 controls the second node N2 to be maintained at a valid level, and the second clock signal CLK2 makes the third node N3 at a valid level through the first control circuit 300, the first clock signal CLK1 is output through the second output circuit 500, and the shift register unit outputs the first level.
[0070] In some embodiments, in the first stage t3, the first clock signal CLK1, the second clock signal CLK2, and the trigger signal STV are all at the first level; the second control circuit 600 controls the first node N1 to be maintained at an invalid level, the first control circuit 300 controls the second node N2 to be maintained at an invalid level, the second output circuit 500 controls the third node N3 to be maintained at a valid level, the first clock signal CLK1 is output through the second output circuit 500, and the shift register unit outputs the first level.
[0071] Taking the first level as high level, the second level as low level, and the low level as valid as an example, combined with Figure 3 right Figure 1 The driving method (principle) of the shift register unit shown is explained.
[0072] In the fifth phase t1, the trigger signal STV is at a high level, the first clock signal CLK1 is at a low level, and the second clock signal CLK2 is at a high level. The third transistor T3, the sixth transistor T6, and the seventh transistor T7 are turned off, and the first transistor T1 and the second transistor T2 are turned on. The high level of the trigger signal STV is written into the first node N1 via the first transistor T1, causing the first node N1 to be at a high level. The fourth transistor T4 and the eighth transistor T8 are turned off. The first constant voltage signal VGL is written into the second node N2 via the second transistor T2, causing the second node N2 to be at a low level. The fifth transistor T5 is turned on. The high level of the second clock signal CLK2 is written into the fourth node N4 via the fifth transistor T5, causing the fourth node N4 to be at a high level. Because the potential of the first clock signal CLK1 changes from high to low, the low level of the first clock signal CLK1 is written into the third node N3 due to the coupling effect of the third capacitor C3, causing the third node N3 to be at a low level. The ninth transistor T9 is turned on, and the low level of the first clock signal CLK1 is output via the ninth transistor T9. Therefore, in the fifth phase t1, Figure 1 The shift register unit shown outputs a low level.
[0073] In the sixth phase t2, the trigger signal STV is at a high level, the first clock signal CLK1 is at a high level, and the second clock signal CLK2 is at a low level. The third transistor T3, the first transistor T1, the second transistor T2, and the seventh transistor T7 are turned off, and the sixth transistor T6 is turned on. Node N1 is maintained at a high level from the previous phase due to the first capacitor C1, while the fourth transistor T4 and the eighth transistor T8 remain turned off. The second node N2 is maintained at a low level from the previous phase due to the second capacitor C2, while the fifth transistor T5 remains turned on. The low level of the second clock signal CLK2 is written to the fourth node N4 via the fifth transistor T5, causing the fourth node N4 to be at a low level. Due to the potential change from high to low at the fourth node N4, the low level of the fourth node N4 is written to the second node N2 due to the coupling effect of the second capacitor C2, further pulling down the level of the second node N2, which is then maintained at a low level by the second capacitor C2. The low level of the fourth node N4 is written into the third node N3 via the sixth transistor T6, so that the third node N3 is at a low level, the ninth transistor T9 is turned on, and the high level of the first clock signal CLK1 is output via the ninth transistor T9. Thus, in the sixth stage t2, Figure 1 The output signal of the shift register unit shown changes from the low level in the fifth stage to the high level.
[0074] In the first phase t3, the trigger signal STV, the first clock signal CLK1, and the second clock signal CLK2 are all at a high level. The third transistor T3, the first transistor T1, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are turned off. The first node N1 is maintained at a high level in the previous phase due to the first capacitor C1, and the fourth transistor T4 and the eighth transistor T8 are turned off. The second node N2 is maintained at a low level in the previous phase due to the second capacitor C2, and the fifth transistor T5 is still turned on. The high level of the second clock signal CLK2 is written to the fourth node N4 via the fifth transistor T5, causing the fourth node N4 to be at a high level. As the potential of the fourth node N4 changes from low to high, the high level of the fourth node N4 is written to the second node N2 due to the coupling effect of the second capacitor C2, causing the second node N2 to be at a high level. Then, the second node N2 and the fourth node N4 are maintained at a high level by the second capacitor C2. The third node N3 is maintained at a low level in the previous phase due to the third capacitor C3, and the ninth transistor T9 is turned on. The high level of the first clock signal CLK1 is output via the ninth transistor T9. Therefore, in the first phase t3, Figure 1 The shift register unit shown still outputs a high level.
[0075] In the second stage t4, the trigger signal STV is at a low level, the first clock signal CLK1 is at a low level, and the second clock signal CLK2 is at a high level. The third transistor T3, the first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, and the sixth transistor T6 is turned off. The low level of the trigger signal STV is written into the first node N1 through the first transistor T1, so that the first node N1 is at a low level, the fourth transistor T4 and the eighth transistor T8 are turned on, and the high potential of the second clock signal CLK2 is written into one end of the first capacitor C1 through the fourth transistor T4. Due to the voltage stabilizing effect of the first capacitor C1, the potential of the first node N1 is lowered to ensure that the eighth transistor T8 is turned on, and the first constant voltage signal VGL is output through the eighth transistor T8; the low level of the first clock signal CLK1 is written into the second node N2 through the third transistor T3, and at the same time, the first constant voltage signal VGL is written into the second node N2 through the second transistor T2, so that the second node N2 is at a low level. At a low level, the fifth transistor T5 is still in an on state, and the high level of the second clock signal CLK2 is written into the fourth node N4 via the fifth transistor T5, so that the fourth node N4 is still at a high level; the low level of the first clock signal CLK1 is written into the third node N3 via the seventh transistor T7, so that the third node N3 is at a low level. Due to the potential jump of the first clock signal CLK1 from high to low, the voltage stabilizing effect of the third capacitor C3 pulls down the potential of the third node N3, so that the voltage of the third node N3 is negative, the ninth transistor T9 is turned on, and the low level of the first clock signal CLK1 is output via the ninth transistor T9. Therefore, in the second stage t4, Figure 1The output signal of the shift register unit shown changes from a high level in the first phase t3 to a low level.
[0076] In the third stage t5, the trigger signal STV is at a low level, the first clock signal CLK1 is at a high level, and the second clock signal CLK2 is at a low level. The third transistor T3, the sixth transistor T6, and the seventh transistor T7 are turned on, and the first transistor T1 and the second transistor T2 are turned off. The first node N1 maintains the low level of the previous stage due to the first capacitor C1, the fourth transistor T4 and the eighth transistor T8 are turned on, and the low level of the second clock signal CLK2 is written to one end of the first capacitor C1 through the fourth transistor T4. Due to the potential jump from high to low of the second clock signal CLK2, the low level of the second clock signal CLK2 is written to the first node N1 due to the coupling effect of the first capacitor C1, thereby further lowering the potential of the first node N1, so that the first node N1 is at a low level, and then maintained by the first capacitor C1, the eighth transistor T8 is turned on, and the first constant voltage signal VGL is output through the eighth transistor T8; the first time The high level of the clock signal CLK1 is written into the second node N2 via the third transistor T3, causing the second node N2 to be at a high level. The fifth transistor T5 is turned off. As the potential of the second node N2 changes from low to high, the high level of the second node N2 is written into the fourth node N4 due to the coupling effect of the second capacitor C2, causing the fourth node N4 to remain at a high level. The high level of the fourth node N4 is written into the third node N3 via the sixth transistor T6. At the same time, the high level of the first clock signal CLK1 is written into the third node N3 via the seventh transistor T7, causing the third node N3 to be at a high level. The ninth transistor T9 is turned off. As a result, in the third stage t5, Figure 1 The shift register unit shown outputs a low level.
[0077] The inventors discovered that if the second control circuit 600 is not present, in the third stage t5, when the first clock signal CLK1 becomes high and the second clock signal CLK2 becomes low, a potential output of approximately -8.5V will be generated. This is because the first clock signal CLK1 is high at this time, the potential of the first node N1 rises slightly, and the first constant-voltage signal VGL output by the eighth transistor T8 is lost. However, under the control of the second control circuit 600, after the second clock signal CLK2 is low and written to the first node N1 via the fourth transistor T4, the signal output by the eighth transistor T8 will return to the first constant-voltage signal VGL and will be maintained thereafter, i.e., the current sensitivity and output effect will not be affected. If the clock signal loading time is reduced, the falling edge time Tf can be reduced to below 1u, and the potential of the output signal of the eighth transistor T8 can be reduced to below -9V, which can basically be considered as no potential output.
[0078] In the fourth phase t6, the trigger signal STV is low, the first clock signal CLK1 is high, and the second clock signal CLK2 is also high. The third transistor T3 and the seventh transistor T7 are turned on, and the first transistor T1, the second transistor T2, and the sixth transistor T6 are turned off. The first node N1 is maintained at a low level in the previous stage due to the first capacitor C1. The fourth transistor T4 and the eighth transistor T8 are turned on. The high level of the second clock signal CLK2 is written into one end of the first capacitor C1 via the fourth transistor T4. As the potential of the second clock signal CLK2 changes from low to high, the high level of the second clock signal CLK2 is written into the first node N1 due to the coupling effect of the first capacitor C1, pulling up the potential of the first node N1, so that the first node N1 is at a high level. Thereafter, the first node N1 is maintained at a high level by the first capacitor C1, and the fourth transistor T4 and the eighth transistor T8 are turned off. The high level of the first clock signal CLK1 is written into the second node N2 via the third transistor T3, so that the second node N2 is still at a high level. The fifth transistor T5 is turned off. The fourth node N4 maintains the high level of the previous stage due to the voltage stabilization effect of the second capacitor C2. The high level of the first clock signal CLK1 is written into the third node N3 via the seventh transistor T7, so that the third node N3 is at a high level. The ninth transistor T9 is turned off. Therefore, in the fourth stage t6, Figure 1 The output signal of the shift register unit shown is maintained at a low level.
[0079] After the fourth stage t6, when the trigger signal STV is maintained at the second level, the level of the first clock signal CLK1 and the level of the second clock signal CLK2 are repeatedly set according to the level of the first clock signal CLK1 and the level of the second clock signal CLK2 in the second stage t4, the third stage t5 and the fourth stage t6.
[0080] Taking the first level as high level, the second level as low level, and the low level as valid as an example, combined with Figure 3 right Figure 2 The driving method (principle) of the shift register unit shown is explained.
[0081] In the fifth phase t1, the trigger signal STV is at a high level, the first clock signal CLK1 is at a low level, and the second clock signal CLK2 is at a high level. The first transistor T1 and the second transistor T2 are turned on, and the third transistor T3 and the sixth transistor T6 are turned off. The high level of the trigger signal STV is written into the first node N1 via the first transistor T1, causing the first node N1 to be at a high level. The fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off. The first constant voltage signal VGL is written into the second node N2 via the second transistor T2, causing the second node N2 to be at a low level. The high level of the second clock signal CLK2 is written into the fourth node N4 via the fifth transistor T5, causing the fourth node N4 to be at a high level. Due to the potential change of the first clock signal CLK1 from high to low, due to the coupling effect of the third capacitor C3, the low level of the first clock signal CLK1 is written into the third node N3 via the third capacitor C3, causing the third node N3 to be at a low level. The ninth transistor T9 is turned on, and the low level of the first clock signal CLK1 is output via the ninth transistor T9. Therefore, in the fifth phase t1, Figure 2 The shift register unit shown outputs a low level.
[0082] In the sixth phase t2, the trigger signal STV is at a high level, the first clock signal CLK1 is at a high level, and the second clock signal CLK2 is at a low level. The sixth transistor T6 is turned on, while the third transistor T3, the first transistor T1, and the second transistor T2 are turned off. The first node N1 is maintained at a high level in the previous phase by the first capacitor C1, and the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off. The second node N2 is maintained at a low level in the previous phase by the second capacitor C2, and the fifth transistor T5 remains on. The low level of the second clock signal CLK2 is written to the fourth node N4 via the fifth transistor T5, causing the fourth node N4 to be at a low level. As the potential of the fourth node N4 changes from high to low, the low level of the fourth node N4 is written to the second node N2 due to the coupling effect of the second capacitor C2, causing the potential of the second node N2 to further decrease. Subsequently, the second node N2 is still maintained at a low level by the second capacitor C2. The low level of the fourth node N4 is written into the third node N3 via the sixth transistor T6, so that the third node N3 is at a low level, the ninth transistor T9 is turned on, and the high level of the first clock signal CLK1 is output via the ninth transistor T9. Thus, in the sixth stage t2, Figure 2 The output signal of the shift register unit shown changes from a low level in the fifth stage t1 to a high level.
[0083] In the first phase t3, the trigger signal STV is at a high level, the first clock signal CLK1 is at a high level, and the second clock signal CLK2 is at a high level. The third transistor T3, the first transistor T1, the second transistor T2, and the sixth transistor T6 are all turned off. The first node N1 is maintained at a high level in the previous phase by the second capacitor C2, and the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off. The second node N2 is maintained at a low level in the previous phase by the second capacitor C2, and the fifth transistor T5 remains on. The high level of the second clock signal CLK2 is written to the fourth node N4 via the fifth transistor T5, causing the fourth node N4 to be at a high level. The potential of the fourth node N4 changes from low to high. Due to the coupling effect of the second capacitor C2, the high level of the fourth node N4 is written to the second node N2 via the second capacitor C2, causing the second node N2 to become a high level. The second node N2 is then maintained at a high level by the second capacitor C2, and the fifth transistor T5 is turned off. The third node N3 is kept at a low level in the previous stage due to the third capacitor C3, the ninth transistor T9 is still turned on, and the high level of the first clock signal CLK1 is output through the ninth transistor T9, so that in the first stage t3, Figure 2 The output of the shift register unit shown is high.
[0084] In the second phase t4, the trigger signal STV is at a low level, the first clock signal CLK1 is at a low level, and the second clock signal CLK2 is at a high level. The third transistor T3, the first transistor T1, and the second transistor T2 are turned on, and the sixth transistor T6 is turned off. The low level of the first clock signal CLK1 is written to the second node N2 via the third transistor T3. Simultaneously, the first constant voltage signal VGL is written to the second node N2 via the second transistor T2, causing the second node N2 to remain at a low level. The fifth transistor T5 is turned on, and the high level of the second clock signal CLK2 is written to the fourth node N4 via the fifth transistor T5, causing the fourth node N4 to be at a high level. The low level of the trigger signal STV is written to the first node N1 via the first transistor T1, causing the first node N1 to be at a low level. The fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned on. The high level of the second clock signal CLK2 is written to one end of the first capacitor C1 via the fourth transistor T4. The voltage stabilization effect of the first capacitor C1 pulls down the first node N1. The fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 remain turned on. The low level of the first clock signal CLK1 is written into the ninth transistor T9 via the seventh transistor T7, so that the third node N3 is at a low level, the ninth transistor T9 is turned on, and the low level of the first clock signal CLK1 is output via the ninth transistor T9. Thus, in the second phase t4, Figure 2 The output signal of the shift register unit shown changes from a high level in the first phase t3 to a low level.
[0085] In the third phase t5, the trigger signal STV is at a low level, the first clock signal CLK1 is at a high level, and the second clock signal CLK2 is at a low level. The third transistor T3 and the sixth transistor T6 are turned on, while the first transistor T1 and the second transistor T2 are turned off. The first node N1 is maintained at a low level in the previous phase by the first capacitor C1. The fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are still turned on. The low level of the second clock signal CLK2 is written to one end of the first capacitor C1 via the fourth transistor T4. The potential of the second clock signal CLK2 changes from high to low. The low level of the second clock signal CLK2 is written to the first node N1 due to the coupling effect of the first capacitor C1, further lowering the low potential of the first node N1. The first node N1 is then maintained at a low level by the first capacitor C1. The eighth transistor T8 is still turned on, and the first constant voltage signal VGL is output via the eighth transistor T8. The high level of the first clock signal CLK1 is written into the second node N2 via the third transistor T3, causing the second node N2 to be at a high level. The fifth transistor T5 is turned off, and the potential of the second node N2 changes from low to high. Due to the coupling effect of the second capacitor C2, the high level of the second node N2 is written into the fourth node N4 via the second capacitor C2 and maintained by the second capacitor C2, so that the first capacitor C1 is still at a high level. The high level of the fourth node N4 is written into the third node N3 via the sixth transistor T6, and the high level of the first clock signal CLK1 is written into the third node N3 via the seventh transistor T7, causing the third node N3 to be at a high level. The ninth transistor T9 is turned off, so that in the third stage t5, Figure 2 The shift register unit shown outputs a low level.
[0086] The inventors discovered that if the second control circuit 600 is not present, in the third stage t5, when the first clock signal CLK1 becomes high and the second clock signal CLK2 becomes low, a potential output of approximately -8.5V will be generated. This is because the first clock signal CLK1 is high at this time, the potential of the first node N1 rises slightly, and the first constant-voltage signal VGL output by the eighth transistor T8 is lost. However, under the control of the second control circuit 600, after the second clock signal CLK2 is low and written to the first node N1 via the fourth transistor T4, the signal output by the eighth transistor T8 will return to the first constant-voltage signal VGL and will be maintained thereafter, i.e., the current sensitivity and output effect will not be affected. If the clock signal loading time is reduced, the falling edge time Tf can be reduced to below 1u, and the potential of the output signal of the eighth transistor T8 can be reduced to below -9V, which can basically be considered as no potential output.
[0087] In the fourth stage t6, the trigger signal STV is at a low level, the first clock signal CLK1 is at a high level, the second clock signal CLK2 is at a high level, the third transistor T3 is turned on, and the first transistor T1, the second transistor T2, and the sixth transistor T6 are turned off. The high level of the first clock signal CLK1 is written to the second node N2 via the third transistor T3, causing the second node N2 to be at a high level. The fifth transistor T5 is turned off, and due to the coupling effect of the second capacitor C2, the fourth node N4 is at a high level. The first node N1 is kept at a low level in the previous stage due to the first capacitor C1. The fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are still turned on. The high level of the first clock signal CLK1 is written to the third node N3 via the seventh transistor T7, causing the third node N3 to be at a high level. The ninth transistor T9 is turned off. The high level of the second clock signal CLK2 is written to the third node N3 via the fourth transistor T3, causing the third node N3 to be at a high level. The transistor T4 writes to one end of the first capacitor C1, and the potential of the second clock signal CLK2 changes from low to high. The high level of the second clock signal CLK2 is written to the first node N1 due to the coupling effect of the first capacitor C1, so that the potential of the first node N1 is pulled up, so that the first node N1 is at a high level. Thereafter, the first node N1 is maintained at a high level by the first capacitor C1, and the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 remain turned off. After the seventh transistor T7 is turned off, the third node N3 is maintained at a high level due to the third capacitor C3, and the ninth transistor T9 is still turned off. Therefore, in the fourth stage t6, Figure 2 The output signal of the shift register unit shown is maintained at a low level.
[0088] After the fourth stage t6, when the trigger signal STV is maintained at the second level, the level of the first clock signal CLK1 and the level of the second clock signal CLK2 are repeatedly set according to the level of the first clock signal CLK1 and the level of the second clock signal CLK2 in the second stage t4, the third stage t5 and the fourth stage t6.
[0089] In the shift register unit and its driving method provided by this embodiment, during the falling phase of the shift register unit output signal, i.e., the second phase t4, the low level of the first clock signal CLK1 is written to the third node N3, i.e., the gate of the ninth transistor T9, via the seventh transistor, causing the ninth transistor T9 to turn on and output the low level of the first clock signal CLK1. Furthermore, because the falling edge time Tf of the first clock signal CLK1 is relatively short, and the fourth transistor T4 and the first capacitor C1 further lower the potential of the first node N1, the eighth transistor T8 is quickly turned on, causing the eighth transistor T8 to output the first constant voltage signal VGL, thereby eliminating the falling edge step of the output signal of the shift register unit. Furthermore, experiments have shown that:
[0090] 1. The output rising edge time Tr of the shift register unit provided in this embodiment is 700-900 n, and the falling edge time Tf is 0.8-1.4 u, which is shorter than the falling edge time Tf of the output signal in the existing project of 2-3 u;
[0091] 2. The capacitance values of the second capacitor C2, the third capacitor C3, and the first capacitor C1 in the shift register unit provided in this embodiment are 20~50f, 20~50f, and 80~100f, respectively, which are smaller than the capacitance values of existing projects (conventionally 90~100f, 150~200f, and 200~300f). Moreover, the capacitance values of the second capacitor C2 and the third capacitor C3 can be further reduced without affecting the output effect through simulation, and can be as low as 20f.
[0092] 3. Based on the 9T3C circuit architecture and the smaller capacitance values of the second capacitor C2, the third capacitor C3, and the first capacitor C1, the overall layout width of the shift register unit can be reduced from the current 140μm to 80-90μm, achieving the goal of reducing the border. If the width-to-length ratio (W / L) of the transistors TFT in the shift register unit is further adjusted, the layout width can be further shortened.
[0093] Example 2
[0094] The present embodiment provides a scan drive circuit, comprising a plurality of cascaded shift register units of the above-described embodiments. Each shift register unit provides a scan drive signal to a row of gate lines to implement scan drive for a display panel. The cascaded shift register units include a first-stage shift register unit to an M-stage shift register unit. The first input end of the second input circuit 200 and the input end of the first output unit in each stage of the shift register unit are connected to a first constant voltage signal VGL. In the present embodiment, M is an integer greater than or equal to 4.
[0095] In some embodiments, the scan driving circuit includes a plurality of cascaded Figure 1The shift register unit shown. The input end of the first input circuit 100, the first control end of the second input circuit 200, and the first control end of the first control unit in the first stage shift register unit are connected to the trigger signal STV, the control end of the first input circuit 100, the second input end and the second control end of the second input circuit 200, the first input end of the first control circuit 300, and the input end of the second input circuit 200 are connected to the first clock signal CLK1; the second input end and the second control end of the first control circuit 300, and the input end of the second control circuit 600 are connected to the second clock signal CLK2; the input end of the first input circuit 100, the first control end of the second input circuit 200, and the first control end of the first control unit in the Mth stage shift register unit are connected to the output signal of the M-1th stage shift register unit, wherein:
[0096] If the remainder when M is divided by 4 is 0, the control terminal of the first input circuit 100, the second input terminal and the second control terminal of the second input circuit 200, the first input terminal of the first control circuit 300, and the input terminal of the second input circuit 200 in the M-th stage shift register unit are connected to the fourth clock signal CLK4, and the second input terminal and the second control terminal of the first control circuit 300, and the input terminal of the fourth control circuit are connected to the first clock signal CLK1;
[0097] If the remainder when M is divided by 4 is 1, the control terminal of the first input circuit 100, the second input terminal and the second control terminal of the second input circuit 200, the first input terminal of the first control circuit 300, and the input terminal of the second input circuit 200 in the M-th stage shift register unit are connected to the first clock signal CLK1, and the second input terminal and the second control terminal of the first control circuit 300, and the input terminal of the fourth control circuit are connected to the second clock signal CLK2;
[0098] If the remainder when M is divided by 4 is 2, the control terminal of the first input circuit 100, the second input terminal and the second control terminal of the second input circuit 200, the first input terminal of the first control circuit 300, and the input terminal of the second input circuit 200 in the M-th stage shift register unit are connected to the second clock signal CLK2, and the second input terminal and the second control terminal of the first control circuit 300, and the input terminal of the fourth control circuit are connected to the third clock signal CLK3;
[0099] If the remainder when M is divided by 4 is 2, the control terminal of the first input circuit 100, the second input terminal and the second control terminal of the second input circuit 200, the first input terminal of the first control circuit 300, and the input terminal of the second input circuit 200 in the M-th stage shift register unit are connected to the third clock signal CLK3, the second input terminal and the second control terminal of the first control circuit 300, and the input terminal of the fourth control circuit are connected to the fourth clock signal CLK4, and so on. Taking M as 4 as an example, the timing state diagram of each signal in the scan drive circuit is as follows: Figure 4 shown.
[0100] In some embodiments, the scan driving circuit includes a plurality of cascaded Figure 2 The shift register unit shown. The input end of the first input circuit 100 and the first control end of the second input circuit 200 in the first stage shift register unit are connected to the trigger signal STV, the control end of the first input circuit 100, the second input end and the second control end of the second input circuit 200, the first input end of the first control circuit 300, and the input end of the second input circuit 200 are connected to the first clock signal CLK1; the second input end and the second control end of the first control circuit 300, and the input end of the second control circuit 600 are connected to the second clock signal CLK2; the input end of the first input circuit 100 and the first control end of the second input circuit 200 in the Mth stage shift register unit are connected to the output signal of the M-1th stage shift register unit, wherein:
[0101] If the remainder when M is divided by 4 is 0, the control terminal of the first input circuit 100, the second input terminal and the second control terminal of the second input circuit 200, the first input terminal of the first control circuit 300, and the input terminal of the second input circuit 200 in the M-th stage shift register unit are connected to the fourth clock signal CLK4, and the second input terminal and the second control terminal of the first control circuit 300, and the input terminal of the fourth control circuit are connected to the first clock signal CLK1;
[0102] If the remainder when M is divided by 4 is 1, the control terminal of the first input circuit 100, the second input terminal and the second control terminal of the second input circuit 200, the first input terminal of the first control circuit 300, and the input terminal of the second input circuit 200 in the M-th stage shift register unit are connected to the first clock signal CLK1, and the second input terminal and the second control terminal of the first control circuit 300, and the input terminal of the fourth control circuit are connected to the second clock signal CLK2;
[0103] If the remainder when M is divided by 4 is 2, the control terminal of the first input circuit 100, the second input terminal and the second control terminal of the second input circuit 200, the first input terminal of the first control circuit 300, and the input terminal of the second input circuit 200 in the M-th stage shift register unit are connected to the second clock signal CLK2, and the second input terminal and the second control terminal of the first control circuit 300, and the input terminal of the fourth control circuit are connected to the third clock signal CLK3;
[0104] If the remainder when M is divided by 4 is 2, then the control terminal of the first input circuit 100, the second input terminal and the second control terminal of the second input circuit 200, the first input terminal of the first control circuit 300, and the input terminal of the second input circuit 200 in the M-th stage shift register unit are connected to the third clock signal CLK3, and the second input terminal and the second control terminal of the first control circuit 300 and the input terminal of the fourth control circuit are connected to the fourth clock signal CLK4. Similarly, taking M as 4 as an example, the timing state diagram of each signal in the scan drive circuit is as follows: Figure 4 shown.
[0105] For other descriptions of the shift register unit, refer to the first embodiment.
[0106] Example 3
[0107] This embodiment further provides a display panel, comprising the scan driving circuit of the above embodiment.
[0108] In one embodiment, the display panel includes a liquid crystal display panel or an organic light emitting diode display panel.
[0109] Example 4
[0110] This embodiment further provides a display device, comprising the display panel of the above embodiment.
[0111] The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present invention.
[0112] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications derived therefrom remain within the scope of protection of the present invention.
Claims
1. A shift register unit, characterized in that: include: a first input circuit, a control terminal of which is connected to the first clock signal, an input terminal of which is connected to the trigger signal, and an output terminal of which is connected to the first node; a second input circuit, configured to write the first constant voltage signal or the first clock signal into the second node according to the first clock signal and the trigger signal; a first control circuit, configured to input the first clock signal or the second clock signal to the third node according to the potential of the second node and the trigger signal, or to input the first clock signal or the second clock signal to the third node according to the potentials of both the second node and the first node; a first output circuit, having a control terminal connected to the first node and an input terminal connected to the first constant voltage signal, and configured to output the first constant voltage signal when the level of the first node is valid; The second output circuit has a control terminal connected to the third node and an input terminal connected to the first clock signal, and is configured to output the first clock signal when the level of the third node is valid.
2. The shift register unit according to claim 1, wherein: The first input circuit includes: a first transistor, a control terminal of which is connected to a first clock signal, an input terminal of which is connected to a trigger signal, and an output terminal of which is connected to a first node.
3. The shift register unit according to claim 1, wherein: The second input circuit includes: a second transistor, a control terminal of which is connected to the first clock signal, an input terminal of which is connected to the first constant voltage signal, and an output terminal of which is connected to the second node; and The third transistor has a control terminal connected to the trigger signal, an input terminal connected to the first clock signal, and an output terminal connected to the second node.
4. The shift register unit according to claim 1, wherein: Also includes: A second control circuit has a control end connected to the first node, an input end connected to the second clock signal, and an output end connected to the first node, and is used to pull down the level at the first node when the first input circuit writes a valid level to the first node, or when the first input circuit does not input a voltage to the first node and the level at the first node and the second clock signal are at a valid level.
5. The shift register unit according to claim 4, wherein: The second control circuit includes: a fourth transistor, a control terminal of which is connected to the first node, and an input terminal of which is connected to the second clock signal; A first capacitor, one end of the first capacitor is connected to the output end of the fourth transistor, and the other end of the first capacitor is connected to the first node.
6. The shift register unit according to claim 1, wherein: The first control circuit includes: a first control subcircuit, configured to input the second clock signal to the third node according to the potential of the second node; The second control subcircuit is configured to input the first clock signal to the third node according to the trigger signal or the potential of the first node.
7. The shift register unit according to claim 6, wherein: The first control subcircuit includes: a fifth transistor, having a control terminal connected to the second node, an input terminal connected to the second clock signal, and an output terminal connected to the fourth node; a sixth transistor, a control terminal of which is connected to the second clock signal, an input terminal of which is connected to the fourth node, and an output terminal of which is connected to the third node; The second capacitor has a first end connected to the second node and a second end connected to the fourth node.
8. The shift register unit according to claim 6, wherein: The second control subcircuit includes: a seventh transistor, a control end of which is connected to the trigger signal or the first node, an input end of which is connected to the first clock signal, and an output end of which is connected to the third node.
9. The shift register unit according to claim 1, wherein: The first output circuit includes: an eighth transistor, a control end of which is connected to the first node, an input end of which is connected to the first constant voltage signal, and an output end of which serves as the output end of the first output circuit.
10. The shift register unit according to claim 1, wherein: The second output circuit includes: a ninth transistor, having a control terminal connected to the third node, an input terminal connected to the first clock signal, and an output terminal serving as an output terminal of the second output circuit; A third capacitor has a first end connected to the third node and a second end connected to the input end of the ninth transistor.
11. A scan driving circuit, comprising a plurality of cascaded shift register units according to any one of claims 1 to 10.
12. A display panel, characterized in that: The scanning driving circuit comprises the scanning driving circuit as claimed in claim 11.
13. A display device, characterized in that: Comprising the display panel as claimed in claim 12.