Embedded software image data transmission device and image processor

Abstract

The utility model provides an embedded software image data transmission device and an image processor, and relates to the field of radar image processing. The device comprises a main control board, a data transmission module and a plurality of image processing boards, the main control board transmits high-speed images and reliable control data to the data transmission module through the PCIe communication interface and the TCP communication interface, the high-speed images and the reliable control data are transmitted to all the image processing boards at a time through UDP broadcasting after being fused in the data transmission module, a simple link of two-path incoming and one-path broadcasting is achieved, the bottleneck of a single bus is eliminated, model-image synchronization is guaranteed, and the data transmission efficiency is improved. And the transmission efficiency of the radar image in a multi-plate parallel environment is obviously improved.

Description

Technical Field

[0001] The present application relates to the field of radar image processing and provides an embedded software image data transmission device and an image processor. Background Art

[0002] In related technologies, embedded radar image transmission systems mainly rely on a single PCIe link or a centralized Ethernet architecture. Although the former has high bandwidth, the link is rigid and has poor scalability. Although the latter has simple wiring, it is affected by TCP congestion control and cannot meet the coexistence requirements of large-capacity images and high-reliability control. Although some hybrid solutions use PCIe and Ethernet together, they lack unified link management. Timing errors often occur, such as receiving image data before the model is loaded or the results are mixed and cannot be traced. Overall, there are three major defects: rigid link management, single-channel bottleneck, and weak timing control. It is difficult to adapt to the requirements of modern radar image processing for parallel loading of multiple models, differentiated data fusion, and strict timing synchronization. Summary of the Invention

[0003] Based on this, it is necessary to provide an embedded software image data transmission device to address the above technical problems, which can improve the transmission efficiency of radar images in a multi-board parallel environment.

[0004] In a first aspect, the present application provides an embedded software data transmission device, the device comprising:

[0005] Main control board, integrated with PCIe and TCP communication interfaces;

[0006] The data transmission module is configured to establish connections with the PCIe and TCP communication interfaces of the main control board respectively, and the data transmission module also includes a UDP transmission unit;

[0007] The plurality of image processing boards are configured to establish a communication connection with the UDP transmission unit of the data transmission module.

[0008] In one embodiment, the data transmission module includes:

[0009] PCIe receiving unit, TCP receiving unit and data flow control unit, UDP transmission unit includes UDP sender,

[0010] The PCIe interface of the main control board establishes a PCIe transmission channel between the PCIe receiving unit and the data flow control unit, and the TCP interface of the main control board establishes a TCP transmission channel between the TCP receiving unit and the data flow control unit;

[0011] The data flow control unit is connected to the multiple image processing boards through the UDP transmitter. The data flow control unit is configured to send the data sent by the main control board to the multiple image processing boards through the UDP transmitter according to a preset timing.

[0012] In one embodiment, the data flow control unit is connected to the UDP sender via a data fusion pipeline, which includes:

[0013] Data synchronizer: The data synchronizer is used to coordinate the timing matching between the data transmitted by the TCP transmission channel and the PCIe transmission channel, so that the data transmitted by the TCP transmission channel and the PCIe transmission channel are synchronized;

[0014] Data merger, the data merger is used to integrate the synchronized data into a unified data stream for broadcast transmission by the UDP sender.

[0015] In one embodiment, the data flow control unit includes: a data gating, a model gating, an output gating, and a model identification code reading unit;

[0016] The TCP receiving unit is connected to the data fusion pipeline through model gating, and the PCIe receiving unit is connected to the data fusion pipeline through data gating and output gating in turn;

[0017] The model identification code reading unit is connected to the data gate and the model gate respectively.

[0018] In one embodiment, the model identification code reading unit is configured to generate a unique model identification code after the model gating is enabled, and trigger the enabling of the data gating after the model identification code is generated.

[0019] In one embodiment, the model identification code reading unit includes: a file header reading circuit, an address decoder and a data buffer;

[0020] The file header reading circuit reads the model identification code from a preset position of the model file received by the TCP receiving unit, the address decoder locates the storage address of the model identification code in the model file, and the data buffer temporarily stores the read model identification code.

[0021] In one embodiment, the data transmission module further includes: a PCIe sending unit, a TCP sending unit and a data separation pipeline; the UDP transmission unit further includes a UDP receiver;

[0022] Multiple image processing boards send image processing result data to the data separation pipeline through the UDP receiver.

[0023] The data separation pipeline is configured to separate the image processing result data into a first type of data and a second type of data, the first type of data including the result image data, and the second type of data including the result log data and the overall monitoring data;

[0024] The data separation pipeline sends the first type of data to the main control board through the PCIe sending unit, and sends the second type of data to the main control board through the TCP sending unit.

[0025] In one embodiment, the data separation pipeline includes:

[0026] A first data separation pipeline, the first data separation pipeline including a data type identifier and a high-speed buffer,

[0027] The data type identifier is configured to identify and extract first type data from the image processing result data;

[0028] The high-speed buffer is configured to temporarily store the extracted first type of data and then send it to the PCIe sending unit.

[0029] In one embodiment, the data separation pipeline includes:

[0030] The second data separation pipeline includes a log data filter and a format converter.

[0031] The log data filter is configured to filter the second type of data from the image processing result data;

[0032] The format converter is configured to convert the second type of data into a data format suitable for TCP transmission.

[0033] In a second aspect, the present application further provides an image processor, which is an FPGA processor or a DSP processor, and the image processor integrates the embedded software image data transmission device of the first aspect.

[0034] In the above-mentioned embedded software image data transmission device, the main control board transmits high-speed image and reliable control data to the data transmission module through the PCIe communication interface and the TCP communication interface. After internal fusion, the data transmission module sends it to all image processing boards at once via UDP broadcast, realizing a simple link with two input and one broadcast. This not only eliminates the bottleneck of a single bus, but also ensures model-image synchronization, significantly improving the transmission efficiency of radar images in a multi-board parallel environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a structural diagram of an embedded software image data transmission device in one embodiment;

[0036] Figure 2 A schematic diagram of embedded software image data transmission in one embodiment;

[0037] Figure 3 2 is a structural diagram of a data flow control unit in one embodiment. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0039] In one embodiment, Figure 1 As shown, an embedded software image data transmission device is provided, which includes: a main control board, a data transmission module and multiple image processing boards.

[0040] Specifically, the main control board integrates a PCIe communication interface and a TCP communication interface. The data transmission module can connect or dock with the main control board using these interfaces, respectively. The main control board can then transmit data to the data transmission module via these interfaces. The data transmission module also includes a UDP transmission unit, which packages data transmitted between the PCIe and TCP communication interfaces and the main control board into UDP packets and then broadcasts them via Ethernet to multiple image processing boards (image processing board 1, image processing board 2, ..., image processing board N).

[0041] The main control board, data transmission module and multiple image processing boards are connected in series in sequence to form a single data chain of main control board → data transmission module → image processing board.

[0042] In this embodiment, the main control board transmits data to the data transmission module through the PCIe communication interface and the TCP communication interface. After internal fusion, the data transmission module sends the data to all image processing boards at once via UDP broadcast, realizing a simple link with two input and one broadcast. This not only eliminates the bottleneck of a single bus, but also ensures model-image synchronization, significantly improving the transmission efficiency of radar images in a multi-board parallel environment.

[0043] In one embodiment, Figure 2 As shown, the data transmission module includes a PCIe receiving unit, a TCP receiving unit and a data flow control unit, and the UDP transmission unit includes a UDP sender.

[0044] The PCIe interface of the main control board establishes a PCIe transmission channel between the PCIe receiving unit and the data flow control unit, and the TCP interface of the main control board establishes a TCP transmission channel between the TCP receiving unit and the data flow control unit;

[0045] The data flow control unit is connected to the multiple image processing boards through the UDP transmitter. The data flow control unit is configured to send the data sent by the main control board to the multiple image processing boards through the UDP transmitter according to a preset timing.

[0046] Specifically, the PCIe communication interface of the main control board can be inserted into the PCIe receiving unit of the data transmission module through a differential line pair to form a PCIe transmission channel. The PCIe transmission channel can serve as a high-speed data transmission backbone, responsible for the transmission of image data. The PCIe transmission channel can transmit image data to the data flow control unit without waiting.

[0047] The TCP communication interface of the main control board can be connected to the TCP receiving unit of the data transmission module through an RJ45 network cable to form a TCP transmission channel. The TCP transmission channel can be responsible for transmitting the model file data along the TCP transmission channel to the data flow control unit.

[0048] The data flow control unit synchronously latches and packages the data transmitted by the two channels according to the preset timing, and then sends it to multiple image processing boards simultaneously in a broadcast manner through the UDP transmitter, forming a coherent data path in which the data enters the PCIe+TCP communication interface and is then sent out through the UDP transmitter.

[0049] It's important to note that the UDP sender can leverage the network's broadcast capabilities to simultaneously send data packets carrying model identification codes to multiple image processing boards, ensuring that all boards receive the same model file data and image data simultaneously. Each image processing board then loads the corresponding processing model based on the received model identification code and performs parallel computations based on its hardware capabilities. Furthermore, the performance of different image processing boards is evaluated and compared by comparing their reported processing time, resource utilization, and recognition accuracy.

[0050] In one embodiment, Figure 2 As shown, the data flow control unit and the UDP sender are connected through a data fusion pipeline, which includes:

[0051] Data synchronizer: The data synchronizer is used to coordinate the timing matching between the data transmitted by the TCP transmission channel and the PCIe transmission channel, so that the data transmitted by the TCP transmission channel and the PCIe transmission channel are synchronized;

[0052] Data merger, the data merger is used to integrate the synchronized data into a unified data stream for broadcast transmission by the UDP sender.

[0053] Specifically, the data flow control unit first feeds the model file data from the TCP transmission channel and the image data from the PCIe transmission channel into a data fusion pipeline. The data fusion pipeline is used to fuse the image data from the PCIe transmission channel with the model file data from the TCP transmission channel. The data fusion pipeline includes a data synchronizer and a data merger.

[0054] The data synchronizer can use a pair of counters to compare the timestamps and frame numbers of the data transmitted by the two transmission channels in real time. When the model file data arrives completely and the model identification code is generated, the synchronization signal is pulled high to ensure that the data beats of the two channels are consistent, so that the data transmitted by the TCP transmission channel and the PCIe transmission channel are synchronized.

[0055] Furthermore, the data merger can splice the synchronized data into a continuous byte stream to form a single UDP message, and push it directly to the UDP sender cache to complete cross-channel synchronization and unified packaging.

[0056] In one embodiment, Figure 2 As shown, the data transmission module also includes a PCIe sending unit, a TCP sending unit and a data separation pipeline; the UDP transmission unit also includes a UDP receiver;

[0057] The plurality of image processing boards send the image processing result data to a data separation pipeline through a UDP receiver, wherein the data separation pipeline is configured to separate the image processing result data into a first type of data and a second type of data, wherein the first type of data includes result image data and the second type of data includes result log data and overall monitoring data;

[0058] The data separation pipeline sends the first type of data to the main control board through the PCIe sending unit, and sends the second type of data to the main control board through the TCP sending unit.

[0059] Specifically, multiple image processing boards can access UDP receivers via Ethernet, integrating synchronized data into a unified data stream and feeding it into a data separation pipeline. At the pipeline entrance, the data separation pipeline first parses the type flag in each frame's packet header and directly stores the result image data (first type data) in a high-speed buffer. The PCIe sender then immediately transmits the result log data and overall monitoring data (second type data) back to the main control board via the PCIe transmission channel, ensuring high bandwidth and low latency. The TCP sender then transfers the result log data and overall monitoring data (second type data) to a low-speed buffer. After format conversion, the TCP sender reliably transmits them back to the main control board along the existing TCP transmission channel, achieving automatic diversion and corresponding transmission of heterogeneous data within the same data transmission module.

[0060] It should be noted that the UDP receiver can be used to receive the processing result data from each image processing board. The UDP receiver can achieve data timing separation by reading the timer. For example, the result image data is received before the timer reaches a preset time, and the result log data and overall monitoring data are received after the timer reaches a preset time. The delay control mechanism can automatically distinguish different types of data based on the timing characteristics of data transmission.

[0061] Similarly, the UDP receiver can extract the model identification code from the data packet according to the fixed code length of the model identification code. By reading the data flow control unit, it can match the model identification code and identify the model and processing board to which the received image processing result belongs. Furthermore, if multiple image processing boards return processing results simultaneously, the model identification code carried in the data packet can also distinguish the source of each result data, ensuring that the data is correctly transmitted to the corresponding processing path.

[0062] In one embodiment, Figure 2 As shown, the data separation pipeline includes:

[0063] A first data separation pipeline, the first data separation pipeline including a data type identifier and a high-speed buffer,

[0064] The data type identifier is configured to identify and extract first type data from the image processing result data;

[0065] The high-speed buffer is configured to temporarily store the extracted first type of data and then send it to the PCIe sending unit.

[0066] Specifically, the first data separation pipeline includes a data type identifier and a high-speed buffer. The data type identifier is located at the exit of the UDP receiver. The first data separation pipeline identifies the packet header of each return frame and retains only frames whose headers indicate result image data (first type of data). All other return frames whose headers do not indicate first type of data are discarded.

[0067] The retained image data can be transferred to a high-speed buffer, which can be a storage medium such as FLASH or DDR. When the high-speed buffer is half full, the resulting image data begins to be transmitted via the PCIe transmission channel. The PCIe send unit can pull the entire frame of data back to the main control board at once, completing the seamless conversion from UDP return frames to PCIe uplink frames.

[0068] In one embodiment, Figure 2 As shown, the data separation pipeline includes:

[0069] a second data separation pipeline, the second data separation pipeline comprising a log data filter and a format converter, the log data filter being configured to filter the second type of data from the image processing result data;

[0070] The format converter is configured to convert the second type of data into a data format suitable for TCP transmission.

[0071] Specifically, the log data filter is located at the UDP receiver exit. It filters out the result log data and overall monitoring data (second type data) based on the packet header type field and temporarily stores them in a buffer, discarding the remaining data. The buffer can be a storage medium such as FLASH or EEPROM.

[0072] Furthermore, the format converter can retrieve the result log data and overall monitoring data from the cache, complete the length, checksum and separator according to the fixed text template, and then cut them into message segments that meet the requirements of the sending unit. Finally, the TCP sending unit transmits them back to the main control board along the TCP transmission channel to complete the orderly return of low-speed and small data volumes.

[0073] Through this data separation mechanism, different types of return data can be allocated to corresponding transmission channels according to data type and transmission characteristics requirements. As a result, image data can be quickly transmitted back through the PCIe transmission channel, and result log data and overall monitoring data can be transmitted through the TCP transmission channel, achieving optimized configuration of data transmission and maximizing performance.

[0074] In one embodiment, Figure 3 As shown, the data flow control unit includes: data gating, model gating, output gating and model identification code reading unit;

[0075] The TCP receiving unit is connected to the data fusion pipeline through model gating, and the PCIe receiving unit is connected to the data fusion pipeline through data gating and output gating in turn;

[0076] The model identification code reading unit is connected to the data gate and the model gate respectively.

[0077] Specifically, the data flow control unit is internally provided with a model gating, a data gating, an output gating and a model identification code reading unit.

[0078] The TCP receiving unit's output can be directly connected to the model gate's input, and the model gate's output is then connected to the data fusion pipeline, forming the model's first-stage valve. The PCIe receiving unit's output can first pass through data gating, then output gating, and finally enter the data fusion pipeline, forming the second and third-stage valves after the image.

[0079] It should be noted that the sampling port of the model identification code reading unit is simultaneously connected to the exit of the model gate and the enable end of the data gate, that is, when the model gate is opened and the model file data is fully entered, the model identification code reading unit immediately extracts the unique identification code and simultaneously sends a release pulse to the data gate. Only when the model identification code is valid and the data gate is opened, the output gate is finally opened, and the model file data and image data are synchronously sent to the data fusion pipeline. Thus, the three-level gates are linked in sequence to ensure that the model file data arrives first, the image data arrives later, and is finally output in a unified manner.

[0080] In one embodiment, Figure 3 As shown, the model identification code reading unit is configured to generate a unique model identification code after the model gating is turned on, and trigger the data gating to be turned on after the model identification code is generated;

[0081] The model identification code reading unit includes: a file header reading circuit, an address decoder and a data buffer;

[0082] The file header reading circuit reads the model identification code from a preset position of the model file received by the TCP receiving unit, the address decoder locates the storage address of the model identification code in the model file, and the data buffer temporarily stores the read model identification code.

[0083] Specifically, the file header reading circuit primarily consists of a shift register, a clock generator, and a data latch. The shift register reads the model identification code from a preset position in the model file received by the TCP receiving unit. The clock generator provides a synchronous clock signal to control the data reading rhythm, and the data latch latches and outputs valid data on the rising edge of the clock. During operation, the model file data is serially input into the shift register and shifted bit by bit under the clock signal. When the shift register detects the file header identifier, the latch outputs the complete identifier code data in parallel. The output binary format of the file header identifier is directly passed to the address decoder as a control signal for model selection.

[0084] The address decoder's input signal is derived from the header identifier output by the header read circuit. It operates by combining the binary address signal through AND and OR gates to generate the corresponding chip select or memory cell select signal. When the header identifier is input, the decoder activates the corresponding output line based on the identifier combination, enabling precise selection of a specific model.

[0085] In the model identification code reading unit, the address decoder receives the file header identifier from the file header reading circuit and generates the corresponding model identification code output based on the identifier information. For example, receiving the identifier 000 generates 0x01 (Model 1), 001 generates 0x02 (Model 2), and 010 generates 0x03 (Model 3), with the resulting binary identifiers increasing in sequence. While generating the model identification code, the address decoder also sends the corresponding address signal to the data buffer, which is used to locate and access the data storage area of ​​the corresponding model. The generated identification code can be written into the file header or data stream to identify the current model type.

[0086] It should be noted that the address decoder has a wide range of application scenarios, including decoding the address signal sent by the CPU into chip select signals of different peripherals in the microcontroller (such as register access of peripherals such as UART, SPI, I2C, etc.), and implementing set associative mapping in the CPU's cache controller to map memory addresses to specific cache rows and ways.

[0087] The data buffer can be composed of an SRAM memory cell array, a row and column selector, and a read / write driver. The SRAM cell array provides data storage space, the row and column selector selects specific memory cells based on address signals received from the address decoder, and the read / write driver controls data writing and reading operations. During data storage, the address signal locates the target cell via the row and column selector, and the write driver writes the data to the selected location. During data reading, the read driver reads the data from the selected cell and outputs it via the data bus.

[0088] Based on the same concept, the present application also provides an image processor, which is an FPGA processor or a DSP processor, and the image processor is integrated with an embedded software image data transmission device.

[0089] Specifically, this application directly embeds the aforementioned image data transmission device within an FPGA or DSP-based image processor, enabling it to simultaneously perform radar image algorithm computations and multi-interface data distribution. This allows for simultaneous image-model broadcasting and result return via on-chip PCIe, TCP, and UDP transmission channels without the need for an external data transmission module. FPGAs, which are field-programmable gate arrays, offer reconfigurable logic circuits and high parallelism, making them suitable for high-speed image processing. DSPs, which are digital signal processors with dedicated multiply-add arrays and instruction sets, excel at complex algorithmic operations and offer strong real-time performance.

[0090] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The above embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. An embedded software image data transmission device, characterized in that: The device comprises: Main control board, integrated with PCIe and TCP communication interfaces; A data transmission module is configured to establish connections with the PCIe and TCP communication interfaces of the main control board respectively, and the data transmission module also includes a UDP transmission unit; A plurality of image processing boards are configured to establish a communication connection with the UDP transmission unit of the data transmission module.

2. The embedded software image data transmission device according to claim 1, characterized in that: The data transmission module includes: PCIe receiving unit, TCP receiving unit and data flow control unit, the UDP transmission unit includes a UDP sender, The PCIe interface of the main control board establishes a PCIe transmission channel with the data flow control unit through the PCIe receiving unit, and the TCP interface of the main control board establishes a TCP transmission channel with the data flow control unit through the TCP receiving unit; The data flow control unit is communicatively connected to the multiple image processing boards via the UDP transmitter, and the data flow control unit is configured to send the data sent by the main control board to the multiple image processing boards via the UDP transmitter according to a preset timing.

3. The embedded software image data transmission device according to claim 2, characterized in that: The data flow control unit is connected to the UDP sender via a data fusion pipeline, and the data fusion pipeline includes: A data synchronizer is used to coordinate the timing matching between the data transmitted by the TCP transmission channel and the PCIe transmission channel, so as to synchronize the data transmitted by the TCP transmission channel and the PCIe transmission channel; A data merger is used to integrate the synchronized data into a unified data stream for broadcast transmission by the UDP sender.

4. The embedded software image data transmission device according to claim 3, characterized in that: The data flow control unit includes: data gating, model gating, output gating and model identification code reading units; The TCP receiving unit is communicatively connected to the data fusion pipeline via the model gating, and the PCIe receiving unit is communicatively connected to the data fusion pipeline via the data gating and the output gating in sequence; The model identification code reading unit is connected to the data gate and the model gate respectively.

5. The embedded software image data transmission device according to claim 4, characterized in that: The model identification code reading unit is configured to generate a unique model identification code after the model gating is enabled, and trigger the enabling of the data gating after the model identification code is generated.

6. The embedded software image data transmission device according to claim 5, characterized in that: The model identification code reading unit includes: a file header reading circuit, an address decoder and a data buffer; The file header reading circuit reads the model identification code from a preset position of the model file received by the TCP receiving unit, the address decoder locates the storage address of the model identification code in the model file, and the data buffer temporarily stores the read model identification code.

7. The embedded software image data transmission device according to claim 2, characterized in that: The data transmission module further includes: a PCIe sending unit, a TCP sending unit and a data separation pipeline; the UDP transmission unit further includes a UDP receiver; The plurality of image processing boards send the image processing result data to the data separation pipeline through the UDP receiver, The data separation pipeline is configured to separate the image processing result data into a first type of data and a second type of data, the first type of data including result image data, and the second type of data including result log data and overall monitoring data; The data separation pipeline sends the first type of data to the main control board through the PCIe sending unit, and sends the second type of data to the main control board through the TCP sending unit.

8. The embedded software image data transmission device according to claim 7, characterized in that: The data separation pipeline includes: a first data separation pipeline comprising a data type identifier and a high-speed buffer, The data type identifier is configured to identify and extract the first type of data from the image processing result data; The high-speed buffer is configured to temporarily store the extracted first type of data and then send it to the PCIe sending unit.

9. The embedded software image data transmission device according to claim 7, characterized in that: The data separation pipeline includes: a second data separation pipeline comprising a log data filter and a format converter, The log data filter is configured to filter the second type of data from the image processing result data; The format converter is configured to convert the second type of data into a data format suitable for TCP transmission.

10. An image processor, wherein the image processor is an FPGA processor or a DSP processor, and the image processor is integrated with the embedded software image data transmission device according to any one of claims 1 to 9.

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