Complete machine multi-power amplifier control device and audio playing equipment

Abstract

The utility model discloses a complete machine multi-power-amplifier control device and audio playing equipment, which are applied to the field of multi-power-amplifier control, and comprise a processing chip, a plurality of power amplifier chips and a control module, the communication protocol interface of the processing chip is connected with the communication protocol interface of each power amplifier chip and is used for initializing and resetting each power amplifier chip; the audio interface of the processing chip is connected with the audio interface of each power amplifier chip and is used for transmitting an audio signal; the control signal output end of the processing chip is connected with the control signal input end of the control module, and each output end of the control module is connected with the input end of the corresponding power amplifier chip; and the output end of each power amplifier chip is connected with the input end of the corresponding loudspeaker. When the processing chip outputs effective signals, after all the power amplifier chips are located at the same device address through the control module, the power amplifier chips at the device address are controlled to reset at the same time, so that all the power amplifier modules are located at the same working state starting point.

Description

Technical Field

[0001] The utility model relates to the field of multi-power amplifier control, in particular to a complete multi-power amplifier control device and audio playback equipment. Background Art

[0002] With the development of science and technology, people's requirements for sound quality are getting higher and higher. In order to enrich the sound level and reduce the distortion problem of a single speaker when covering the entire audio frequency range, multiple speakers can be set to process sounds in different frequency ranges respectively to improve sound quality and reduce distortion. Driving these speakers requires multiple power amplifier chips.

[0003] However, since multiple power amplifier chips are serially initialized, the working starting points of each power amplifier chip are inconsistent, resulting in a phase difference in the output of the speaker, that is, the sound output is not synchronized.

[0004] Therefore, how to make the working starting point of the power amplifier chip consistent is a technical problem that needs to be solved urgently. Utility Model Content

[0005] In view of this, the purpose of this utility model is to provide a complete multi-amplifier control device to solve the problem that the serial initialization of multiple amplifier chips will cause the working starting points of each amplifier chip to be inconsistent, resulting in phase differences in the output of the speaker. The specific solution is as follows:

[0006] In order to solve the above technical problems, the present application provides a whole-machine multi-amplifier control device, comprising: a processing chip, multiple power amplifier chips, and a control module;

[0007] The communication protocol interface of the processing chip is connected to the communication protocol interface of each power amplifier chip, and is used to initialize and reset each power amplifier chip;

[0008] The audio interface of the processing chip is connected to the audio interface of each power amplifier chip for transmitting audio signals;

[0009] The control signal output terminal of the processing chip is connected to the control signal input terminal of the control module, and each output terminal of the control module is connected to the input terminal of the corresponding power amplifier chip, so as to control all the power amplifier chips to be at the same device address when the signal output by the control signal output terminal of the processing chip is a valid signal;

[0010] The output end of each power amplifier chip is connected to the input end of the corresponding speaker.

[0011] As an optional solution, the control module includes: a plurality of switch devices, the number of the switch devices being equal to the number of the power amplifier chips, and configured to switch on the circuit between the control signal output terminal of the processing chip and the input terminal of the power amplifier chip when the signal output from the control signal output terminal of the processing chip is the valid signal; and switch off the circuit between the control signal output terminal of the processing chip and the input terminal of the power amplifier chip when the signal output from the control signal output terminal of the processing chip is the invalid signal;

[0012] The first ends of the switch devices are connected to each other, and the common end thereof is the control signal input end of the control module;

[0013] The second end of each switch device is the output end of the control module and is respectively connected to the input end of the corresponding power amplifier chip.

[0014] As an optional solution, the switching device is a diode, the valid signal is a low-level signal, and the invalid signal is a high-level signal;

[0015] The cathode of the diode is the first end of the switching device, and the anode of the diode is the second end of the switching device.

[0016] As an optional solution, the switching device is a switching tube;

[0017] The first end of the switch tube is the first end of the switch device, the second end of the switch tube is the second end of the switch device, and the control end of the switch tube is connected to the control signal output end of the processing chip.

[0018] As an optional solution, the switch tube is a PNP transistor, the valid signal is a low-level signal, and the invalid signal is a high-level signal;

[0019] The PNP base is the control end of the switch tube, the PNP collector is the first end of the switch tube, and the PNP emitter is the second end of the switch tube.

[0020] As an optional solution, the system further includes: a plurality of decoding chips, the number of the decoding chips being equal to the number of the power amplifier chips;

[0021] The audio signal input end of each decoding chip is connected to the audio interface of the processing chip, and the decoded audio signal output end of each decoding chip is connected to the audio interface of the corresponding power amplifier chip.

[0022] As an optional solution, the decoded audio output terminal of the above-mentioned decoding chip is connected to the corresponding audio interface of the power amplifier chip through an I2S signal line.

[0023] As an optional solution, the number of the power amplifier chips is 3, namely a first power amplifier chip, a second power amplifier chip, and a third power amplifier chip;

[0024] The communication protocol interface of the first power amplifier chip, the communication protocol interface of the second power amplifier chip, and the communication protocol interface of the third power amplifier chip are respectively connected to the communication protocol interface of the processing chip through an I2C bus, and the processing chip is a system-on-chip;

[0025] The control signal output terminal of the processing chip and the control signal input terminal of the control module are GPIO interfaces.

[0026] As an optional solution, the power amplifier chip further includes an expansion port, and one power amplifier chip is connected to a plurality of the speakers.

[0027] In order to solve the above technical problems, the present application also provides an audio playback device, including the above-mentioned whole-machine multi-amplifier control device.

[0028] The present application provides a complete multi-amplifier control device comprising a processing chip, a plurality of power amplifier chips, and a control module; the communication protocol interface of the processing chip is connected to the communication protocol interface of each of the power amplifier chips, for initializing and resetting each of the power amplifier chips; the audio interface of the processing chip is connected to the audio interface of each of the power amplifier chips, for transmitting audio signals; the control signal output terminal of the processing chip is connected to the control signal input terminal of the control module, and each output terminal of the control module is connected to the input terminal of the corresponding power amplifier chip, for controlling all of the power amplifier chips to be at the same device address when the signal output from the control signal output terminal of the processing chip is a valid signal; the output terminal of each of the power amplifier chips is connected to the input terminal of the corresponding speaker. As can be seen from the above, when the control signal output terminal of the processing chip outputs a valid signal, the control module makes all the power amplifier chips at the same device address, and then the communication protocol interface of the processing chip controls the reset of the power amplifier chip at the device address. After the reset is completed, the control signal output terminal of the processing chip stops outputting a valid signal. Since all the power amplifier chips are at the same device address, all the power amplifier chips are at the same working state starting point after being reset at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0030] Figure 1A multi-amplifier control device for a whole machine provided in an embodiment of the present application;

[0031] Figure 2 A specific control module circuit diagram provided in an embodiment of the present application;

[0032] Figure 3 A specific whole-machine multi-amplifier control device provided in the embodiment of the present application;

[0033] Figure 4 A specific whole-machine multi-amplifier control device provided in the embodiment of the present application;

[0034] Figure 5 This is an operating logic diagram of a complete multi-amplifier control device provided in an embodiment of the present application;

[0035] The reference numerals are as follows: 10 is a processing chip, 20 is a power amplifier chip, 30 is a control module, 40 is a decoding chip, 201 is a first power amplifier chip, 202 is a second power amplifier chip, and 203 is a third power amplifier chip. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0037] The core of this application is to provide a complete multi-amplifier control device and an audio playback device.

[0038] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0039] With the development of science and technology, people's requirements for sound quality are getting higher and higher. In order to enrich the sound level and reduce the distortion problem of a single speaker when covering the entire audio frequency range, multiple speakers can be set to process sounds in different frequency ranges respectively to improve sound quality and reduce distortion. Driving these speakers requires multiple power amplifier chips.

[0040] However, since multiple power amplifier chips are serially initialized, the working starting points of each power amplifier chip are inconsistent, resulting in a phase difference in the output of the speaker, that is, the sound output is not synchronized.

[0041] Therefore, how to make the working starting point of the power amplifier chip consistent is a technical problem that needs to be solved urgently.

[0042] In order to solve the above problems, an embodiment of the present utility model discloses a whole-machine multi-power amplifier control device. Figure 1 The embodiment of the present application provides a whole machine multi-amplifier control device, such as Figure 1 As shown, the device includes: a processing chip 10, a plurality of power amplifier chips 20, and a control module 30;

[0043] The communication protocol interface of the processing chip 10 is connected to the communication protocol interface of each power amplifier chip 20, and is used to initialize and reset each power amplifier chip 20;

[0044] The audio interface of the processing chip 10 is connected to the audio interface of each power amplifier chip 20 for transmitting audio signals;

[0045] The control signal output terminal of the processing chip 10 is connected to the control signal input terminal of the control module 30, and each output terminal of the control module 30 is connected to the input terminal of the corresponding power amplifier chip 20, so as to control all the power amplifier chips 20 to be at the same device address when the signal output by the control signal output terminal of the processing chip 10 is a valid signal;

[0046] The output terminal of each power amplifier chip 20 is connected to the input terminal of the corresponding speaker.

[0047] The processing chip 10 can be any chip that can output audio signals, including a system-on-chip (SoC). It should be noted that the audio signals output by the processing chip 10 are typically digital audio signals, while the signals received and processed by the power amplifier chip 20 are typically analog audio signals. Therefore, if the audio interface of the processing chip 10 is connected to the audio interface of the power amplifier chip 20, the power amplifier chip 20 must have a decoding function to decode the received digital audio signals into analog audio signals. Alternatively, a processing chip 10 that directly outputs analog audio signals can be directly connected to a power amplifier chip 20 that can only receive and process analog audio signals.

[0048] The power amplifier chip 20 receives the audio signal output by the processing chip 10, converts it into a sound signal, and generates sound through the corresponding speaker. However, considering that the audio signal directly output by the processing chip 10 may not be interpreted by the corresponding power amplifier chip 20, a decoding chip can be added between the power amplifier chip 20 and the processing chip 10 to decode the audio signal output by the processing chip 10 into a signal that can be interpreted by the power amplifier chip 20.

[0049] The above-mentioned control module 30, after receiving the valid signal output by the processing chip 10, places all the power amplifier chips 20 at the same device address. The device address refers to the address used to uniquely identify a slave device on the communication bus in the communication protocol. In a specific embodiment, the valid signal is a low-level signal, and the invalid signal is a high-level signal. When the output signal of the control module 30 is a low-level signal, the circuit between the processing chip 10 and the power amplifier chip 20 is turned on, so that the pins connecting all the power amplifier chips 20 to the control module 30 are pulled down to a low potential, so that all the power amplifier chips 20 are under the same device address. At this time, the control module 30 can be composed of a plurality of diodes corresponding to the number of power amplifier chips 20, or it can be composed of the same number of switching tubes.

[0050] The whole-machine multi-amplifier control device provided in the present application includes: a processing chip 10, multiple power amplifier chips 20, and a control module 30; the communication protocol interface of the processing chip 10 is connected to the communication protocol interface of each power amplifier chip 20, for initializing and resetting each power amplifier chip 20; the audio interface of the processing chip 10 is connected to the audio interface of each power amplifier chip 20, for transmitting audio signals; the control signal output end of the processing chip 10 is connected to the control signal input end of the control module 30, and each output end of the control module 30 is connected to the input end of the corresponding power amplifier chip 20, for controlling all power amplifier chips 20 to be at the same device address when the signal output from the control signal output end of the processing chip 10 is a valid signal; the output end of each power amplifier chip 20 is connected to the input end of the corresponding speaker. As can be seen from the above, when the control signal output end of the processing chip 10 outputs a valid signal, the control module 30 makes all the power amplifier chips 20 at the same device address, and then the communication protocol interface of the processing chip 10 controls the reset of the power amplifier chip 20 at the device address. After the reset is completed, the control signal output end of the processing chip 10 stops outputting a valid signal. Since all the power amplifier chips 20 are at the same device address, all the power amplifier chips 20 are reset at the same time and are at the same starting point of the working state.

[0051] In order to achieve the requirement of resetting all power amplifier chips 20 simultaneously, according to the above embodiment, this embodiment provides a specific solution. The control module 30 includes: a plurality of switching devices, the number of which is equal to the number of power amplifier chips 20, and is used to conduct the circuit between the control signal output terminal of the processing chip 10 and the input terminal of the power amplifier chip 20 when the signal output by the control signal output terminal of the processing chip 10 is a valid signal;

[0052] When the signal outputted by the control signal output terminal of the processing chip 10 is an invalid signal, the circuit between the control signal output terminal of the processing chip 10 and the input terminal of the power amplifier chip 20 is turned off;

[0053] The first terminals of the switch devices are connected to each other, and the common terminal thereof is the control signal input terminal of the control module 30;

[0054] The second end of each switch device is the output end of the control module 30 and is respectively connected to the input end of the corresponding power amplifier chip 20 .

[0055] It should be noted that the number of switching devices corresponds one-to-one to each power amplifier chip 20, and each switching device controls a power amplifier chip 20 separately. When the control signal output end of the processing chip 10 outputs an invalid signal, the switching device remains in the off state so that the signal does not affect the power amplifier chip 20. When the control signal output end of the processing chip 10 outputs a valid signal, the switching device will close and turn on the circuit between the processing chip 10 and the corresponding power amplifier chip 20, and the processing chip 10 will adjust all power amplifier chips 20 to the same device address.

[0056] As can be seen from the above, when the signal output from the control signal output terminal of the processing chip 10 is an invalid signal, the switch device will be opened, and the circuit between the processing chip 10 and the power amplifier chip 20 will not be conductive. This invalid signal has no effect on the power amplifier chip 20. When the signal output from the control signal output terminal of the processing chip 10 is a valid signal, the switch device will be closed, and the circuit between the processing chip 10 and the power amplifier chip 20 will be conductive. At the same time, the processing chip 10 adjusts all the power amplifier chips 20 to the same device address. At this time, the processing chip 10 resets the power amplifier chip 20 with the device address, thereby resetting all the power amplifier chips 20 simultaneously.

[0057] In order to achieve the requirement of resetting all power amplifier chips 20 simultaneously, according to the above embodiment, this embodiment provides a specific solution: Figure 2 A circuit diagram of a specific control module 30 provided in an embodiment of the present application is shown as follows: Figure 2 As shown, in a specific embodiment, the switching device is a diode (such as Figure 2 As shown, they are DW15, DW16, and DW17 respectively), the valid signal is a low-level signal, and the invalid signal is a high-level signal.

[0058] The cathode of the diode is the first terminal of the switching device, and the anode of the diode is the second terminal of the switching device.

[0059] In this embodiment, the control signal output terminal of the processing chip 10 and the control signal input terminal of the control module 30 are GPIO interfaces, and the input terminal of the power amplifier chip 20 is the ADDR pin connected to the output terminal of the control module 30. It should be noted that when the GPIO output is high, due to the unidirectional conductivity of the diode, the diode is not conductive, and therefore the ADDR pin of the power amplifier chip 20 will not change accordingly. When the GPIO output is low, the diode is conductive and pulls down the ADDR pins of all power amplifier chips 20 to a low potential, so that all power amplifier chips 20 are at the same device address. At this time, the processing chip 10 resets the power amplifier chip 20 of the device address, so that all power amplifier chips 20 can be reset at the same time and are at the same working starting point.

[0060] As can be seen from the above, due to the unidirectional conductivity of the diode, when the valid signal is a low-level signal, the control signal output terminal of the processing chip 10 outputs a high-level signal, and the above circuit is non-conductive, thus having no effect on the pin potential of the power amplifier chip 20. However, when the control signal output terminal of the processing chip 10 outputs a low-level signal, the above circuit is conductive, simultaneously pulling down all ADDR pins to a low potential, placing them at the same device address. At this point, the processing chip 10 resets the power amplifier chip 20 at that device address, thereby resetting all power amplifier chips 20 simultaneously.

[0061] In order to achieve the requirement of resetting all power amplifier chips 20 simultaneously, according to the above embodiment, this embodiment provides a specific solution, in which the switching device is a switching tube;

[0062] The first end of the switch tube is the first end of the switch device, the second end of the switch tube is the second end of the switch device, and the control end of the switch tube is connected to the processing chip.

[0063] It can be understood that the control ends of all switching tubes are connected to the processing chip 10, and the processing chip 10 simultaneously controls the conduction and disconnection of all switching tubes. When the signal output from the control signal output end of the processing chip 10 is a valid signal, the processing chip 10 controls all switching tubes to be turned on at the same time, and adjusts the power amplifier chip 20 connected to the switching tube to the same device address.

[0064] As can be seen from the above, all switching transistors are controlled by the processing chip 10 to turn on and off. When the control signal output terminal of the processing chip 10 outputs a valid signal, all switching transistors simultaneously conduct the path between the processing chip 10 and the corresponding power amplifier chip 20, and all power amplifier chips 20 are placed at the same device address. At this time, the processing chip 10 resets the power amplifier chip 20 at the device address, thereby achieving a simultaneous reset of all power amplifier chips 20.

[0065] In order to achieve the requirement of resetting all power amplifier chips 20 simultaneously, according to the above embodiment, this embodiment provides a specific solution, in which the switch tube is a PNP transistor, the valid signal is a low-level signal, and the invalid signal is a high-level signal;

[0066] The base of the PNP transistor is the control end of the switch tube, the collector of the PNP transistor is the first end of the switch tube, and the emitter of the PNP transistor is the second end of the switch tube.

[0067] In this embodiment, when the control signal output end of the processing chip 10 outputs a high-level signal, due to the characteristics of the PNP transistor, the voltage of its base is higher than that of the emitter, and the transistor is not turned on. When the control signal output end of the processing chip 10 outputs a low-level signal, the voltage of the base is lower than that of the emitter, and the transistor is turned on.

[0068] From the above, it can be seen that based on the characteristic that the PNP transistor is turned on only when the base voltage is less than the emitter voltage, the PNP transistor can disconnect the conduction of the circuit between the processing chip 10 and the power amplifier chip 20 when the control signal output terminal of the processing chip 10 outputs a high-level signal, and connect the circuit between the processing chip 10 and the power amplifier chip 20 when the control signal output terminal of the processing chip 10 outputs a low-level signal, and at the same time lower the potential of the input terminal of each power amplifier chip 20, so that all power amplifier chips are at the same device address.

[0069] In order to ensure that the audio signal received by the power amplifier chip 20 is a resolvable audio signal, according to the above embodiment, Figure 3 As shown, this embodiment provides a specific solution, further comprising: a plurality of decoding chips 40, the number of the decoding chips 40 being equal to the number of the power amplifier chips 20;

[0070] The audio signal input end of each decoding chip 40 is connected to the audio interface of the processing chip 10 , and the decoded audio signal output end of each decoding chip 40 is connected to the audio interface of the corresponding power amplifier chip 20 .

[0071] It is understandable that the audio signal type output by the processing chip 10 is not necessarily the same as the audio signal type received by the power amplifier chip 20. Therefore, depending on the actual situation, a decoder chip 40 may be installed between the audio interface of the processing chip 10 and the audio interface of the power amplifier chip 20 to ensure compatibility between the output signal of the processing chip 10 and the input signal of the power amplifier chip 20. It should be noted that the decoder chip 40 can be an independent chip connected between the processing chip 10 and the power amplifier chip 20, or it can be part of the power amplifier chip 20, that is, the power amplifier chip 20 includes both decoding and amplification functions.

[0072] From the above, it can be seen that by adding a decoding chip 40 between the processing chip 10 and the power amplifier chip 20, the audio signal output by the processing chip 01 can be decoded to obtain the audio signal type that can be received and analyzed by the power amplifier chip 20, thereby ensuring the compatibility between the output signal of the processing chip 10 and the input signal of the power amplifier chip 20.

[0073] In order to reduce the complexity of wiring on the processing chip 10, according to the above embodiment, this embodiment provides a specific solution, in which the audio input end of the decoding chip 40 is connected to the audio interface of the processing chip 10 via an SPDIF (Sony / Philips Digital Interface, coaxial output) signal line.

[0074] It should be noted that if Figure 3 As shown, at this time, the audio signal that the power amplifier chip 20 can parse is I2S (Inter-IC Sound, integrated circuit built-in audio bus), and the processing chip 10 inputs the SPDIF signal to the decoding chip 40. The signal line of this signal is generally one, while the I2S signal line is generally three. Therefore, the decoding chip 40 can not only convert the audio signal into an audio signal that can be parsed by the power amplifier chip 20, but also ensure that the audio interface of the processing chip 10 matches the audio interface of the power amplifier chip 20.

[0075] As can be seen from the above, the audio input terminal of the decoding chip 40 is connected to the audio interface of the processing chip 10 via an SPDIF signal line. Since there is generally only one SPDIF signal line, the complexity of wiring on the processing chip 10 can be greatly reduced.

[0076] According to the above embodiment, Figure 4 and Figure 5 As shown, this embodiment provides a specific solution, the number of the power amplifier chips 20 is 3, namely the first power amplifier chip 201, the second power amplifier chip 202, and the third power amplifier chip 203;

[0077] The communication protocol interface of the first power amplifier chip 201, the communication protocol interface of the second power amplifier chip 202, and the communication protocol interface of the third power amplifier chip 203 are respectively connected to the communication protocol interface of the processing chip 10 through an I2C bus. The processing chip 10 is a system-level chip;

[0078] The control signal output terminal of the processing chip 10 and the control signal input terminal of the control module 30 are GPIO interfaces.

[0079] After power-on, the SOC (System on Chip) first pulls up the level of the GPIO interface, so that the first power amplifier chip 201, the second power amplifier chip 202 and the third power amplifier chip 203 work at different device addresses, and then serially initializes the three power amplifier chips 20 through the I2C bus of the SOC. However, since the serial initialization does not initialize the three power amplifier chips 20 at the same time, but initializes them one by one in sequence, the working starting points of the first power amplifier chip 201, the second power amplifier chip 202 and the third power amplifier chip 203 are inconsistent. After the initialization is completed, the SOC pulls down the GPIO, so that all the power amplifier chips are at the same device address, and resets the power amplifier chip at the address through the I2C bus to make their working starting points consistent. After the reset is completed, the SOC pulls up the GPIO.

[0080] From the above, it can be seen that the SOC pulls down the GPIO level so that the first power amplifier chip 201, the second power amplifier chip 202 and the third power amplifier chip 203 are all at the same device address, and then controls the power amplifier chip 20 of the device address to be reset at the same time through the I2C bus, so that the working starting points of the first power amplifier chip 201, the second power amplifier chip 202 and the third power amplifier chip 203 are consistent.

[0081] In order to expand the application scenarios of the whole-machine multi-amplifier control device, according to the above embodiment, this embodiment provides a specific solution, where the power amplifier chip 20 further includes an expansion port, and one power amplifier chip 20 is connected to multiple speakers.

[0082] It is understandable that the same multi-amplifier control device may need to increase or decrease the number of speakers in different scenarios. Therefore, to accommodate a wider range of application scenarios, the amplifier chip 20 may also include an expansion port. In one embodiment, multiple speakers can be added to the same amplifier chip 20, and multi-channel output can be achieved if supported by the amplifier chip 20. In another embodiment, the amplifier chip 20 has a bridging function, and the expansion port is a bridging interface. Two amplifier chips 20 are connected to output higher power to drive a single speaker or a dual-coil speaker.

[0083] It should be noted that the positions of different speakers connected to the power amplifier chip 20 are independent of each other, and the speakers can be set at different positions according to specific needs. For example, in mobile screen products, some speakers can be on the screen, and other speakers can be located on the base.

[0084] From the above, it can be seen that the power amplifier chip 20 can add additional speakers through the expansion port, or connect multiple power amplifier chips 20 to drive a single speaker with higher power, so as to expand the application scenarios of the whole machine multi-amplifier control device.

[0085] Finally, this embodiment provides an audio playback device, including the above-mentioned whole-machine multi-amplifier control device.

[0086] The above description of the disclosed embodiments will enable those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is to be construed in the widest possible manner consistent with the principles and novel features disclosed herein.

Claims

1. A whole machine multi-amplifier control device, characterized in that: include: Processing chip, multiple power amplifier chips, control module; The communication protocol interface of the processing chip is connected to the communication protocol interface of each power amplifier chip, and is used to initialize and reset each power amplifier chip; The audio interface of the processing chip is connected to the audio interface of each power amplifier chip for transmitting audio signals; The control signal output terminal of the processing chip is connected to the control signal input terminal of the control module, and each output terminal of the control module is connected to the input terminal of the corresponding power amplifier chip, so as to control all the power amplifier chips to be at the same device address when the signal output by the control signal output terminal of the processing chip is a valid signal; The output end of each power amplifier chip is connected to the input end of the corresponding speaker.

2. The whole machine multi-amplifier control device according to claim 1, characterized in that: The control module includes: a plurality of switch devices, the number of which is equal to the number of the power amplifier chips, and is configured to connect the circuit between the control signal output terminal of the processing chip and the input terminal of the power amplifier chip when the signal output from the control signal output terminal of the processing chip is the valid signal; and disconnect the circuit between the control signal output terminal of the processing chip and the input terminal of the power amplifier chip when the signal output from the control signal output terminal of the processing chip is the invalid signal; The first ends of the switch devices are connected to each other, and the common end thereof is the control signal input end of the control module; The second end of each switch device is the output end of the control module and is respectively connected to the input end of the corresponding power amplifier chip.

3. The whole machine multi-amplifier control device according to claim 2, characterized in that: The switching device is a diode, the valid signal is a low-level signal, and the invalid signal is a high-level signal; The cathode of the diode is the first end of the switching device, and the anode of the diode is the second end of the switching device.

4. The whole machine multi-amplifier control device according to claim 2, characterized in that: The switching device is a switching tube; The first end of the switch tube is the first end of the switch device, the second end of the switch tube is the second end of the switch device, and the control end of the switch tube is connected to the processing chip.

5. The whole machine multi-amplifier control device according to claim 4, characterized in that: The switch tube is a PNP transistor, the valid signal is a low-level signal, and the invalid signal is a high-level signal; The base of the PNP transistor is the control end of the switch tube, the collector of the PNP transistor is the first end of the switch tube, and the emitter of the PNP transistor is the second end of the switch tube.

6. The whole machine multi-amplifier control device according to claim 1, characterized in that: Also includes: A plurality of decoding chips, the number of the decoding chips being equal to the number of the power amplifier chips; The audio signal input end of each decoding chip is connected to the audio interface of the processing chip, and the decoded audio signal output end of each decoding chip is connected to the audio interface of the corresponding power amplifier chip.

7. The whole machine multi-amplifier control device according to claim 6, characterized in that: The audio input terminal of the decoding chip is connected to the audio interface of the processing chip via an SPDIF signal line.

8. The whole machine multi-power amplifier control device according to any one of claims 1 to 7, characterized in that: The number of the power amplifier chips is 3, namely the first power amplifier chip, the second power amplifier chip, and the third power amplifier chip; The communication protocol interface of the first power amplifier chip, the communication protocol interface of the second power amplifier chip, and the communication protocol interface of the third power amplifier chip are respectively connected to the communication protocol interface of the processing chip through an I2C bus, and the processing chip is a system-on-chip; The control signal output terminal of the processing chip and the control signal input terminal of the control module are GPIO interfaces.

9. The whole machine multi-amplifier control device according to claim 1, characterized in that: The power amplifier chip also includes an expansion port, and one power amplifier chip is connected to multiple speakers.

10. An audio playback device, characterized in that: The invention comprises the whole machine multi-power amplifier control device according to any one of claims 1 to 9.

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