Integrated automatic test system for transformer substation

Abstract

The utility model discloses an integrated automation test system for a transformer station, which relates to the technical field of power system automation and comprises an interface module to be tested, a front-end data acquisition module, a data front-end preprocessing module, a microcontroller module, a radio frequency switch circuit and a wireless radio frequency chip. According to the utility model, to-be-tested data of a transformer station is accessed through the to-be-tested interface module; through the signal conditioning module and the filtering gating module, performance indexes such as the signal-to-noise ratio, the spurious-free dynamic range and the common-mode rejection ratio of signals to be detected are improved, high-precision collection is achieved, and multi-channel parallel sampling is achieved through the ADC collection module. The data to be tested can enter a monitoring state safely and quickly and are uploaded to the microcontroller module, real-time data uploading and acquisition are completed, control and data storage of multiple pieces of test data are achieved, and the data are combined and sent to the automatic test module for automatic test. Automatic test control of artificial intelligence is realized, and the efficiency of automatic test is improved.

Description

Technical Field

[0001] This utility model relates to the field of power system automation technology, and in particular to a substation integrated automation testing system. Background Technology

[0002] In power systems, automation devices in smart substations, such as protection and measurement and control systems, monitor and control the primary and secondary equipment of the entire substation. They also perform time-related testing functions such as remote control hold time, remote signaling anti-jitter, and SOE resolution. With the development of smart grid construction, more and more new smart substations are being built. The reliability of the functions and performance of these devices directly affects the safe operation of the substation; therefore, testing of smart substation automation devices is extremely important.

[0003] Currently, time correlation testing of automated devices still relies on some single-function debugging tools, such as multimeters, oscilloscopes, and simple switch quantity testers. Some of these instruments have simple functions, are inconvenient to use, or have low accuracy. Others require multiple instruments to complete the test, which cannot meet the testing needs of smart substations. Utility Model Content

[0004] The purpose of this utility model is to address the shortcomings and deficiencies of the existing technology by providing a substation integrated automation testing system, which solves the problems of inconvenient and low-precision testing of intelligent substation automation devices in the existing technology.

[0005] To achieve the above objectives, this utility model provides the following technical solution:

[0006] A substation integrated automation testing system includes a test interface module, a front-end data acquisition module, a data front-end preprocessing module, a microcontroller module, an RF switch circuit, a wireless RF chip, an alarm module, a human-machine interface module, a clock module, and a power supply module. The output of the test interface module is connected to the input of the front-end data acquisition module, the output of the front-end data acquisition module is connected to the input of the data front-end preprocessing module, and the output of the data front-end preprocessing module is connected to the input of the microcontroller module. The microcontroller module is connected to the wireless RF chip via the RF switch circuit, and the alarm module, human-machine interface module, clock module, and power supply module are each connected to the microcontroller module.

[0007] As a further preferred embodiment of the substation integrated automation test system of this utility model, the data front-end preprocessing module includes a signal conditioning module, a filtering and gating module, and an ADC acquisition module. The front-end data acquisition module is connected to the microcontroller module in sequence through the signal conditioning module, the filtering and gating module, and the ADC acquisition module.

[0008] As a further preferred embodiment of the substation integrated automation testing system of this utility model, the signal conditioning module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first operational amplifier, a second operational amplifier, and a third operational amplifier. The signal input -IN terminal is connected to one end of the first resistor; the other end of the first resistor is connected to one end of the first capacitor, one end of the third resistor, and the negative power supply pin of the first operational amplifier; the other end of the first capacitor is connected to the other end of the third resistor and the output pin of the first operational amplifier; the signal input +IN terminal is connected to one end of the second resistor; and the other end of the second resistor is connected to the first operational amplifier. The positive power supply pin of the amplifier is connected to one end of the fourth resistor and one end of the second capacitor. The other end of the second capacitor is connected to the other end of the fourth resistor and grounded. The output pin of the first operational amplifier is connected to one end of the fifth resistor. The other end of the fifth resistor is connected to the positive power supply pin of the second operational amplifier. The negative power supply pin of the second operational amplifier is connected to the negative power supply pin of the third operational amplifier. The positive power supply pin of the third operational amplifier is connected to one end of the eighth resistor and one end of the ninth resistor. The other end of the ninth resistor is grounded. The other end of the eighth resistor is connected to one end of the seventh resistor and the output pin of the second operational amplifier. The other end of the seventh resistor is connected to one end of the fourth capacitor. The other end of the fourth capacitor is connected to one end of the ninth resistor. The other end of the ninth resistor is connected to one end of the third capacitor. The other end of the third capacitor is grounded.

[0009] As a further preferred embodiment of the substation integrated automation test system of this utility model, the filtering and gating module includes an anti-aliasing filter unit and a signal gating unit connected in sequence, and the signal conditioning module is connected to the ADC acquisition module through the anti-aliasing filter unit and the signal gating unit in sequence; wherein, the chip model of the anti-aliasing filter unit is OPA2277, and the chip model of the signal gating unit is ADG1634BCPZ.

[0010] As a further preferred embodiment of the substation integrated automation testing system of this utility model, the radio frequency switch circuit includes an RF terminal, a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, a fourth NMOS transistor Q4, a fifth NMOS transistor Q5, and a sixth NMOS transistor Q6; a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12; a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, and a sixth diode D6; an RF ANT terminal; a voltage VCTRL terminal; and a voltage VCTRI terminal. The RF terminal is connected to one end of the fifth resistor R5, one end of the seventh resistor R7, the drain of the third NMOS transistor Q3, and the drain of the fourth NMOS transistor Q4. The other end of the fifth resistor R5 is connected to the third NMOS transistor Q3. The source of the first NMOS transistor Q1, the drain of the second NMOS transistor Q2, and one end of the third resistor R3 are connected to the source of the first NMOS transistor Q1, the drain of the first NMOS transistor Q2, and one end of the first resistor R1. The other end of the first resistor R1 is connected to the source of the first NMOS transistor Q1 and grounded. The base of the first NMOS transistor Q1 is connected to the anode of the first diode. The cathode of the first diode is connected to the gate of the first NMOS transistor Q1 and one end of the second resistor R2. The other end of the second resistor R2 is connected to one end of the fourth resistor R4 and the voltage VCTRI terminal. One end of the sixth resistor R6 is connected to the gate of the second NMOS transistor Q2 and the cathode of the second diode D2. The anode of the second diode D2 is connected to the base of the second NMOS transistor Q2. The other end of the sixth resistor R6 is connected to the gate of the third NMOS transistor Q3 and the cathode of the third diode D3. The anode of the third diode D3 is connected to the base of the third NMOS transistor Q3.The gate of the fourth NMOS transistor Q4 is connected to the cathode of the fourth diode D4 and one end of the eighth resistor R8. The other end of the seventh resistor R7 is connected to the source of the fourth NMOS transistor Q4, the drain of the fifth NMOS transistor Q5, and one end of the ninth resistor R9. The gate of the fifth NMOS transistor Q5 is connected to one end of the tenth resistor R10 and the cathode of the fifth diode D5. The anode of the fifth diode D5 is connected to the base of the fifth diode D5. The source of the fifth NMOS transistor Q5 is connected to the other end of the ninth resistor R9, one end of the eleventh resistor R11, and the drain of the sixth NMOS transistor Q6. The gate of the sixth NMOS transistor Q6 is connected to one end of the twelfth resistor R12 and the cathode of the sixth diode D6. The anode of the sixth diode D6 is connected to the base of the sixth diode D6. The other end of the twelfth resistor R12 is connected to the other end of the eighth resistor R8. The other end of the tenth resistor R10 is connected to the voltage VCTRL terminal. The source of the sixth NMOS transistor Q6 is connected to the other end of the eleventh resistor R11 and the RF ANT terminal.

[0011] As a further preferred embodiment of the substation integrated automation test system of this utility model, the data storage module uses ST's S25FL128P Flash memory for real-time storage with a storage capacity of 128Mbit. It establishes communication with an external controller through an SPI interface, and the maximum clock frequency of the interface can reach 104MHz.

[0012] As a further preferred embodiment of the substation integrated automation testing system of this utility model, the human-machine interaction module includes an input unit and an output unit, the input unit is electrically connected to the output unit, and the input unit is electrically connected to the controller module.

[0013] As a further preferred embodiment of the substation integrated automation testing system of this utility model, the input unit includes a keyboard or a touch screen.

[0014] As a further preferred embodiment of the substation integrated automation testing system of this utility model, the output unit includes a display screen.

[0015] Compared with the prior art, the present invention, by adopting the above technical solution, has the following technical effects:

[0016] 1. This utility model discloses a substation integrated automation testing system, comprising a test interface module, a front-end data acquisition module, a data front-end preprocessing module, a microcontroller module, an RF switch circuit, a wireless RF chip, an alarm module, a human-machine interaction module, a clock module, and a power supply module. This utility model receives the test data from the substation through the test interface module; it improves the signal-to-noise ratio, spurious-free dynamic range, and common-mode rejection ratio of the test signal through a signal conditioning module and a filtering and gating module, achieving high-precision acquisition; and it achieves multi-channel parallel sampling through an ADC acquisition module. This allows the test data to safely and quickly enter the monitoring state, be uploaded to the microcontroller module, complete real-time data upload, realize the control and storage of multiple test data, and combine the data to send to the automation testing module for automated testing. This achieves automated test control using artificial intelligence, improving the efficiency of automated testing.

[0017] 2. The radio frequency switch circuit of this invention can better meet the operation of large voltage swing while ensuring insertion loss and isolation. It improves the traditional stacking technology, reduces uneven voltage distribution, significantly improves the branch voltage handling capability, and improves the branch voltage tolerance, thereby better serving antenna tuning and ensuring normal operation even under antenna mismatch. The radio frequency switch section adopts a series-parallel structure, and the control signals of the two branches are complementary. When the series branch is on, it is equivalent to a small resistance, and when the parallel branch is off, it is equivalent to a capacitor and a resistor in parallel. Attached Figure Description

[0018] The accompanying drawings, which are provided to further illustrate the present invention and form part of this application, do not constitute an undue limitation of the present invention. In the drawings:

[0019] Figure 1 This is a schematic diagram of the structural principle of a substation integrated automation testing system according to the present invention;

[0020] Figure 2 This is a schematic diagram of the signal conditioning module of this utility model.

[0021] Figure 3 This is a circuit diagram of the signal conditioning module of this utility model;

[0022] Figure 4 This is a schematic diagram of the filtering and gating module of this utility model;

[0023] Figure 5 This is a circuit diagram of the radio frequency switch circuit of this utility model. Detailed Implementation

[0024] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. The illustrative embodiments and descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0025] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present utility model, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the scope of protection of the present utility model.

[0026] A substation integrated automation testing system, such as Figure 1 As shown, the system includes a test interface module, a front-end data acquisition module, a data front-end preprocessing module, a microcontroller module, an RF switch circuit, a wireless RF chip, an alarm module, a human-machine interface module, a clock module, and a power supply module. The output of the test interface module is connected to the input of the front-end data acquisition module, the output of the front-end data acquisition module is connected to the input of the data front-end preprocessing module, and the output of the data front-end preprocessing module is connected to the input of the microcontroller module. The microcontroller module is connected to the wireless RF chip via the RF switch circuit, and the alarm module, human-machine interface module, clock module, and power supply module are each connected to the microcontroller module.

[0027] This invention utilizes a test interface module to access substation test data. Through signal conditioning and filtering modules, it improves the signal-to-noise ratio, spurious-free dynamic range, and common-mode rejection ratio of the test signal, achieving high-precision acquisition. An ADC acquisition module enables multi-channel parallel sampling, allowing the test data to safely and quickly enter the monitoring state and be uploaded to the microcontroller module for real-time data upload. This enables control and data storage of multiple test data sets, and the combined data is sent to the automated testing module for automated testing. This achieves automated test control using artificial intelligence, improving the efficiency of automated testing.

[0028] Preferred, such as Figure 2 As shown, the data front-end preprocessing module includes a signal conditioning module, a filtering and gating module, and an ADC acquisition module. The front-end data acquisition module is connected to the microcontroller module in sequence through the signal conditioning module, the filtering and gating module, and the ADC acquisition module.

[0029] Preferred, therefore Figure 3As shown, the signal conditioning module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first operational amplifier, a second operational amplifier, and a third operational amplifier. The signal input -IN terminal is connected to one end of the first resistor. The other end of the first resistor is connected to one end of the first capacitor, one end of the third resistor, and the negative power supply pin of the first operational amplifier. The other end of the first capacitor is connected to the other end of the third resistor and the output pin of the first operational amplifier. The signal input +IN terminal is connected to one end of the second resistor. The other end of the second resistor is connected to the positive power supply pin of the first operational amplifier and one end of the fourth resistor. One end of the first operational amplifier is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the other end of the fourth resistor and grounded. The output pin of the first operational amplifier is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to the positive power supply pin of the second operational amplifier. The negative power supply pin of the second operational amplifier is connected to the negative power supply pin of the third operational amplifier. The positive power supply pin of the third operational amplifier is connected to one end of the eighth resistor and one end of the ninth resistor, respectively. The other end of the ninth resistor is grounded. The other end of the eighth resistor is connected to one end of the seventh resistor and one end of the second operational amplifier, respectively. The other end of the seventh resistor is connected to one end of the fourth capacitor, and the other end of the fourth capacitor is connected to one end of the ninth resistor, respectively. The other end of the ninth resistor is connected to one end of the third capacitor, and the other end of the third capacitor is grounded.

[0030] The signal conditioning module amplifies and filters the data before inputting it into the signal conversion circuit, greatly reducing signal noise and signal loss during measurement. The amplification circuit consists of an OPA277 operational amplifier and resistors and capacitors, which is a typical differential amplifier circuit. Meanwhile, C3 and R6, C4 and R7 form a low-pass filter, and two OPA277 operational amplifiers form a dual op-amp band-pass filter. The Q value and center frequency of the band-pass filter are adjustable. Adjusting R9 can adjust the resonant frequency of the circuit, and adjusting R8 can adjust the Q value of the circuit. It is worth noting that the signal output is sent to the signal processing circuit and then input to the AD7794 for digital-to-analog conversion, converting the analog signal into a digital signal, which is beneficial for long-distance wireless signal transmission.

[0031] Preferred, such as Figure 4 As shown, the filtering and gating module includes an anti-aliasing filter unit and a signal gating unit connected in sequence. The signal conditioning module is connected to the ADC acquisition module through the anti-aliasing filter unit and the signal gating unit in sequence. The chip model of the anti-aliasing filter unit is OPA2277, and the chip model of the signal gating unit is ADG1634BCPZ.

[0032] like Figure 5As shown, the radio frequency (RF) switch circuit includes an RF terminal, a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, a fourth NMOS transistor Q4, a fifth NMOS transistor Q5, and a sixth NMOS transistor Q6; a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12; a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, and a sixth diode D6; an RF ANT terminal; a voltage VCTRL terminal; and a voltage VCTRI terminal. The RF terminal is connected to one end of the fifth resistor R5, one end of the seventh resistor R7, the drain of the third NMOS transistor Q3, and the drain of the fourth NMOS transistor Q4. The other end of the fifth resistor R5 is connected to the source of the third NMOS transistor Q3 and the second NMOS transistor Q4. The drain of Q2 and one end of the third resistor R3 are connected. The other end of the third resistor R3 is connected to the source of the second NMOS transistor Q2, the drain of the first NMOS transistor Q1, and one end of the first resistor R1. The other end of the first resistor R1 is connected to the source of the first NMOS transistor Q1 and grounded. The base of the first NMOS transistor Q1 is connected to the anode of the first diode. The cathode of the first diode is connected to the gate of the first NMOS transistor Q1 and one end of the second resistor R2. The other end of the second resistor R2 is connected to one end of the fourth resistor R4 and the voltage VCTRI terminal. One end of the sixth resistor R6 is connected to the gate of the second NMOS transistor Q2 and the cathode of the second diode D2. The anode of the second diode D2 is connected to the base of the second NMOS transistor Q2. The other end of the sixth resistor R6 is connected to the gate of the third NMOS transistor Q3 and the cathode of the third diode D3. The anode of the third diode D3 is connected to the base of the third NMOS transistor Q3.The gate of the fourth NMOS transistor Q4 is connected to the cathode of the fourth diode D4 and one end of the eighth resistor R8. The other end of the seventh resistor R7 is connected to the source of the fourth NMOS transistor Q4, the drain of the fifth NMOS transistor Q5, and one end of the ninth resistor R9. The gate of the fifth NMOS transistor Q5 is connected to one end of the tenth resistor R10 and the cathode of the fifth diode D5. The anode of the fifth diode D5 is connected to the base of the fifth diode D5. The source of the fifth NMOS transistor Q5 is connected to the other end of the ninth resistor R9, one end of the eleventh resistor R11, and the drain of the sixth NMOS transistor Q6. The gate of the sixth NMOS transistor Q6 is connected to one end of the twelfth resistor R12 and the cathode of the sixth diode D6. The anode of the sixth diode D6 is connected to the base of the sixth diode D6. The other end of the twelfth resistor R12 is connected to the other end of the eighth resistor R8. The other end of the tenth resistor R10 is connected to the voltage VCTRL terminal. The source of the sixth NMOS transistor Q6 is connected to the other end of the eleventh resistor R11 and the RF ANT terminal.

[0033] This utility model of RF switch circuit can better meet the needs of large voltage swing operation while ensuring insertion loss and isolation. It improves the traditional stacking technology, reduces uneven voltage distribution, significantly improves the branch voltage handling capability, and improves the branch voltage tolerance, thus better serving antenna tuning and ensuring normal operation even under antenna mismatch conditions. The RF switch section adopts a series-parallel structure, and the control signals of the two branches are complementary. When the series branch is on, it is equivalent to a small resistance, and when the parallel branch is off, it is equivalent to a capacitor and a resistor in parallel.

[0034] The wireless radio frequency chip used is the nRF905 wireless transceiver chip. The nRF905 is a long-range wireless transceiver chip with multiple transmitting points, long transmission distance, and strong anti-interference capabilities. It operates in three ISM bands: 433 / 868 / 915MHz, with a switching time between transmit and receive modes of less than 650µs. Ports such as TRX_CE, PWR_UP, TXEN, CSN, SCK, MISO, and MOSI are connected to the microcontroller. CSN, SCK, MISO, and MOSI form an SPI interface. When transmitting data, the nRF905 is set to transmit mode. The microcontroller writes the receiver address and valid data into the chip's buffer via the SPI interface, then generates a CRC and preamble using the TRX_CE level, and transmits the data. When receiving data, the nRF905 is set to receive mode, waiting for data arrival. Upon receiving the preamble, valid address, and CRC, the data is stored in a register, generating an interrupt that prompts the microcontroller to read it.

[0035] Preferably, the data storage module uses ST's S25FL128P Flash memory for real-time storage, with a storage capacity of 128Mbit. It communicates with an external controller via an SPI interface, and the maximum clock frequency of the interface can reach 104MHz.

[0036] Preferably, the human-computer interaction module includes an input unit and an output unit, the input unit being electrically connected to the output unit and the controller module; the input unit includes a keyboard or a touch screen; and the output unit includes a display screen.

[0037] The above description is only a preferred embodiment of the present utility model. Therefore, all equivalent changes or modifications made to the structure, features and principles described in the claims of the present utility model patent application are included in the scope of the present utility model patent application.

[0038] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless defined as herein.

[0039] The above embodiments are merely illustrative of the technical concept of this utility model and should not be construed as limiting the scope of protection of this utility model. Any modifications made to the technical solution based on the technical concept proposed in this utility model shall fall within the scope of protection of this utility model. The implementation methods of this utility model have been described in detail above, but this utility model is not limited to the above-described implementation methods. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this utility model.

Claims

1. A substation integrated automation testing system, characterized in that: The device includes a test interface module, a front-end data acquisition module, a data front-end preprocessing module, a microcontroller module, an RF switch circuit, a wireless RF chip, an alarm module, a human-machine interface module, a clock module, and a power supply module. The output of the test interface module is connected to the input of the front-end data acquisition module, the output of the front-end data acquisition module is connected to the input of the data front-end preprocessing module, and the output of the data front-end preprocessing module is connected to the input of the microcontroller module. The microcontroller module is connected to the wireless RF chip via the RF switch circuit, and the alarm module, human-machine interface module, clock module, and power supply module are each connected to the microcontroller module.

2. The substation integrated automation testing system according to claim 1, characterized in that: The data front-end preprocessing module includes a signal conditioning module, a filtering and gating module, and an ADC acquisition module. The front-end data acquisition module is connected to the microcontroller module in sequence through the signal conditioning module, the filtering and gating module, and the ADC acquisition module.

3. The substation integrated automation testing system according to claim 2, characterized in that: The signal conditioning module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first operational amplifier, a second operational amplifier, and a third operational amplifier. The signal input -IN terminal is connected to one end of the first resistor. The other end of the first resistor is connected to one end of the first capacitor, one end of the third resistor, and the negative power supply pin of the first operational amplifier. The other end of the first capacitor is connected to the other end of the third resistor and the output pin of the first operational amplifier. The signal input +IN terminal is connected to one end of the second resistor. The other end of the second resistor is connected to the positive power supply pin of the first operational amplifier and one end of the fourth resistor. One end of the second capacitor is connected to the other end of the fourth resistor and grounded. The output pin of the first operational amplifier is connected to one end of the fifth resistor. The other end of the fifth resistor is connected to the positive power supply pin of the second operational amplifier. The negative power supply pin of the second operational amplifier is connected to the negative power supply pin of the third operational amplifier. The positive power supply pin of the third operational amplifier is connected to one end of the eighth resistor and one end of the ninth resistor. The other end of the ninth resistor is grounded. The other end of the eighth resistor is connected to one end of the seventh resistor and the output pin of the second operational amplifier. The other end of the seventh resistor is connected to one end of the fourth capacitor. The other end of the fourth capacitor is connected to one end of the ninth resistor. The other end of the ninth resistor is connected to one end of the third capacitor. The other end of the third capacitor is grounded.

4. The substation integrated automation testing system according to claim 2, characterized in that: The filtering and gating module includes an anti-aliasing filter unit and a signal gating unit connected in sequence. The signal conditioning module is connected to the ADC acquisition module through the anti-aliasing filter unit and the signal gating unit in sequence. The anti-aliasing filter unit is equipped with an OPA2277 chip, and the signal gating unit is equipped with an ADG1634BCPZ chip.

5. The substation integrated automation testing system according to claim 2, characterized in that: The radio frequency (RF) switch circuit includes an RF terminal, a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, a fourth NMOS transistor Q4, a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, an RF ANT terminal, and a voltage V. CTRL Terminal and voltage V CTRI The RF terminals are connected to one end of the fifth resistor R5, one end of the seventh resistor R7, the drain of the third NMOS transistor Q3, and the drain of the fourth NMOS transistor Q4. The other end of the fifth resistor R5 is connected to the source of the third NMOS transistor Q3, the drain of the second NMOS transistor Q2, and one end of the third resistor R3. The other end of the third resistor R3 is connected to the source of the second NMOS transistor Q2, the drain of the first NMOS transistor Q1, and one end of the first resistor R1. The other end of the first resistor R1 is connected to the source of the first NMOS transistor Q1 and grounded. The base of the first NMOS transistor Q1 is connected to the anode of the first diode. The cathode of the first diode is connected to the gate of the first NMOS transistor Q1 and one end of the second resistor R2. The other end of the second resistor R2 is connected to one end of the fourth resistor R4 and the voltage V. CTRI One end of the sixth resistor R6 and the other end of the fourth resistor R4 are connected to the gate of the second NMOS transistor Q2 and the cathode of the second diode D2, respectively. The anode of the second diode D2 is connected to the base of the second NMOS transistor Q2. The other end of the sixth resistor R6 is connected to the gate of the third NMOS transistor Q3 and the cathode of the third diode D3, respectively. The anode of the third diode D3 is connected to the base of the third NMOS transistor Q3. The gate of the fourth NMOS transistor Q4 is connected to the cathode of the fourth diode D4. One end of the eighth resistor R8 and the other end of the seventh resistor R7 are connected to the source of the fourth NMOS transistor Q4, the drain of the fifth NMOS transistor Q5, and the... One end of resistor R9 is connected to the gate of the fifth NMOS transistor Q5, which is connected to one end of the tenth resistor R10 and the cathode of the fifth diode D5. The anode of the fifth diode D5 is connected to its base. The source of the fifth NMOS transistor Q5 is connected to the other end of resistor R9, one end of resistor R11, and the drain of the sixth NMOS transistor Q6. The gate of the sixth NMOS transistor Q6 is connected to one end of resistor R12 and the cathode of the sixth diode D6. The anode of the sixth diode D6 is connected to its base. The other end of resistor R12 is connected to the other end of resistor R8. The other end of resistor R10 is connected to voltage V. CTRL The source of the sixth NMOS transistor Q6 is connected to the other end of the eleventh resistor R11 and the RF ANT terminal, respectively.

6. The substation integrated automation testing system according to claim 1, characterized in that: It also includes a data storage module, which uses ST's S25FL128P Flash memory for real-time storage with a storage capacity of 128Mbit. It communicates with an external controller through an SPI interface with a maximum clock frequency of 104MHz.

7. The substation integrated automation testing system according to claim 1, characterized in that: The human-computer interaction module includes an input unit and an output unit. The input unit is electrically connected to the output unit and the controller module.

8. The substation integrated automation testing system according to claim 7, characterized in that: The input unit includes a keyboard or a touchscreen.

9. A substation integrated automation testing system according to claim 7, characterized in that: The output unit includes a display screen.

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