Three-terminal LDO chip aging test device

Abstract

The utility model provides a three-terminal LDO chip aging test device, and belongs to the technical field of chip testing. The aging test device for the three-terminal LDO chip comprises an aging test module used for outputting an aging analog signal, the aging test module comprises a three-terminal LDO chip to be tested, a voltage follower and a test sampling resistor which are sequentially connected in series, and the input end of the three-terminal LDO chip to be tested is connected with an input voltage; the output end of the to-be-tested three-end LDO chip is connected with the positive input end of the voltage follower, the negative input end of the voltage follower is connected with the output end of the voltage follower, the output end of the voltage follower is connected with one end of the test sampling resistor, and the other end of the test sampling resistor outputs an aging analog signal. When the aging test device for the three-terminal LDO chip is used for performing aging test on the three-terminal LDO chips with different parameters, the acquired output voltage can be ensured to be stable, the aging test conditions are unified, and the accuracy of the aging test result is ensured.

Description

Technical Field

[0001] This utility model relates to the field of chip testing technology, and in particular to a three-terminal LDO chip aging test device. Background Technology

[0002] Three-terminal LDO (Low-dropout regulator) chips, also known as "low-dropout linear regulators," typically undergo aging tests before being delivered for use. These tests assess their reliability and durability in real-world applications. The aging test simulates the long-term operating conditions of the three-terminal LDO chip, acquiring aging data during the testing process. Analyzing this data helps manufacturers understand the chip's performance after long-term use, thereby ensuring stable operation of the product in practical applications.

[0003] In the existing three-terminal LDO chip aging test: First, the same test sampling resistor is connected in series with the three-terminal LDO chip under test; second, the same external voltage is applied to the test sampling resistor; finally, by collecting the resistance value of the test sampling resistor, the collected voltage is obtained and checked back to analyze the chip performance.

[0004] However, when existing three-terminal LDO chip aging test equipment performs aging tests on different three-terminal LDO chips, the voltage in the input test sampling resistor varies due to differences in chip parameters, which in turn affects the accuracy of the aging test results. Utility Model Content

[0005] One objective of this invention is to solve the problem that when existing three-terminal LDO chip aging test devices perform aging tests on three-terminal LDO chips, the voltage at the input sampling test resistor varies due to differences in the parameters of the three-terminal LDO chips, thus affecting the accuracy of the aging test results.

[0006] Specifically, embodiments of this application provide a three-terminal LDO chip aging test apparatus, comprising:

[0007] An aging test module is used to output an aging simulation signal. The aging test module includes a three-terminal LDO chip under test, a voltage follower, and a test sampling resistor connected in series. The input terminal of the three-terminal LDO chip under test is connected to the input voltage. The output terminal of the three-terminal LDO chip under test is connected to the positive input terminal of the voltage follower. The negative input terminal of the voltage follower is connected to the output terminal of the voltage follower. The output terminal of the voltage follower is connected to one end of the test sampling resistor. The other end of the test sampling resistor outputs the aging simulation signal.

[0008] Furthermore, the three-terminal LDO chip aging test device also includes:

[0009] An ADC module, the input of which is connected to the other end of the sampling test resistor, is used to convert the aging analog signal into a digital signal;

[0010] A data processing module, connected to the ADC module, is used to receive digital signals transmitted by the ADC module and process the digital signals; and

[0011] The data display module is connected to the data processing module and is used to display the data processed by the data processing module.

[0012] Furthermore, the output terminal of the voltage follower is connected to a capacitor and then grounded.

[0013] Furthermore, the aging test module in the three-terminal LDO chip aging test device is in multiple groups, and the multiple groups of aging test modules are connected in parallel. The ADC module has multiple acquisition channels, and each group of aging test modules corresponds to one acquisition channel.

[0014] Furthermore, the three-terminal LDO chip aging test device also includes a power supply module that provides power to the ADC module, the data processing module, and the data display module.

[0015] Furthermore, the power module includes a voltage regulator chip and multiple filter capacitors.

[0016] Furthermore, the data processing module includes a processor, which includes a clock module for providing an external clock to the processor and a reset module for providing fault self-repair to the processor.

[0017] Furthermore, a fuse is connected in series between the input voltage and the input terminal of the three-terminal LDO chip under test.

[0018] The beneficial effects of this utility model are:

[0019] 1. By connecting a voltage follower in series at the output of the three-terminal LDO chip under test, the power consumption of the circuit can be reduced, and the output voltage can be kept stable when testing three-terminal LDO chips with different parameters. This ensures the uniformity of aging test conditions and guarantees the accuracy of aging test results.

[0020] 2. By setting up an ADC module, a data processing module, and a data display module in the three-terminal LDO chip aging test device, the data acquired by the aging test module is displayed intuitively in the data display module, making it convenient for users to analyze the relevant data.

[0021] 3. The three-terminal LDO chip aging test device of this utility model includes multiple sets of aging test modules connected in parallel, and the ADC chip in the ADC module includes multiple acquisition channels. Each aging test module corresponds to one acquisition channel. This allows for simultaneous testing of multiple three-terminal LDO chips under test, improving testing efficiency. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a set of aging test modules according to an embodiment of the present invention;

[0023] Figure 2 This is a structural connection diagram of a three-terminal LDO chip aging test device according to an embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram showing multiple aging test modules connected in parallel to an ADC module according to one embodiment of the present invention.

[0025] In the picture:

[0026] 1- Three-terminal LDO chip under test; 2- Aging test module; 3- ADC module; 4- Data processing module; 5- Data display module; 6- Power supply module. Detailed Implementation

[0027] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0028] The terms “comprising” and “having”, and any variations thereof, used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0029] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0030] like Figure 1 As shown, the three-terminal LDO chip aging test device of this utility model includes an aging test module 2 for outputting an aging simulation signal. The aging test module 2 includes a three-terminal LDO chip under test 1, a voltage follower U1, and a test sampling resistor R1 connected in series. The input terminal of the three-terminal LDO chip under test 1 is connected to an input voltage. The output terminal of the three-terminal LDO chip under test 1 is connected to the positive input terminal of the voltage follower U1. The negative input terminal of the voltage follower U1 is connected to the output terminal of the voltage follower U1. The output terminal of the voltage follower U1 is connected to one end of the test sampling resistor R1. The other end of the test sampling resistor outputs the aging simulation signal.

[0031] By connecting a voltage follower U in series at the output of the three-terminal LDO chip 1 under test, the power consumption of the circuit can be reduced. At the same time, when testing three-terminal LDO chips with different parameters, the collected output voltage can be kept stable, the aging test conditions can be unified, and the accuracy of the aging test results can be guaranteed.

[0032] The workflow of the above-mentioned aging test module 2 is as follows: the external power supply provides VCC voltage, the voltage passes through the three-terminal LDO chip 1 under test and flows into the voltage follower U1, and finally flows into the test sampling resistor R1, sending the aging simulation signal to the next process.

[0033] like Figure 2 As shown, in one embodiment, the aging test device of this utility model further includes an ADC module 3, a data processing module 4, and a data display module 5. The input terminal of the ADC module 3 is connected to the other end of the sampling test resistor R1, and the ADC module 3 is used to convert the aging analog signal into a digital signal. The data processing module 4 is connected to the ADC module 3 and is used to receive the digital signal transmitted by the ADC module 3 and process the digital signal. The data display module 5 is connected to the data processing module 4 and is used to display the data processed by the data processing module 4 for user analysis of the acquired voltage.

[0034] The data acquired by the aging test module 2 is analyzed through the ADC module 3, data processing module 4, and data display module 5, and displayed intuitively in the data display module 5, making it convenient for users to analyze the relevant data.

[0035] In one embodiment, the processor in data processing module 4 uses an STM32F103C8T6, and the voltage range it acquires is 0-3.3V. If the voltage acquired and displayed by data display module 5 exceeds the normal voltage range of the three-terminal LDO chip under test, the three-terminal LDO chip under test is determined to be abnormally faulty. The processor in data processing module 5 controls the read / write status of the display screen in data display module 5 through its output pins.

[0036] In one embodiment, the output of voltage follower U1 is connected to capacitor C1 and then grounded to improve the transient characteristics of the aging test module.

[0037] This utility model discloses a three-terminal LDO chip aging test device comprising multiple sets of aging test modules 2 connected in parallel. The ADC module 3 includes one or more ADC chips, each ADC chip having multiple acquisition channels. Each set of aging test modules 2 corresponds to one acquisition channel. This configuration allows for simultaneous testing of multiple three-terminal LDO chips, improving testing efficiency. Furthermore, because the multiple sets of aging test modules 2 are connected in parallel, a failure in one set of aging test modules 2 will not affect the normal operation of the other sets.

[0038] like Figure 3 As shown, in one embodiment, each ADC chip in ADC module 3 has 4 acquisition channels. The 4 acquisition channels in each ADC chip correspond to 4 sets of aging test modules 2. For example, if the number of three-terminal LDO chips 1 under test is 64, the number of aging test modules 2 is 64, requiring 16 ADC chips. In practical applications, the number of channels in the ADC chip can be switched as needed, for example, using an 8-channel ADC chip, selected according to the number of three-terminal LDO chips to be tested. Considering the cost-effectiveness of ADC chips, ADC chips with more channels can be selected based on device cost, which will not be elaborated further here.

[0039] The three-terminal LDO chip aging test device of this invention also includes a power supply module 6 that provides power to the ADC module 3, data processing module 4, and data display module 5. The power supply module 6 includes a voltage regulator chip and multiple filter capacitors. In one embodiment, the number of filter capacitors is four. Through the power supply module 6, VCC is converted to a 3.3V operating voltage, providing a stable input voltage to the ADC module 3, data processing module 4, and data display module 5.

[0040] In one embodiment, the processor includes a clock module for providing an external clock to the processor and a reset module for providing fault self-healing for the processor.

[0041] To prevent short circuits in the internal circuitry of the aging test module during long-term aging tests, which could cause the three-terminal LDO chip under test (DUT) to overheat and burn out, in one embodiment, a fuse F1 is connected in series between the input voltage VCC and the input terminal of the DUT chip 1.

[0042] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A three-terminal LDO chip aging test device, characterized in that, include: An aging test module is used to output an aging simulation signal. The aging test module includes a three-terminal LDO chip under test, a voltage follower, and a test sampling resistor connected in series. The input terminal of the three-terminal LDO chip under test is connected to the input voltage. The output terminal of the three-terminal LDO chip under test is connected to the positive input terminal of the voltage follower. The negative input terminal of the voltage follower is connected to the output terminal of the voltage follower. The output terminal of the voltage follower is connected to one end of the test sampling resistor. The other end of the test sampling resistor outputs the aging simulation signal.

2. The three-terminal LDO chip aging test apparatus according to claim 1, characterized in that, Also includes: An ADC module, the input of which is connected to the other end of the test sampling resistor, is used to convert the aging analog signal into a digital signal; A data processing module, connected to the ADC module, is used to receive digital signals transmitted by the ADC module and process the digital signals. and The data display module is connected to the data processing module and is used to display the data processed by the data processing module.

3. The three-terminal LDO chip aging test apparatus according to claim 1, characterized in that, The output terminal of the voltage follower is connected to a capacitor and then grounded.

4. The three-terminal LDO chip aging test apparatus according to claim 2, characterized in that, The number of aging test modules is multiple, and the multiple groups of aging test modules are connected in parallel. The number of acquisition channels in the ADC module is multiple, and each group of aging test modules corresponds to one acquisition channel.

5. The three-terminal LDO chip aging test apparatus according to claim 2, characterized in that, It also includes a power supply module that provides power to the ADC module, the data processing module and the data display module.

6. The three-terminal LDO chip aging test apparatus according to claim 5, characterized in that, The power module includes a voltage regulator chip and multiple filter capacitors.

7. The three-terminal LDO chip aging test apparatus according to claim 2, characterized in that, The data processing module includes a processor, which includes a clock module for providing an external clock to the processor and a reset module for providing fault self-repair to the processor.

8. The three-terminal LDO chip aging test apparatus according to any one of claims 1 to 7, characterized in that, A fuse is connected in series between the input voltage and the input terminal of the three-terminal LDO chip under test.

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