USB charging circuit for instrument panel

Abstract

The utility model provides a USB charging circuit for an instrument panel, which is characterized in that the USB charging circuit comprises a USB socket, an SOC chip and a USB charging management chip, the signal transmission end of the USB socket is connected with the first contact end of a common mode inductor, the second contact end of the common mode inductor is connected with the signal transmission end of the USB charging management chip, and the signal transmission end of the USB socket is connected with the signal transmission end of the SOC chip. A first contact end of the common mode inductor is provided with a USB data positive signal line and a USB data negative signal line, the USB data positive signal line and the USB data negative signal line are both connected with a bidirectional TVS tube, and the other end of the bidirectional TVS tube is grounded; the signal transmission end of the USB charging management chip is connected with the signal transmission end of the SOC chip. According to the USB charging circuit for the instrument panel, the risk of distraction caused by searching or operating the USB interface is reduced. Therefore, the concentration degree of the driver can be kept, and the safety in the driving process can be improved.

Description

Technical Field

[0001] This utility model relates to a USB charging circuit, and more particularly to a USB charging circuit for a dashboard. Background Technology

[0002] As the core of the vehicle's infotainment and control system, the central control system's USB port is located in the center between the driver and front passenger seats. However, the driver operating the USB port while driving increases safety risks. Therefore, there is an urgent need for a USB port designed on the dashboard. A dashboard-mounted USB port would be convenient for the driver to operate while driving, thus reducing the risk of distraction from searching for or operating the USB port. Utility Model Content

[0003] This utility model aims to at least solve the technical problems existing in the prior art, and in particular, innovatively proposes a USB charging circuit for dashboards.

[0004] To achieve the above-mentioned objectives of this utility model, this utility model provides a USB charging circuit for an instrument panel, including a USB socket, a SOC chip, and a USB charging management chip. The signal transmission end of the USB socket is connected to the first contact end of a common-mode inductor, and the second contact end of the common-mode inductor is connected to the signal transmission end of the USB charging management chip. The first contact end of the common-mode inductor has a USB positive data signal line and a USB negative data signal line. A bidirectional TVS diode is connected to both the USB positive data signal line and the USB negative data signal line, and the other end of the bidirectional TVS diode is grounded.

[0005] The signal transmission terminal of the USB charging management chip is connected to the signal transmission terminal of the SOC chip.

[0006] When a USB charging management chip is connected to a USB interface, the bidirectional TVS diode and common-mode inductor in the USB interface play a crucial role in protecting the circuit from electrostatic interference and electromagnetic interference. Furthermore, the bidirectional transient diode provides protection under both forward and reverse voltage conditions.

[0007] Furthermore, the signal transmission terminal of the USB charging management chip is connected to the signal transmission terminal of the SOC chip, including:

[0008] The power input terminal IN of the USB charging management chip U13, the first terminal of capacitor CP518, and the first terminal of capacitor CP516 are connected to the +5VSW power supply. The second terminals of capacitors CP518 and CP516 are connected to the power ground. The negative data output terminal DM_OUT of the USB charging management chip U13 is connected to the first terminal of resistor RB65, and the second terminal of resistor RB65 is connected to the negative signal terminal of the USB data line of the SOC chip. The positive data output terminal DP_OUT of the USB charging management chip U13 is connected to the first terminal of resistor RB66, and the second terminal of resistor RB66 is connected to the positive signal terminal of the USB data line of the SOC chip. The following connections are made: The STATUS output terminal of the USB charging management chip U13 is connected to the first terminals of resistors RP10 and RP8; the second terminal of resistor RP8 is connected to the USB charging status output terminal of the SOC chip. The FAULT output terminal of the USB charging management chip U13 is connected to the first terminals of resistors RP4 and RP5; the second terminal of resistor RP5 is connected to the USB system fault terminal of the SOC chip. The ILIM_SEL current detection selection terminal of the USB charging management chip U13 is connected to the first terminal of resistor RP6; the second terminal of resistor RP6 is connected to the USB port current limiting terminal of the SOC chip. The enable terminal EN of the USB charging management chip U13 is connected to the first terminals of resistors RP3 and RP9, and the second terminal of resistor RP9 is connected to the USB power enable terminal of the SOC chip. The control input terminal CTL1 of the USB charging management chip U13 is connected to the first terminals of resistors RP2, RP16, and RP11, and the second terminal of resistor RP11 is connected to the USB control logic input terminal of the SOC chip. The control input terminal CTL2 of the USB charging management chip U13 is connected to the first terminals of resistors RP1, RP17, and RP12, and the second terminal of resistor RP12 is connected to the first terminal of resistor RP12. The two terminals are connected to the USB control logic input terminal of the SOC chip; the control input terminal CTL3 of the USB charging management chip U13 is connected to the first terminal of resistor RP7, the first terminal of resistor RP18, and the first terminal of resistor RP15; the second terminal of resistor RP15 is connected to the USB control logic input terminal of the SOC chip; the second terminals of resistors RP10, RP4, RP3, RP2, RP1, and RP7 are connected to the +3.3VSW power supply; the second terminals of resistors RP16, RP17, and RP18 are connected to the power supply ground.

[0009] The power switch output terminal OUT of the USB charging management chip U13 outputs power USB1_+5V;

[0010] The positive data input terminal DP_IN of the USB charging management chip U13 is connected to the first output terminal of the common-mode inductor LL1; the negative data input terminal DM_IN of the USB charging management chip U13 is connected to the second output terminal of the common-mode inductor LL1; the ground terminal GND of the USB charging management chip U13 is connected to the power supply ground; the low current limit threshold setting terminal ILIM_LO of the USB charging management chip U13 is connected to the first terminal of the resistor RP14; the high current limit threshold setting terminal ILIM_HI of the USB charging management chip U13 is connected to the first terminal of the resistor RP13; the second terminals of the resistors RP13 and RP14 are connected to the power supply ground; the heat dissipation terminal Exposed PAD of the USB charging management chip U13 is connected to the power supply ground. The positive data input terminal DP_IN and the negative data input terminal DM_IN can also be used as data output terminals, in which case the positive data input terminal DP_OUT and the negative data output terminal DM_OUT are data input terminals.

[0011] Furthermore, the power switch output terminal OUT of the USB charging management chip U13 is also connected to the power filtering circuit:

[0012] The power switch output terminal OUT of the USB charging management chip U13 outputs power USB1_+5V, which is connected to the first terminal of capacitor CP1, the first terminal of capacitor CP2, and the positive terminal of polarized capacitor C169. The second terminal of capacitor CP1, the second terminal of capacitor CP2, and the negative terminal of polarized capacitor C169 are connected to the power ground.

[0013] The positive data input terminal DP_IN of the USB charging management chip U13 is connected to the first output terminal of the common-mode inductor LL1; the negative data input terminal DM_IN of the USB charging management chip U13 is connected to the second output terminal of the common-mode inductor LL1; the ground terminal GND of the USB charging management chip U13 is connected to the power supply ground; the low current limit threshold setting terminal ILIM_LO of the USB charging management chip U13 is connected to the first terminal of the resistor RP14; the high current limit threshold setting terminal ILIM_HI of the USB charging management chip U13 is connected to the first terminal of the resistor RP13; the second terminals of the resistors RP13 and RP14 are connected to the power supply ground; the heat dissipation terminal Exposed PAD of the USB charging management chip U13 is connected to the power supply ground. The positive data input terminal DP_IN and the negative data input terminal DM_IN can also be used as data output terminals, in which case the positive data input terminal DP_OUT and the negative data output terminal DM_OUT are data input terminals.

[0014] Furthermore, the signal transmission terminal of the USB socket is connected to the first contact terminal of the common-mode inductor, and the second contact terminal of the common-mode inductor is connected to the signal transmission terminal of the USB charging management chip. The first contact terminal of the common-mode inductor has a USB positive data signal line and a USB negative data signal line. Both the USB positive and negative data signal lines are connected to a bidirectional TVS diode, and the other end of the bidirectional TVS diode is grounded. This includes:

[0015] The first input terminal of the common-mode inductor LL1 is connected to the third terminal of the USB interface J14 and the first terminal of the transient diode LTV13; the second input terminal of the common-mode inductor LL1 is connected to the fourth terminal of the USB interface J14 and the first terminal of the transient diode LTV12; the second terminals of the transient diode LTV12 and LTV13, and the first terminal of the capacitor C143 are connected to the power supply ground; the second terminal of the capacitor C143 and the first terminal of the USB interface J14 are connected to the power supply USB1_+5V; the second terminal of the USB interface J14 is connected to the power supply ground; where the USB socket is the USB interface.

[0016] The data source for USB interface J14 is an external USB flash drive or an internal SOC chip, which is transmitted to the external USB flash drive or internal circuitry via the charging management chip U13.

[0017] The transient diode is preferably a bidirectional transient diode, providing protection under both forward and reverse voltages. The USB interface needs to transmit data and supply power, thus it may be exposed to voltage surges from different directions. When the USB charging management chip is connected to the USB interface, the bidirectional TVS diode and common-mode inductor in the USB interface play a crucial role in protecting the circuit from electrostatic and electromagnetic interference. The inclusion of these components improves the circuit's anti-interference capability and stability, ensuring smooth USB charging.

[0018] Furthermore, the SOC chip is also connected to the MCU chip and the FLAH chip:

[0019] The crystal output terminal of SOC chip U6 is connected to the first terminal of resistor RM502, the third terminal of crystal Y1, and the first terminal of capacitor C45. The second terminal of resistor RM502 is connected to the crystal input terminal of SOC chip U6, the first terminal of crystal Y1, and the first terminal of capacitor C44. The second terminals of capacitor C44, capacitor C45, and the fourth terminal of crystal Y1 are connected to the power supply ground. The second terminal of crystal Y1 is also connected to the power supply ground.

[0020] The reset terminal of the SOC chip U6 is connected to the first terminal of capacitor C43, the collector of transistor Q7, and the first terminal of resistor RB5. The second terminal of capacitor C43 and the emitter of transistor Q7 are connected to the power supply ground. The second terminal of resistor RB5 is connected to the power supply VDD33_IO. The base of transistor Q7 is connected to the first terminal of resistor R131, and the second terminal of resistor R131 is connected to the reset control terminal of the MCU chip. Transistor Q7 is an NPN transistor.

[0021] SOC chip U6 is also connected to FLAH: the data transmission terminal of FLAH chip U7 is connected to the data transmission terminal of SOC chip U6 through a resistor; the power input terminal of FLAH chip U7, the first terminal of resistor R132, and the first terminal of capacitor C48 are connected to power supply VDD33_IO; the second terminal of capacitor C48 is connected to power ground.

[0022] In addition to the SOC chip connecting to the USB charging management chip to receive external power and control the charging process via the USB interface, the MCU chip connects to the SOC chip, receives instructions from the SOC chip, and executes corresponding control tasks. The MCU chip may also communicate with external devices (such as computers, mobile phones, etc.) via the USB interface or other communication interfaces. The SOC chip connects to the FLASH chip to store the program code and configuration parameters of the SOC chip or MCU chip.

[0023] Furthermore, it also includes the internal power supply circuit of the SOC chip, which includes the SOC first part internal power supply circuit, the SOC second part internal power supply circuit and the SOC third part internal power supply circuit.

[0024] The first internal power supply circuit converts the +1.2V power supply to VDD1V2_CORE, the second internal power supply circuit converts the +1.8V power supply to +1.8V_MCU, and the third internal power supply circuit converts the +3.3VSW power supply to VDD33_IO.

[0025] Furthermore, the internal power supply circuit of the first part of the SOC includes: the first terminal of inductor L6 is connected to the +1.2V power supply; the second terminal of inductor L6 outputs power supply VDD1V2_CORE, and is connected to the first terminals of capacitors C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C60, C61, and C62; the second terminals of capacitors C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C60, C61, and C62 are connected to the power supply ground.

[0026] The internal power supply circuit of the second part of the SOC includes: the first terminal of inductor L8 is connected to the +1.8V power supply; the second terminal of inductor L8 outputs the +1.8V power supply to the MCU and is connected to the first terminals of capacitors C80, C81, C82, C83, and C84; the second terminals of capacitors C80, C81, C82, C83, and C84 are connected to the power supply ground.

[0027] The internal power supply circuit of the third part of the SOC includes: the first terminal of inductor L7 is connected to the +3.3VSW power supply; the second terminal of inductor L7 outputs power supply VDD33_IO and is connected to the first terminals of capacitors C65, C66, C67, C68, and C69; the second terminals of capacitors C65, C66, C67, C68, and C69 are connected to the power supply ground; in addition, the second terminal of inductor L7 can also be connected to the first terminals of capacitors C70, C71, C72, C73, C74, and C75; the second terminals of capacitors C70, C71, C72, C73, C74, and C75 are connected to the power supply ground.

[0028] Furthermore, the internal power supply circuitry of the third part of the SOC also includes three sub-power supply circuits: used to convert power supply VDD33_IO into power supply VDD3.3V_SAR, power supply VDD3V3A, and power supply VCC_RTC respectively.

[0029] The first sub-power supply circuit includes: power supply VDD33_IO is connected to the first terminal of resistor R39, the second terminal of resistor R39 outputs power supply VDD3.3V_SAR and is connected to the first terminal of capacitor C85 and the first terminal of capacitor C86, and the second terminal of capacitor C85 and the second terminal of capacitor C86 are connected to power supply ground.

[0030] The second sub-power supply circuit includes: power supply VDD33_IO is connected to the first end of resistor R40, the second end of resistor R40 outputs power supply VDD3V3A and is connected to the first end of capacitor C87, the first end of capacitor C88, and the first end of capacitor C89, and the second end of capacitor C87, the second end of capacitor C88, and the second end of capacitor C89 is connected to power supply ground.

[0031] The third sub-power supply circuit includes: power supply VDD33_IO is connected to the first end of resistor R41, the second end of resistor R41 outputs power supply VCC_RTC and is connected to the first end of capacitor CO5 and the first end of capacitor C90, and the second end of capacitor CO5 and the second end of capacitor C90 are connected to power supply ground.

[0032] The power supply +3.3VSW is converted to power supply VDD33_IO; the third part of the internal power supply circuit also includes: converting power supply VDD33_IO to power supply VDD3.3V_SAR, power supply VDD3V3A, and power supply VCC_RTC respectively.

[0033] In summary, by adopting the above technical solution, the USB charging circuit for the dashboard designed in this utility model reduces the risk of distraction caused by searching for or operating the USB port. This helps maintain the driver's focus and improves safety during driving. Furthermore, because the central control system integrates too many functions, it is susceptible to electromagnetic interference; designing the USB charging circuit on the dashboard can mitigate this problem to some extent.

[0034] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0035] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0036] Figure 1 This is a connection diagram of this utility model.

[0037] Figure 2 This is a circuit connection diagram of the USB charging management chip of this utility model.

[0038] Figure 3This is a schematic diagram of the circuit connection of the SOC chip of the present invention.

[0039] Figure 4 This is a schematic diagram of the internal power supply circuit connection of the SOC chip of the present invention. Detailed Implementation

[0040] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0041] The USB charging circuit structure for the instrument panel proposed in this utility model is as follows: Figure 1 As shown, it includes a USB socket, a SOC chip, and a USB charging management chip.

[0042] The signal transmission terminals of the USB charging management chip are connected to the signal transmission terminals of the USB socket and the SOC chip, respectively. The USB charging management chip is connected to the USB socket, and the USB charging management chip is connected to the SOC chip. Besides charging, this connection also enables functions such as data transmission and upgrades.

[0043] In addition, there is an audio playback function via USB flash drive. The USB flash drive is connected to the SOC chip, which decodes the audio signal and transmits the decoded audio to the DSP chip via I2S. The DSP chip then converts the audio back into an analog signal, which is then transmitted to the AMP chip for audio playback.

[0044] The circuit connection of the USB charging management chip is as follows: Figure 2 As shown:

[0045] The power input terminal IN of the USB charging management chip U13, the first terminal of capacitor CP518, and the first terminal of capacitor CP516 are connected to the +5VSW power supply. The second terminals of capacitors CP518 and CP516 are connected to the power ground. The negative data output terminal DM_OUT of the USB charging management chip U13 is connected to the first terminal of resistor RB65, and the second terminal of resistor RB65 is connected to the negative signal terminal of the USB data line of the SOC chip. The positive data output terminal DP_OUT of the USB charging management chip U13 is connected to the first terminal of resistor RB66, and the second terminal of resistor RB66 is connected to the positive signal terminal of the USB data line of the SOC chip. The following connections are made: The STATUS output terminal of the USB charging management chip U13 is connected to the first terminals of resistors RP10 and RP8; the second terminal of resistor RP8 is connected to the USB charging status output terminal of the SOC chip. The FAULT output terminal of the USB charging management chip U13 is connected to the first terminals of resistors RP4 and RP5; the second terminal of resistor RP5 is connected to the USB system fault terminal of the SOC chip. The ILIM_SEL current detection selection terminal of the USB charging management chip U13 is connected to the first terminal of resistor RP6; the second terminal of resistor RP6 is connected to the USB port current limiting terminal of the SOC chip. The enable terminal EN of the USB charging management chip U13 is connected to the first terminals of resistors RP3 and RP9, and the second terminal of resistor RP9 is connected to the USB power enable terminal of the SOC chip. The control input terminal CTL1 of the USB charging management chip U13 is connected to the first terminals of resistors RP2, RP16, and RP11, and the second terminal of resistor RP11 is connected to the USB control logic input terminal of the SOC chip. The control input terminal CTL2 of the USB charging management chip U13 is connected to the first terminals of resistors RP1, RP17, and RP12, and the second terminal of resistor RP12 is connected to the first terminal of resistor RP12. The two terminals are connected to the USB control logic input terminal of the SOC chip; the control input terminal CTL3 of the USB charging management chip U13 is connected to the first terminal of resistor RP7, the first terminal of resistor RP18, and the first terminal of resistor RP15; the second terminal of resistor RP15 is connected to the USB control logic input terminal of the SOC chip; the second terminals of resistors RP10, RP4, RP3, RP2, RP1, and RP7 are connected to the +3.3VSW power supply; the second terminals of resistors RP16, RP17, and RP18 are connected to the power supply ground.

[0046] The power switch output terminal OUT of the USB charging management chip U13 outputs power USB1_+5V, which is connected to the first terminal of capacitor CP1, the first terminal of capacitor CP2, and the positive terminal of polarized capacitor C169. The second terminal of capacitor CP1, the second terminal of capacitor CP2, and the negative terminal of polarized capacitor C169 are connected to the power ground.

[0047] The positive data input terminal DP_IN of the USB charging management chip U13 is connected to the first output terminal of the common-mode inductor LL1; the negative data input terminal DM_IN of the USB charging management chip U13 is connected to the second output terminal of the common-mode inductor LL1; the ground terminal GND of the USB charging management chip U13 is connected to the power supply ground; the low current limit threshold setting terminal ILIM_LO of the USB charging management chip U13 is connected to the first terminal of the resistor RP14; the high current limit threshold setting terminal ILIM_HI of the USB charging management chip U13 is connected to the first terminal of the resistor RP13; the second terminals of the resistors RP13 and RP14 are connected to the power supply ground; the heat dissipation terminal Exposed PAD of the USB charging management chip U13 is connected to the power supply ground. The positive data input terminal DP_IN and the negative data input terminal DM_IN can also be used as data output terminals, in which case the positive data input terminal DP_OUT and the negative data output terminal DM_OUT are data input terminals.

[0048] The USB charging management chip is connected to the USB interface:

[0049] The first input terminal of the common-mode inductor LL1 is connected to the third terminal of the USB interface J14 and the first terminal of the transient diode LTV13; the second input terminal of the common-mode inductor LL1 is connected to the fourth terminal of the USB interface J14 and the first terminal of the transient diode LTV12; the second terminals of the transient diode LTV12 and LTV13, and the first terminal of the capacitor C143 are connected to the power supply ground; the second terminal of the capacitor C143 and the first terminal of the USB interface J14 are connected to the power supply USB1_+5V; the second terminal of the USB interface J14 is connected to the power supply ground.

[0050] The data source for USB interface J14 is an external USB flash drive or an internal SOC chip, which is transmitted to the external USB flash drive or internal circuitry via the charging management chip U13.

[0051] The transient diode is preferably a bidirectional transient diode, providing protection under both forward and reverse voltages. The USB interface needs to transmit data and supply power, thus it may be exposed to voltage surges from different directions. When the USB charging management chip is connected to the USB interface, the bidirectional TVS diode and common-mode inductor in the USB interface play a crucial role in protecting the circuit from electrostatic and electromagnetic interference. The inclusion of these components improves the circuit's anti-interference capability and stability, ensuring smooth USB charging.

[0052] The USB charging management chip U13 has the model number PI5USB2546.

[0053] The circuit connection of the SOC chip is as follows Figure 3 As shown.

[0054] The crystal output terminal of SOC chip U6 is connected to the first terminal of resistor RM502, the third terminal of crystal Y1, and the first terminal of capacitor C45. The second terminal of resistor RM502 is connected to the crystal input terminal of SOC chip U6, the first terminal of crystal Y1, and the first terminal of capacitor C44. The second terminals of capacitor C44, capacitor C45, and the fourth terminal of crystal Y1 are connected to the power supply ground. The second terminal of crystal Y1 is also connected to the power supply ground.

[0055] The reset terminal of the SOC chip U6 is connected to the first terminal of capacitor C43, the collector of transistor Q7, and the first terminal of resistor RB5. The second terminal of capacitor C43 and the emitter of transistor Q7 are connected to the power supply ground. The second terminal of resistor RB5 is connected to the power supply VDD33_IO. The base of transistor Q7 is connected to the first terminal of resistor R131, and the second terminal of resistor R131 is connected to the reset control terminal of the MCU chip. Transistor Q7 is an NPN transistor.

[0056] SOC chip U6 is also connected to FLAH: the data transmission terminal of FLAH chip U7 is connected to the data transmission terminal of SOC chip U6 through a resistor; the power input terminal of FLAH chip U7, the first terminal of resistor R132, and the first terminal of capacitor C48 are connected to power supply VDD33_IO; the second terminal of capacitor C48 is connected to power ground.

[0057] The model number of the SOC chip U6 is ITE9866.

[0058] The internal power supply circuit connection of the SOC chip is as follows: Figure 4As shown, there are three internal power supply circuits that convert +1.2V to VDD1V2_CORE, +1.8V to +1.8V_MCU, and +3.3VSW to VDD33_IO. The third internal power supply circuit also includes converting VDD33_IO to VDD3.3V_SAR, VDD3V3A, and VCC_RTC.

[0059] The internal power supply circuit of the first part of the SOC includes: the first terminal of inductor L6 is connected to the +1.2V power supply; the second terminal of inductor L6 outputs power supply VDD1V2_CORE, and is connected to the first terminals of capacitors C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C60, C61, and C62; the second terminals of capacitors C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C60, C61, and C62 are connected to the power supply ground.

[0060] The internal power supply circuit of the second part of the SOC includes: the first terminal of inductor L8 is connected to the +1.8V power supply; the second terminal of inductor L8 outputs the +1.8V power supply to the MCU and is connected to the first terminals of capacitors C80, C81, C82, C83, and C84; the second terminals of capacitors C80, C81, C82, C83, and C84 are connected to the power supply ground.

[0061] The internal power supply circuit of the third part of the SOC includes: the first terminal of inductor L7 is connected to the +3.3VSW power supply; the second terminal of inductor L7 outputs power supply VDD33_IO and is connected to the first terminals of capacitors C65, C66, C67, C68, and C69; the second terminals of capacitors C65, C66, C67, C68, and C69 are connected to the power supply ground; in addition, the second terminal of inductor L7 can also be connected to the first terminals of capacitors C70, C71, C72, C73, C74, and C75; the second terminals of capacitors C70, C71, C72, C73, C74, and C75 are connected to the power supply ground.

[0062] The third part of the SOC's internal power supply circuit also includes three sub-power supply circuits:

[0063] The first sub-power supply circuit includes: power supply VDD33_IO is connected to the first terminal of resistor R39, the second terminal of resistor R39 outputs power supply VDD3.3V_SAR and is connected to the first terminal of capacitor C85 and the first terminal of capacitor C86, and the second terminal of capacitor C85 and the second terminal of capacitor C86 are connected to power supply ground.

[0064] The second sub-power supply circuit includes: power supply VDD33_IO is connected to the first end of resistor R40, the second end of resistor R40 outputs power supply VDD3V3A and is connected to the first end of capacitor C87, the first end of capacitor C88, and the first end of capacitor C89, and the second end of capacitor C87, the second end of capacitor C88, and the second end of capacitor C89 is connected to power supply ground.

[0065] The third sub-power supply circuit includes: power supply VDD33_IO is connected to the first end of resistor R41, the second end of resistor R41 outputs power supply VCC_RTC and is connected to the first end of capacitor CO5 and the first end of capacitor C90, and the second end of capacitor CO5 and the second end of capacitor C90 are connected to power supply ground.

[0066] The power supply +3.3VSW is converted to power supply VDD33_IO; the third part of the internal power supply circuit also includes: converting power supply VDD33_IO to power supply VDD3.3V_SAR, power supply VDD3V3A, and power supply VCC_RTC respectively.

[0067] Although embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A USB charging circuit for a dashboard, characterized in that, The device includes a USB socket, a SOC chip, and a USB charging management chip. The signal transmission end of the USB socket is connected to the first contact end of a common-mode inductor, and the second contact end of the common-mode inductor is connected to the signal transmission end of the USB charging management chip. The first contact end of the common-mode inductor has a USB positive data signal line and a USB negative data signal line. Both the USB positive data signal line and the USB negative data signal line are connected to a bidirectional TVS diode, and the other end of the bidirectional TVS diode is grounded. The signal transmission terminal of the USB charging management chip is connected to the signal transmission terminal of the SOC chip.

2. The USB charging circuit for an instrument panel according to claim 1, characterized in that, The signal transmission terminal of the USB charging management chip is connected to the signal transmission terminal of the SOC chip, including: The power input terminal IN of the USB charging management chip U13, the first terminal of capacitor CP518, and the first terminal of capacitor CP516 are connected to the +5VSW power supply. The second terminals of capacitors CP518 and CP516 are connected to the power ground. The negative data output terminal DM_OUT of the USB charging management chip U13 is connected to the first terminal of resistor RB65, and the second terminal of resistor RB65 is connected to the negative signal terminal of the USB data line of the SOC chip. The positive data output terminal DP_OUT of the USB charging management chip U13 is connected to the first terminal of resistor RB66, and the second terminal of resistor RB66 is connected to the positive signal terminal of the USB data line of the SOC chip. The following connections are made: The STATUS output terminal of the USB charging management chip U13 is connected to the first terminals of resistors RP10 and RP8; the second terminal of resistor RP8 is connected to the USB charging status output terminal of the SOC chip. The FAULT output terminal of the USB charging management chip U13 is connected to the first terminals of resistors RP4 and RP5; the second terminal of resistor RP5 is connected to the USB system fault terminal of the SOC chip. The ILIM_SEL current detection selection terminal of the USB charging management chip U13 is connected to the first terminal of resistor RP6; the second terminal of resistor RP6 is connected to the USB port current limiting terminal of the SOC chip. The enable terminal EN of the USB charging management chip U13 is connected to the first terminals of resistors RP3 and RP9, and the second terminal of resistor RP9 is connected to the USB power enable terminal of the SOC chip. The control input terminal CTL1 of the USB charging management chip U13 is connected to the first terminals of resistors RP2, RP16, and RP11, and the second terminal of resistor RP11 is connected to the USB control logic input terminal of the SOC chip. The control input terminal CTL2 of the USB charging management chip U13 is connected to the first terminals of resistors RP1, RP17, and RP12, and the second terminal of resistor RP12 is connected to the first terminal of resistor RP12. The two terminals are connected to the USB control logic input terminal of the SOC chip; the control input terminal CTL3 of the USB charging management chip U13 is connected to the first terminal of resistor RP7, the first terminal of resistor RP18, and the first terminal of resistor RP15; the second terminal of resistor RP15 is connected to the USB control logic input terminal of the SOC chip; the second terminals of resistors RP10, RP4, RP3, RP2, RP1, and RP7 are connected to the +3.3VSW power supply; the second terminals of resistors RP16, RP17, and RP18 are connected to the power supply ground. The power switch output terminal OUT of the USB charging management chip U13 outputs power USB1_+5V; The positive data input terminal DP_IN of the USB charging management chip U13 is connected to the first output terminal of the common-mode inductor LL1; the negative data input terminal DM_IN of the USB charging management chip U13 is connected to the second output terminal of the common-mode inductor LL1; the ground terminal GND of the USB charging management chip U13 is connected to the power supply ground; the low current limit threshold setting terminal ILIM_LO of the USB charging management chip U13 is connected to the first terminal of the resistor RP14; the high current limit threshold setting terminal ILIM_HI of the USB charging management chip U13 is connected to the first terminal of the resistor RP13; the second terminals of the resistor RP13 and the second terminals of the resistor RP14 are connected to the power supply ground; the heat dissipation terminal Exposed PAD of the USB charging management chip U13 is connected to the power supply ground.

3. The USB charging circuit for an instrument panel according to claim 1, characterized in that, The power switch output terminal OUT of the USB charging management chip U13 is also connected to the power filtering circuit: The power switch output terminal OUT of the USB charging management chip U13 outputs power USB1_+5V, which is connected to the first terminal of capacitor CP1, the first terminal of capacitor CP2, and the positive terminal of polarized capacitor C169. The second terminal of capacitor CP1, the second terminal of capacitor CP2, and the negative terminal of polarized capacitor C169 are connected to the power ground. The positive data input terminal DP_IN of the USB charging management chip U13 is connected to the first output terminal of the common-mode inductor LL1; the negative data input terminal DM_IN of the USB charging management chip U13 is connected to the second output terminal of the common-mode inductor LL1; the ground terminal GND of the USB charging management chip U13 is connected to the power supply ground; the low current limit threshold setting terminal ILIM_LO of the USB charging management chip U13 is connected to the first terminal of the resistor RP14; the high current limit threshold setting terminal ILIM_HI of the USB charging management chip U13 is connected to the first terminal of the resistor RP13; the second terminals of the resistor RP13 and the second terminals of the resistor RP14 are connected to the power supply ground; the heat dissipation terminal Exposed PAD of the USB charging management chip U13 is connected to the power supply ground.

4. A USB charging circuit for an instrument panel according to claim 1, characterized in that, The signal transmission terminal of the USB socket is connected to the first contact terminal of a common-mode inductor, and the second contact terminal of the common-mode inductor is connected to the signal transmission terminal of the USB charging management chip. The first contact terminal of the common-mode inductor has a USB positive data signal line and a USB negative data signal line. Both the USB positive and negative data signal lines are connected to a bidirectional TVS diode, and the other end of the bidirectional TVS diode is grounded. (Includes:) The first input terminal of the common-mode inductor LL1 is connected to the third terminal of the USB interface J14 and the first terminal of the transient diode LTV13; the second input terminal of the common-mode inductor LL1 is connected to the fourth terminal of the USB interface J14 and the first terminal of the transient diode LTV12; the second terminals of the transient diode LTV12 and LTV13, and the first terminal of the capacitor C143 are connected to the power supply ground; the second terminal of the capacitor C143 and the first terminal of the USB interface J14 are connected to the power supply USB1_+5V; the second terminal of the USB interface J14 is connected to the power supply ground; where the USB socket is the USB interface.

5. A USB charging circuit for an instrument panel according to claim 1, characterized in that, The SOC chip is also connected to the MCU chip and the FLAH chip: The crystal output terminal of SOC chip U6 is connected to the first terminal of resistor RM502, the third terminal of crystal Y1, and the first terminal of capacitor C45. The second terminal of resistor RM502 is connected to the crystal input terminal of SOC chip U6, the first terminal of crystal Y1, and the first terminal of capacitor C44. The second terminals of capacitor C44, capacitor C45, and the fourth terminal of crystal Y1 are connected to the power supply ground. The second terminal of crystal Y1 is also connected to the power supply ground. The reset terminal of the SOC chip U6 is connected to the first terminal of capacitor C43, the collector of transistor Q7, and the first terminal of resistor RB5. The second terminal of capacitor C43 and the emitter of transistor Q7 are connected to the power supply ground. The second terminal of resistor RB5 is connected to the power supply VDD33_IO. The base of transistor Q7 is connected to the first terminal of resistor R131. The second terminal of resistor R131 is connected to the reset control terminal of the MCU chip.

6. A USB charging circuit for an instrument panel according to claim 1, characterized in that, It also includes the internal power supply circuit of the SOC chip, which includes the SOC first part internal power supply circuit, the SOC second part internal power supply circuit and the SOC third part internal power supply circuit. The first internal power supply circuit converts the +1.2V power supply to VDD1V2_CORE, the second internal power supply circuit converts the +1.8V power supply to +1.8V_MCU, and the third internal power supply circuit converts the +3.3VSW power supply to VDD33_IO.

7. A USB charging circuit for an instrument panel according to claim 6, characterized in that, The internal power supply circuit of the first part of the SOC includes: the first terminal of inductor L6 is connected to the +1.2V power supply; the second terminal of inductor L6 outputs power supply VDD1V2_CORE, and is connected to the first terminals of capacitors C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C60, C61, and C62; the second terminals of capacitors C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C60, C61, and C62 are connected to the power supply ground. The internal power supply circuit of the second part of the SOC includes: the first terminal of inductor L8 is connected to the +1.8V power supply; the second terminal of inductor L8 outputs the +1.8V power supply to the MCU and is connected to the first terminals of capacitors C80, C81, C82, C83, and C84; the second terminals of capacitors C80, C81, C82, C83, and C84 are connected to the power supply ground. The internal power supply circuit of the third part of the SOC includes: the first terminal of inductor L7 is connected to the +3.3VSW power supply; the second terminal of inductor L7 outputs power supply VDD33_IO and is connected to the first terminals of capacitors C65, C66, C67, C68, and C69; the second terminals of capacitors C65, C66, C67, C68, and C69 are connected to the power supply ground; in addition, the second terminal of inductor L7 can also be connected to the first terminals of capacitors C70, C71, C72, C73, C74, and C75; the second terminals of capacitors C70, C71, C72, C73, C74, and C75 are connected to the power supply ground.

8. A USB charging circuit for an instrument panel according to claim 6, characterized in that, The internal power supply circuitry of the third part of the SOC also includes three sub-power supply circuits: used to convert power supply VDD33_IO into power supply VDD3.3V_SAR, power supply VDD3V3A, and power supply VCC_RTC respectively. The first sub-power supply circuit includes: power supply VDD33_IO is connected to the first terminal of resistor R39, the second terminal of resistor R39 outputs power supply VDD3.3V_SAR and is connected to the first terminal of capacitor C85 and the first terminal of capacitor C86, and the second terminal of capacitor C85 and the second terminal of capacitor C86 are connected to power supply ground. The second sub-power supply circuit includes: power supply VDD33_IO is connected to the first end of resistor R40, the second end of resistor R40 outputs power supply VDD3V3A and is connected to the first end of capacitor C87, the first end of capacitor C88, and the first end of capacitor C89, and the second end of capacitor C87, the second end of capacitor C88, and the second end of capacitor C89 is connected to power supply ground. The third sub-power supply circuit includes: power supply VDD33_IO is connected to the first end of resistor R41, the second end of resistor R41 outputs power supply VCC_RTC and is connected to the first end of capacitor CO5 and the first end of capacitor C90, and the second end of capacitor CO5 and the second end of capacitor C90 are connected to power supply ground.

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