Asymmetric multi-path signal transmitting and receiving circuit and intelligent lamp

Abstract

The utility model discloses an asymmetric multipath signal transmit-receive circuit and an intelligent lamp, the asymmetric multipath signal transmit-receive circuit comprises a first transmit-receive module provided with a plurality of first receiving ports and a plurality of first transmitting ports; the second transceiving module is provided with a plurality of second receiving ports and a plurality of second transmitting ports, the second receiving ports are respectively connected with the corresponding first transmitting ports, and the first transceiving module controls the second transceiving module through the first transmitting ports and the second receiving ports in sequence; the buffer module is provided with a plurality of third sending ports and a plurality of third receiving ports, the second sending ports are respectively connected with the corresponding third receiving ports, the third sending ports are respectively connected with the corresponding first receiving ports, and the buffer module is used for caching information sent by the second transceiver module; the asymmetric multi-path signal transceiver circuit provided by the utility model can reduce the information processing pressure of receiving and outputting signals by the first transceiver module.

Description

Technical Field

[0001] This utility model relates to the field of circuit control technology, and in particular to an asymmetric multi-channel signal transceiver circuit and an intelligent lighting fixture. Background Technology

[0002] In a multi-channel signal transceiver circuit, the main control chip needs to send control information to at least one controlled device and receive feedback information generated by at least one controlled device. The main control chip's simultaneous processing of multiple data streams increases the burden of information and instruction processing, affects the real-time performance of the processing, and degrades the performance of the main control chip. Utility Model Content

[0003] The following is an overview of the subject matter described in detail herein, and this overview is not intended to limit the scope of the claims.

[0004] This invention proposes an asymmetric multi-channel signal transceiver circuit and an intelligent lamp, which can reduce the information processing pressure of the first transceiver module in receiving and outputting signals.

[0005] The first aspect of this utility model provides an asymmetric multi-channel signal transceiver circuit, comprising: a first transceiver module having multiple first receiving ports and multiple first transmitting ports; a second transceiver module having multiple second receiving ports and multiple second transmitting ports, wherein each second receiving port is connected to a corresponding first transmitting port, and the first transceiver module controls the second transceiver module sequentially through the first transmitting ports and the second receiving ports; and a buffer module having multiple third transmitting ports and multiple third receiving ports, wherein each second transmitting port is connected to a corresponding third receiving port, and each third transmitting port is connected to a corresponding first receiving port, and the buffer module is used to buffer the information transmitted by the second transceiver module.

[0006] In one embodiment, the buffer module includes multiple relay chips, with the third transmitting port and the third receiving port respectively disposed on each of the relay chips.

[0007] In one embodiment, the first transceiver module is further provided with a plurality of fourth transmitting ports, and each of the relay chips is provided with a fourth receiving port. The fourth transmitting ports are respectively connected to the corresponding fourth receiving ports. The first transceiver module sends control commands to the corresponding relay chip through the fourth transmitting ports, and the relay chip receives the control commands through its respective fourth receiving ports.

[0008] In one embodiment, the first receiving port, the third transmitting port, the fourth transmitting port, and the fourth receiving port are all SPI ports.

[0009] In one embodiment, the first transceiver module is provided with multiple device selection ports, each of which is connected to a corresponding relay chip. The first transceiver module controls the working state of the corresponding relay chip through the device selection ports.

[0010] In one embodiment, the buffer module further includes a storage chip, and each of the relay chips is electrically connected to the storage chip.

[0011] In one embodiment, the first transmitting port and the second receiving port are used to transmit TTL level signals.

[0012] In one embodiment, the second transceiver module includes a plurality of first transceivers and a plurality of second transceivers, wherein the first transceivers are connected to the buffer module and the second transceivers are connected to the first transceiver module.

[0013] In one embodiment, the second transceiver module includes a plurality of third transceivers, and the first transceiver module and the buffer module are respectively connected to the third transceivers.

[0014] In addition, the second aspect of this application proposes an intelligent lighting fixture, including a main control chip, a light-emitting module, and an asymmetric multi-channel signal transceiver circuit as described in the first aspect. The asymmetric multi-channel signal transceiver circuit includes a first transceiver module, a second transceiver module, and a buffer module. The first transceiver module is connected to the main control chip, and the second transceiver module is connected to the light-emitting module.

[0015] The embodiments of this application include at least the following beneficial effects: The first transceiver module is provided with multiple first transmitting ports. The first transceiver module is directly connected to the second receiving port of the second transceiver module through the first transmitting ports. Control information sent by the first transceiver module can be directly sent to the second transceiver module through the first transmitting ports and the second receiving ports, thereby ensuring that the control information sent by the first transceiver module can be quickly responded to by the second transceiver module. During operation, the second transceiver module continuously receives control information sent by the first transceiver module and generates feedback information in real time. By setting a buffer module between the first and second transceiver modules, the buffer module is provided with multiple third transmitting ports and multiple third receiving ports. The second transmitting port of the second transceiver module is connected to the third receiving port of the buffer module, and the third transmitting port of the buffer module is connected to the first receiving port of the first transceiver module. The feedback information of the second transceiver module is buffered by the buffer module and can be selectively sent to the first transceiver module. This reduces the pressure on the first transceiver module to simultaneously generate multiple control information channels and process multiple feedback information channels. The buffer module also reduces the risk of feedback information loss and ensures the stability of the feedback signal path.

[0016] Other features and advantages of this invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of this invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0017] The accompanying drawings are provided to further understand the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this utility model to explain the technical solution of this utility model, and do not constitute a limitation on the technical solution of this utility model.

[0018] Figure 1 A schematic diagram of an optional structure of the asymmetric multi-channel signal transceiver circuit provided in an embodiment of this utility model;

[0019] Figure 2 A schematic diagram of another optional structure of the asymmetric multiplexed signal transceiver circuit provided in this embodiment of the present invention;

[0020] Figure 3 A schematic diagram of another optional structure of the asymmetric multiplexed signal transceiver circuit provided in this embodiment of the present invention;

[0021] Figure 4 An optional circuit diagram of a first transceiver provided for an embodiment of this utility model;

[0022] Figure 5 An optional circuit diagram of a second transceiver provided in an embodiment of this utility model;

[0023] Figure 6 A schematic diagram of an optional circuit for a third transceiver provided in an embodiment of this utility model;

[0024] Figure 7 This is an optional system block diagram of an intelligent lighting fixture provided in an embodiment of the present utility model. Detailed Implementation

[0025] The embodiments of this utility model are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0026] In the description of this utility model, it should be understood that the directional descriptions, such as up, down, front, back, left, right, etc., indicate the directional or positional relationship based on the directional or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0027] In the description of this utility model, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If "first" or "second" is used in the description, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0028] In the description of this utility model, unless otherwise explicitly defined, terms such as "setting," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this utility model in conjunction with the specific content of the technical solution.

[0029] Currently, in multi-channel signal transceiver circuits, the main control chip needs to send control information to at least one controlled device and receive feedback information generated by at least one controlled device. The main control chip's simultaneous processing of multiple data streams increases the burden of information and instruction processing, affects the real-time performance of the processing, and degrades the performance of the main control chip.

[0030] To address the problem of high processing pressure in multi-channel signal transmission and reception, this invention provides an asymmetric multi-channel signal transmission and reception circuit, comprising: a first transceiver module, having multiple first receiving ports and multiple first transmitting ports; a second transceiver module, having multiple second receiving ports and multiple second transmitting ports, wherein each second receiving port is connected to a corresponding first transmitting port, and the first transceiver module controls the second transceiver module sequentially through the first transmitting ports and the second receiving ports; and a buffer module, having multiple third transmitting ports and multiple third receiving ports, wherein each second transmitting port is connected to a corresponding third receiving port, and each third transmitting port is connected to a corresponding first receiving port, and the buffer module is used to buffer the information transmitted by the second transceiver module; the solution provided by this invention can reduce the information processing pressure of the first transceiver module in receiving and outputting signals.

[0031] The embodiments of this utility model will be further described below with reference to the accompanying drawings.

[0032] Reference Figure 1This utility model provides an asymmetric multiplexed signal transceiver circuit, comprising:

[0033] The first transceiver module 100 is equipped with multiple first receiving ports MISO1 and multiple first transmitting ports TX1;

[0034] The second transceiver module 200 is provided with multiple second receiving ports RX2 and multiple second transmitting ports TX2. The second receiving ports RX2 are respectively connected to the corresponding first transmitting ports TX1. The first transceiver module 100 controls the second transceiver module 200 through the first transmitting port TX1 and the second receiving port RX2 in sequence.

[0035] The buffer module 300 is provided with multiple third transmitting ports MISO2 and multiple third receiving ports RX3. The second transmitting port TX2 is connected to the corresponding third receiving port RX3, and the third transmitting port MISO2 is connected to the corresponding first receiving port MISO1. The buffer module 300 is used to buffer the information sent by the second transceiver module 200.

[0036] Based on this, the first transceiver module 100 is provided with multiple first transmitting ports TX1. The first transceiver module 100 is directly connected to the second receiving port RX2 of the second transceiver module 200 through the first transmitting ports TX1. Control information sent by the first transceiver module 100 can be directly sent to the second transceiver module 200 through the first transmitting ports TX1 and the second receiving ports RX2, thereby ensuring that the control information sent by the first transceiver module 100 can be quickly responded to by the second transceiver module 200. During operation, the second transceiver module 200 continuously receives the control information sent by the first transceiver module 100 and generates feedback information in real time. A buffer is set between the first transceiver module 100 and the second transceiver module 200. The buffer module 300 is equipped with multiple third transmit ports MISO2 and multiple third receive ports RX3. The second transmit port TX2 of the second transceiver module 200 is connected to the third receive port RX3 of the buffer module 300, and the third transmit port MISO2 of the buffer module 300 is connected to the first receive port MISO1 of the first transceiver module 100. The feedback information of the second transceiver module 200 is buffered by the buffer module 300 and can be selectively sent to the first transceiver module 100. This reduces the pressure on the first transceiver module 100 to generate multiple control information and process multiple feedback information at the same time. The buffer module 300 can also reduce the risk of feedback information loss and ensure the stability of the feedback signal path.

[0037] In one specific implementation, the first transceiver module 100 is connected to the control chip, and the second transceiver module 200 is connected to the controlled device. The number of controlled devices can be multiple. The second receiving port RX2 and the first transmitting port TX1 are used to transmit TTL level signals.

[0038] Additionally, refer to Figure 2 In some embodiments of this utility model, the buffer module 300 includes multiple relay chips 310, the third transmitting port MISO2 is respectively disposed on each relay chip 310, and the third receiving port RX3 is respectively disposed on each relay chip 310.

[0039] Specifically, the relay chip 310 is equipped with a high-speed buffer. After receiving the feedback information from the second transceiver module 200 through the third receiving port RX3, the relay chip 310 temporarily stores the feedback information in the high-speed buffer. At the same time, the relay chip 310 will also preprocess the feedback information according to the preset program, identify the feedback information, filter out useless feedback information, and send the integrated feedback information to the first transceiver module 100 through the third sending port MISO2.

[0040] In one specific implementation, the relay chip 310 is model STM32F103RCT6.

[0041] Additionally, refer to again Figure 2 In some embodiments of this utility model, the first transceiver module 100 is further provided with multiple fourth transmitting ports MOSI1, and each relay chip 310 is provided with a fourth receiving port MOSI2. The fourth transmitting ports MOSI1 are respectively connected to the corresponding fourth receiving ports MOSI2. The first transceiver module 100 sends control commands to the corresponding relay chip 310 through the fourth transmitting ports MOSI1, and the relay chip 310 receives the control commands through its respective fourth receiving ports MOSI2.

[0042] Specifically, during the process of the control chip sending control information, it is necessary to intermittently adjust the control information based on feedback information. By setting multiple fourth transmission ports MOSI1 on the first transceiver module 100 and corresponding fourth reception ports MOSI2 on each relay chip 310, the relay chip 310 is used to forward various feedback information from the controlled device. When the first transceiver module 100 needs to obtain specific feedback information from the relay chip 310, the first transceiver module 100 sends a control command with a specific identifier to the relay chip 310 through the fourth transmission port MOSI1 corresponding to the relay chip 310. After receiving the control command, the relay chip 310 performs feedback information addressing according to the specific identifier and sends the feedback information corresponding to the specific identifier to the first transceiver module 100 through the third transmission port MISO2, thereby completing the process of the first transceiver module 100 receiving specific feedback information from the buffer module 300.

[0043] Additionally, refer to again Figure 2 In some embodiments of this utility model, the first transceiver module 100 is provided with multiple device selection ports CS, and the device selection ports CS are respectively connected to the corresponding relay chips 310. The first transceiver module 100 controls the working state of the corresponding relay chips 310 through the device selection ports CS.

[0044] Specifically, the buffer module 300 includes multiple relay chips 310, each relay chip 310 being used to receive specific feedback information from the controlled device. The first transceiver module 100 pre-stores the receiving relationship between the relay chip 310 and the type of feedback information. When the first transceiver module 100 needs to receive feedback information, the first transceiver module 100 sends a device selection command to the corresponding relay chip 310 through a specific device selection port CS, thereby controlling the relay chip 310 to send its stored feedback information to the first transceiver module 100 through the third transmission port MISO2.

[0045] Figure 2 In the first transceiver module 100, there are two device selection ports, CS1 and CS2, which are connected to two relay chips 310 respectively. When the first transceiver module 100 intends to control the relay chip 310 corresponding to the CS1 port, the first transceiver module 100 controls the CS1 port to a low level and controls the CS2 port to a high level. When the first transceiver module 100 intends to control the relay chip 310 corresponding to the CS2 port, the first transceiver module 100 controls the CS2 port to a low level and controls the CS1 port to a high level.

[0046] In addition, different relay chips 310 can perform different preprocessing on the same feedback information from the controlled device. The first transceiver module 100 can also send a device selection command to the corresponding relay chip 310 through a specific device selection port CS, thereby obtaining feedback information that has undergone specific preprocessing, reducing its own storage burden on a part of the preprocessing program, and making the first transceiver module 100 more lightweight.

[0047] In one specific implementation, the first receiving port MISO1, the third transmitting port MISO2, the fourth transmitting port MOSI1, the fourth receiving port MOSI2, and the device selection port CS are all SPI ports. The third transmitting port MISO2 and the first receiving port MISO1 are the ports through which the relay chip 310 sends feedback information to the first transceiver module 100. The device selection port CS is used by the first transceiver module 100 to select a specific relay chip 310 for information interaction. The fourth transmitting port MOSI1 and the fourth receiving port MOSI2 are used to select the required feedback information from the relay chip 310. The number of the first receiving port MISO1 and the fourth transmitting port MOSI1 can be one. The first receiving port MISO1 can simultaneously interact with the third transmitting ports MISO1 of multiple relay chips 310. With ISO2 connection, the fourth transmitting port MOSI1 is simultaneously connected to the fourth receiving port MOSI2 of multiple relay chips 310. The CS port of the first transceiver module 100 can be set to high-level trigger. When the device selection port CS connected to one of the relay chips 310 is at a high level, only that relay chip 310 receives and recognizes the control command issued by the fourth transmitting port MOSI1, which can also realize the process of the first transceiver module 100 obtaining specific feedback information from the buffer module 300. Alternatively, the CS port of the first transceiver module 100 can also be set to low-level trigger. When the device selection port CS connected to one of the relay chips 310 is at a low level, only that relay chip 310 receives and recognizes the control command issued by the fourth transmitting port MOSI1.

[0048] Additionally, refer to Figure 3 In some embodiments of this utility model, the buffer module 300 further includes a storage chip 320, and each transfer chip 310 is electrically connected to the storage chip 320.

[0049] Specifically, the storage chip 320 is used to store feedback information, thereby enabling the feedback information to be stored for a relatively long period of time. When the first transceiver module 100 needs to obtain feedback information that was generated a long time ago, the first transceiver module 100 activates the relay chip 310 through the device selection port CS and sends a control command to the relay chip 310 through the fourth transmission port MOSI1. The relay chip 310 searches for the corresponding feedback information in the buffer and the storage chip 320 according to the control command and sends the feedback information to the first transceiver module 100.

[0050] Additionally, refer to Figure 4 and Figure 5 In some embodiments of this utility model, the second transceiver module 200 includes a plurality of first transceivers 210 and a plurality of second transceivers 220. The first transceivers 210 are connected to the buffer module 300, and the second transceivers 220 are connected to the first transceiver module 100.

[0051] Specifically, both the first transceiver 210 and the second transceiver 220 are 485 transceivers. The first transceiver 210 is in simplex mode for the controlled device to send feedback information to the buffer module 300, and the second transceiver 220 is in simplex mode for the first transceiver module 100 to send control information to the controlled device. The first transceiver 210, the second transceiver 220, and the buffer module 300 together form a full-duplex communication channel between the first transceiver module 100 and the controlled device. The RE1 and DE1 ports of the first transceiver 210 are grounded, and the RO1 port of the first transceiver 210 is connected to the second transmit port TX2. The third receive port RX3 of the buffer module 300 is connected to the RO1 port of the first transceiver 210 through the second transmit port TX2. The A and B lines of the first transceiver 210 are connected to the controlled device respectively. The RE1 and DE1 ports of the first transceiver 210 are always in a low-level state. The controlled device sends feedback information to the buffer module 300 through the first transceiver 210.

[0052] In addition, the RE2 and DE2 ports of the second transceiver 220 are connected to the power supply, the DI2 port of the second transceiver 220 is connected to the second receiving port RX2, the first transmitting port TX1 of the first transceiver module 100 is connected to the DI2 port of the second transceiver 220 through the second receiving port RX2, the A line and B line of the second transceiver 220 are respectively connected to the controlled device, the RE2 and DE2 ports of the second transceiver 220 are always in a high level state, and the first transceiver module 100 sends control information to the controlled device through the second transceiver 220.

[0053] Additionally, refer to again Figure 2 and Figure 6In some embodiments of this utility model, the second transceiver module 200 further includes a plurality of third transceivers 230, and the first transceiver module 100 and the buffer module 300 are respectively connected to the third transceivers 230.

[0054] Specifically, the first transceiver module 100 is also equipped with a device control port Bdat. The DE3 port and RE3 port of the third transceiver 230 are both connected to the device control port Bdat. The DI3 port of the third transceiver 230 is connected to the second receiving port RX2. The first transmitting port TX1 of the first transceiver module 100 is connected to the DI3 port through the second receiving port RX2. The RO3 port of the third transceiver 230 is connected to the second transmitting port TX2. The third receiving port RX3 of the buffer module 300 is connected to the RO3 port through the second transmitting port TX2. The A line and B line of the third transceiver 230 are respectively connected to the controlled device.

[0055] When the device control port Bdat is high, the DE3 port of the third transceiver 230 is activated, and the third transceiver 230 enters the transmit mode. The first transceiver module 100 can send control information to the controlled device through the third transceiver 230. When the device control port Bdat is low, the RE3 port of the third transceiver 230 is activated, and the third transceiver 230 enters the receive mode. The buffer module 300 can receive feedback information from the controlled device through the third transceiver 230.

[0056] Additionally, refer to Figure 7 This utility model embodiment also proposes an intelligent lamp, including a main control chip 400, a light-emitting module 500, and an asymmetric multi-channel signal transceiver circuit as described in the above embodiment. The asymmetric multi-channel signal transceiver circuit includes a first transceiver module 100, a second transceiver module 200, and a buffer module 300. The first transceiver module 100 is connected to the main control chip 400, and the second transceiver module 200 is connected to the light-emitting module 500.

[0057] It is understood that the specific implementation of this smart lamp is basically the same as the specific implementation of the above-mentioned asymmetric multi-channel signal transceiver circuit, and will not be described again here.

[0058] The embodiments of the present utility model have been described in detail above with reference to the accompanying drawings. However, the present utility model is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present utility model.

Claims

1. An asymmetric multiplexed signal transceiver circuit, characterized in that, include: The first transceiver module is equipped with multiple first receiving ports and multiple first transmitting ports; The second transceiver module is provided with multiple second receiving ports and multiple second sending ports. The second receiving ports are respectively connected to the corresponding first sending ports. The first transceiver module controls the second transceiver module through the first sending ports and the second receiving ports in sequence. The buffer module is provided with multiple third transmitting ports and multiple third receiving ports. The second transmitting ports are respectively connected to the corresponding third receiving ports, and the third transmitting ports are respectively connected to the corresponding first receiving ports. The buffer module is used to buffer the information sent by the second transceiver module.

2. The asymmetric multiplexed signal transceiver circuit according to claim 1, characterized in that, The buffer module includes multiple relay chips, and the third transmitting port is respectively set on each of the relay chips, and the third receiving port is respectively set on each of the relay chips.

3. The asymmetric multiplexed signal transceiver circuit according to claim 2, characterized in that, The first transceiver module is also provided with multiple fourth transmitting ports, and each of the relay chips is provided with a fourth receiving port. The fourth transmitting ports are respectively connected to the corresponding fourth receiving ports. The first transceiver module sends control commands to the corresponding relay chip through the fourth transmitting ports, and the relay chip receives the control commands through its respective fourth receiving ports.

4. The asymmetric multiplexed signal transceiver circuit according to claim 3, characterized in that, The first receiving port, the third transmitting port, the fourth transmitting port, and the fourth receiving port are all SPI ports.

5. The asymmetric multiplexed signal transceiver circuit according to claim 3, characterized in that, The first transceiver module is provided with multiple device selection ports, each of which is connected to a corresponding relay chip. The first transceiver module controls the working status of the corresponding relay chip through the device selection ports.

6. The asymmetric multiplexed signal transceiver circuit according to claim 2, characterized in that, The buffer module also includes a storage chip, and each of the relay chips is electrically connected to the storage chip.

7. The asymmetric multiplexed signal transceiver circuit according to claim 1, characterized in that, The first transmitting port and the second receiving port are used to transmit TTL level signals.

8. The asymmetric multiplexed signal transceiver circuit according to claim 1, characterized in that, The second transceiver module includes multiple first transceivers and multiple second transceivers, wherein the first transceivers are connected to the buffer module and the second transceivers are connected to the first transceiver module.

9. The asymmetric multiplexed signal transceiver circuit according to claim 1, characterized in that, The second transceiver module includes multiple third transceivers, and the first transceiver module and the buffer module are respectively connected to the third transceivers.

10. A smart lighting fixture, characterized in that, It includes a main control chip, a light-emitting module, and an asymmetric multiplexer circuit as described in any one of claims 1 to 9. The asymmetric multiplexer circuit includes a first transceiver module, a second transceiver module, and a buffer module. The first transceiver module is connected to the main control chip, and the second transceiver module is connected to the light-emitting module.

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