Display device

Abstract

The display device provided by the utility model comprises a substrate; a first transistor including a first active layer of a first semiconductor layer disposed over the substrate, and a first gate electrode overlapping the first active layer; a second transistor including a second active layer of a second semiconductor layer disposed over the substrate, and a second gate electrode overlapping the second active layer; a dummy pattern disposed in the first semiconductor layer at a distance from the first active layer; an inorganic insulating layer disposed on the substrate and covering the first active layer, the dummy pattern, the first gate electrode, the second active layer, and the second gate electrode; a dummy hole passing through the inorganic insulating layer over the dummy pattern; and a shielding layer disposed at least inside the dummy hole and covering a side surface of the inorganic insulating layer exposed through the dummy hole.

Description

Technical Field

[0001] This utility model relates to a display device. Background Technology

[0002] With the development of multimedia, the importance of display devices has been gradually increasing. Accordingly, various display devices, including light-emitting display devices, are being developed. Utility Model Content

[0003] The technical problem to be solved by this invention is to provide a display device that can improve the degradation of transistors.

[0004] The technical problems of this utility model are not limited to those mentioned above. Those skilled in the art can clearly understand other technical problems not mentioned through the following description.

[0005] A display device according to one embodiment includes: a substrate; a first transistor including a first active layer of a first semiconductor layer disposed on the substrate and a first gate electrode overlapping the first active layer; a second transistor including a second active layer of a second semiconductor layer disposed on the substrate and a second gate electrode overlapping the second active layer; a dummy pattern spaced apart from the first active layer and disposed on the first semiconductor layer; an inorganic insulating layer disposed on the substrate and covering the first active layer, the dummy pattern, the first gate electrode, the second active layer, and the second gate electrode; a dummy hole penetrating the inorganic insulating layer over the dummy pattern; and a shielding layer disposed at least inside the dummy hole and covering the side of the inorganic insulating layer exposed through the dummy hole.

[0006] In one embodiment, the display device may further include: an organic insulating layer disposed on the inorganic insulating layer and covering the first transistor, the second transistor, and the shielding layer.

[0007] In one embodiment, the shielding layer may be a conductive pattern containing metal.

[0008] In one embodiment, the second transistor may further include a first electrode disposed on the inorganic insulating layer and connected to the source region or drain region of the first active layer. The first electrode and the shielding layer may be disposed on the same layer on the substrate and contain the same conductive material.

[0009] In one embodiment, the display device may further include power wiring located around the dummy pattern, and the shielding layer may be connected to the power wiring.

[0010] In one embodiment, the power wiring may be disposed on the inorganic insulating layer, and the display device may further include a connection pattern disposed between the conductive layer on which the shielding layer is disposed and the first semiconductor layer, and connecting the shielding layer and the power wiring.

[0011] In one embodiment, the connection pattern may be configured on the same layer as the first gate electrode or the second gate electrode.

[0012] In one embodiment, the display device may further include a capacitor electrode disposed between a conductive layer on the substrate having a first gate electrode and a conductive layer having a second gate electrode, and the connection pattern may be disposed on the same layer as the capacitor electrode.

[0013] In one embodiment, the shielding layer may be an inorganic insulating layer containing nitrogen.

[0014] In one embodiment, the shielding layer may be a single-layer inorganic insulating layer comprising a silicon nitride layer or a silicon oxynitride layer.

[0015] In one embodiment, the shielding layer may be a multilayer inorganic insulating layer comprising a silicon nitride layer or a silicon oxynitride layer and a silicon oxide layer.

[0016] In one embodiment, the shielding layer may have a refractive index of 1.6 or higher.

[0017] In one embodiment, the display device may further include: a pixel, a display area located on the substrate, and a driving circuit, a non-display area located on the substrate and connected to the pixel, wherein the first transistor and the second transistor may be provided in the driving circuit.

[0018] In one embodiment, the dummy pattern, the dummy hole, and the masking layer may be located around the driving circuit.

[0019] In one embodiment, the dummy pattern, the dummy aperture, and the masking layer may be located between the hierarchical circuits provided in the driving circuit.

[0020] A method for manufacturing a display device according to an embodiment includes: sequentially forming a first active layer and a dummy pattern, an inorganic insulating layer covering the first active layer and the dummy pattern, a first gate electrode, an inorganic insulating layer covering the first gate electrode, a second active layer, an inorganic insulating layer covering the second active layer, a second gate electrode, and an inorganic insulating layer covering the second gate electrode on a substrate; forming a contact hole penetrating the inorganic insulating layer to expose a portion of the first active layer and a dummy hole penetrating the inorganic insulating layer to expose a portion of the dummy pattern; and forming a first electrode connected to the first active layer through the contact hole on the inorganic insulating layer, and forming a shielding layer covering the side of the inorganic insulating layer exposed through the dummy hole, at least inside the dummy hole.

[0021] In one embodiment, the method of manufacturing the display device may further include the step of forming an organic insulating layer covering the first electrode and the shielding layer on the inorganic insulating layer.

[0022] In one embodiment, in the step of forming the first electrode and the shielding layer, the first electrode and the shielding layer can be formed simultaneously by using a conductive material containing metal.

[0023] In one embodiment, the method of manufacturing the display device may further include the step of forming power wiring connected to the shielding layer on the inorganic insulating layer.

[0024] In one embodiment, the steps of forming the first electrode and the shielding layer may include: forming the first electrode using a conductive material; and forming the shielding layer using a nitrogen-containing inorganic insulating material.

[0025] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0026] (Utility Model Effect)

[0027] According to the display device and manufacturing method of the embodiment, dummy patterns and dummy holes can be formed around circuit elements including transistors. This allows for more uniform patterning of the display panel and more uniform control of the characteristics of the circuit elements.

[0028] Furthermore, according to the display device and manufacturing method of the embodiment, a shielding layer covering the side of the inorganic insulating layer exposed through the dummy hole can be formed inside the dummy hole. This improves the degradation of circuit elements located around the dummy hole. Moreover, the distance between the transistor and the dummy hole can be appropriately shortened as needed, and the non-display area can be reduced.

[0029] In several embodiments, the shielding layer may be a conductive pattern containing metal and may be connected to power wiring. This enables the display device to operate with stable characteristics.

[0030] The effects of the embodiments are not limited to those illustrated above, and further effects are included in this specification. Attached Figure Description

[0031] Figure 1 This is a perspective view showing an embodiment of a display device.

[0032] Figure 2 It is shown Figure 1 A top view of the display device.

[0033] Figure 3 This is a top view showing a display panel of one embodiment.

[0034] Figure 4 This is a circuit diagram illustrating a pixel in one embodiment.

[0035] Figure 5 This is a cross-sectional view showing a display panel according to one embodiment.

[0036] Figure 6 This is a top view showing a portion of a display panel according to one embodiment.

[0037] Figure 7 This is a top view that schematically illustrates a driving transistor and a dummy pattern of one embodiment.

[0038] Figure 8 This is a cross-sectional view showing a display panel according to one embodiment.

[0039] Figure 9 This is a cross-sectional view showing a display panel according to one embodiment.

[0040] Figure 10 This is a cross-sectional view showing a display panel according to one embodiment.

[0041] Figure 11 This is a cross-sectional view showing a display panel according to one embodiment.

[0042] Figure 12 This is a cross-sectional view showing a display panel according to one embodiment.

[0043] Figure 13 This is a cross-sectional view showing a display panel according to one embodiment.

[0044] Figures 14 to 18 This is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment.

[0045] Figure 19 and Figure 20This is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment.

[0046] Explanation of reference numerals in the attached figures

[0047] 10: Display device; 100: Display panel; 110: Substrate; 120: Circuit layer; 121: Buffer layer; 122-128: First to seventh insulating layers; 130: Light-emitting element layer; 140: Encapsulation layer; ACT1A, ACT1B: First active layer; ACT2A, ACT2B: Second active layer; CE1A, CE1B: First capacitor electrode; CE2A, CE2B: Second capacitor electrode; CNP: Connection pattern; DA: Display area; DMH: Dummy via; DMP: Dummy pattern DPL: Power supply wiring for the drive section; DRA: Drive circuit area; DRT1: First drive transistor; DRT2: Second drive transistor; DRV: First drive circuit; GE1A, GE1B: First gate electrode; GE2A, GE2B: Second gate electrode; NA: Non-display area; PX: Pixel; PXT1: First pixel transistor; PXT2: Second pixel transistor; SHL: Masking layer; ST: Hierarchical circuit; TE1: First electrode; TE2: Second electrode; PL: Pixel power supply wiring Detailed Implementation

[0048] The advantages, features, and methods of implementing this utility model can be clearly understood by referring to the accompanying drawings and the embodiments described in detail below. However, this utility model is not limited to the embodiments disclosed below, but can be implemented in many different ways. These embodiments are provided to fully disclose this utility model and to fully inform those skilled in the art of the scope of this utility model. This utility model is defined only by the scope of the claims.

[0049] When an element or layer is described as being "on" another element or layer, this includes cases where it is directly located on another element or layer or where it is separated by other layers or other elements. Throughout this specification, the same reference numerals denote the same constituent elements. The shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings used to illustrate embodiments are merely exemplary, and therefore this invention is not limited to the content shown in the drawings.

[0050] The various features of the numerous embodiments of this utility model can be partially or entirely combined or integrated with each other, and can technically achieve multiple linkages and drives. The embodiments can be implemented independently of each other, or they can be implemented together in an associated relationship.

[0051] The specific embodiments are described below with reference to the accompanying drawings.

[0052] Figure 1 This is a perspective view showing a display device 10 according to an embodiment.

[0053] Reference Figure 1 The display device 10 is a device for displaying images. It can be used not only as a display screen for portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watchphones, mobile communication terminals, electronic manuals, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs), but also as a display screen for various products such as televisions, laptops, monitors, billboards, and Internet of Things (IoT).

[0054] In one embodiment, the display device 10 may be a light-emitting display device including a light-emitting element. The display device 10 may also be other types of display devices besides light-emitting display devices. Although the following describes an embodiment where the display device 10 is an organic light-emitting display device, the type of display device 10 in these embodiments is not limited thereto.

[0055] Figure 1 The diagram shows a first direction D1, a second direction D2, and a third direction D3. Based on the image display surface of the display device 10, the first direction D1 can be the longitudinal direction, column direction, or vertical direction of the display device 10. The second direction D2 is a direction intersecting the first direction D1; for example, it can be the lateral direction, row direction, or horizontal direction of the display device 10. The third direction D3 is a direction intersecting both the first direction D1 and the second direction D2; for example, it can be the thickness direction or height direction of the display device 10.

[0056] The display device 10 may include a display panel 100, which includes pixels and a first driving circuit (e.g., a panel-integrated gate driving circuit). The display device 10 may also include a second driving circuit 200 and a circuit board 300 connected to the pixels and / or the first driving circuit.

[0057] The display panel 100 may include: a main region MA, including a display area DA for displaying images; and a sub-region SBA located on one side of the main region MA. The display panel 100 may be rigidly formed so that the entire display panel 100 can remain flat, or it may be flexibly formed so that at least a portion of the display panel 100 can be buckled, bent, folded, or rolled.

[0058] The main region MA can include the display region DA and the non-display region NA surrounding the display region DA. The non-display region NA can be located at the edge of the main region MA and can be connected to the sub-region SBA.

[0059] In one embodiment, the main region MA may have a generally rectangular shape, comprising a long side in the first direction D1 and a short side in the second direction D2. The corners where the long and short sides of the main region MA meet may be rounded or formed as right angles. The shape of the main region MA may vary depending on the embodiment.

[0060] The display area DA is the area for pixel arrangement, which can be the area for displaying images through pixels. The display area DA can be located in the center of the main area MA and can occupy most of the area of ​​the main area MA.

[0061] In one embodiment, the display area DA may have a shape corresponding to that of the main area MA. For example, the display area DA may include a long side in the first direction D1 and a short side in the second direction D2, thus having a generally rectangular shape. The corner portions where the long and short sides of the display area DA meet may be rounded or formed as right angles. The shape of the display area DA may vary depending on the embodiment.

[0062] The non-display area NA can be located immediately adjacent to the display area DA. For example, the non-display area NA can be located at the edge of the main area MA and can surround the display area DA. The non-display area NA can be connected to the sub-area SBA.

[0063] The non-display area NA may be configured with wiring (or a portion of the wiring) connected to the pixel. In one embodiment, the non-display area NA may also be configured with a first driving circuit that supplies a first driving signal to the pixel PX.

[0064] In one embodiment, the first driving circuit may be a gate driving circuit that supplies gate signals (e.g., scan signals and / or light emission control signals) to the pixel PX. For example, the first driving circuit may include a hierarchical circuit for generating scan signals and / or a hierarchical circuit for generating light emission control signals for the pixel PX.

[0065] The subregion SBA can be located on one side of the primary region MA. For example, the subregion SBA can protrude from one side of the primary region MA in the first direction D1. For example, the subregion SBA can protrude from the lower end of the primary region MA in the first direction D1.

[0066] In one embodiment, the sub-region SBA may have a narrower width than the main region MA. For example, with the second direction D2 as a reference, the sub-region SBA may have a narrower width than the main region MA.

[0067] The sub-region SBA may provide wiring (or a portion of said wiring) and pads. For example, the sub-region SBA may be configured with wiring and pads connected to pixels and / or first driving circuits located in the main region MA, second driving circuits 200 and / or circuit boards 300 located in the sub-region SBA. In the description of embodiments, "connection" may include the meaning of electrical connection and / or physical connection.

[0068] In one embodiment, a second drive circuit 200 may be mounted on the sub-region SBA. A circuit board 300 may be configured on a portion of the sub-region SBA.

[0069] The second driving circuit 200 can be connected to the pixel PX of the display area DA. The second driving circuit 200 may include data driving circuitry for driving the pixel. The second driving circuit 200 can supply data signals to the pixel PX.

[0070] In one embodiment, the second driving circuit 200 may be provided as an integrated circuit chip (IC) and mounted on the sub-region SBA. In another embodiment, the second driving circuit 200 may be provided or mounted on a circuit board 300 above the sub-region SBA, or it may also be provided or mounted on another circuit board connected to the display panel 100 via the circuit board 300.

[0071] The circuit board 300 may be disposed on a portion of the sub-region SBA. For example, the circuit board 300 may be bonded to pads located on a portion of the sub-region SBA (e.g., the lower edge) and may supply or transmit power supply voltages and drive signals for driving the display panel 100 and / or the second drive circuit 200 to the display panel 100. For example, the circuit board 300 may supply the display panel 100 with input image data (e.g., digital image data), drive signals (e.g., timing signals) for driving the first drive circuit and / or the second drive circuit 200, and power supply voltages for driving pixels, the first drive circuit, and / or the second drive circuit 200. The circuit board 300 may be a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on film (COF), but is not limited thereto.

[0072] Figure 2 It is shown Figure 1 A top view of the display device 10. Figure 1 The display device 10 is shown in its unfolded state without being bent. Figure 2This illustrates the state in which the display device 10 is bent at the sub-region SBA. For example, Figure 1 This shows the state where the subregion SBA and the main region MA are deployed side by side. Figure 2 This shows the state where the subregion SBA is bent so that a portion of the subregion SBA is located in the lower region of the main region MA.

[0073] exist Figure 1 Further reference on the basis Figure 2 The sub-region SBA of the display panel 100 can be flexibly formed so that at least a portion of it can be bent, folded, folded, or rolled. In one embodiment, the sub-region SBA can be bent at a portion adjacent to the main region MA. Thus, a portion of the sub-region SBA on which the second drive circuit 200, etc., is mounted can be located in the lower region of the main region MA.

[0074] Figure 3 This is a top view showing a display panel 100 according to one embodiment. Figure 3 This shows the display panel 100 in its unfolded state without being bent.

[0075] exist Figure 1 and Figure 2 Further references on the basis Figure 3 The display panel 100 may include: a main area MA, including a display area DA and a non-display area NA; and a sub-area SBA, including a pad area PA. In one embodiment, the sub-area SBA may further include a drive circuit mounting area for mounting a second drive circuit 200.

[0076] In one embodiment, the sub-region SBA may further include a curved region BA. In one embodiment, the curved region BA may be adjacent to the main region MA. The display panel 100 may be curved at the sub-region SBA, thereby a portion of the sub-region SBA may be located in the lower region of the main region MA.

[0077] The display panel 100 may include a substrate 110 (or a base layer) forming a base surface. The substrate 110 may include a main region MA, which includes a display region DA and a non-display region NA. In one embodiment, the substrate 110 may further include a sub-region SBA protruding from the main region MA.

[0078] The display panel 100 may include pixels PX and pads PD configured and / or formed on the substrate 110. In one embodiment, the display panel 100 may further include a first driving circuit DRV configured and / or formed on the substrate 110 and wiring. The wiring may be connected to the pixels PX, the first driving circuit DRV, the second driving circuit 200 and / or the pads PD.

[0079] Pixel PX can be configured in display area DA. Display area DA can also be configured with wiring (or a portion of the wiring) connected to pixel PX. For example, display area DA can also be configured with scan wiring, data wiring, and pixel power wiring connected to pixel PX. In display device 10 where the emission time of pixel PX is controlled by emission control signals, display area DA can also be configured with emission control wiring for transmitting each emission control signal to pixel PX.

[0080] A first driving circuit (DRV) can be configured in a non-display area (NA). The first driving circuit (DRV) can be connected to multiple pads (PDs) provided in the pad area (PA). The first driving circuit (DRV) can receive gate control signals (e.g., gate start pulse and gate clock signal) and gate power supply voltages (e.g., gate high voltage and gate low voltage) required to generate gate signals from the multiple pads (PDs). The first driving circuit (DRV) can be connected to a pixel (PX) via gate wiring (e.g., scan wiring and / or light emission control wiring) and can supply gate signals (e.g., scan signals and / or light emission control signals) to the pixel (PX).

[0081] The first driving circuit DRV can be located on at least one side of the display area DA. For example, the first driving circuit DRV can be located on only one side of the display area DA (e.g., the left or right side), or on both sides of the display area DA (e.g., the left and right sides). The location and / or number of the first driving circuit DRVs may vary depending on the embodiment.

[0082] In one embodiment, the first driving circuit DRV may be a built-in circuit provided together with the pixel PX and / or formed inside the display panel 100. For example, the first driving circuit DRV may be formed in the display panel 100 as a gate-inpanel.

[0083] Pads (PDs) can be configured in pad areas (PAs). Pads (PDs) can connect the display panel 100 and / or the second driving circuit 200 to the circuit board 300, etc. Pads (PDs) may include signal pads and power pads for transmitting drive signals and power voltages required to drive pixels (PXs), the first driving circuit (DRV), and / or the second driving circuit 200 into the display panel 100. The circuit board 300 may be configured or bonded onto the pad areas (PAs).

[0084] Figure 4 This is a circuit diagram illustrating a pixel PX according to one embodiment.

[0085] exist Figures 1 to 3 Further reference Figure 4Each pixel PX may include a pixel circuit PXC and a light-emitting element EL connected to the pixel circuit PXC. Figure 4 The document discloses an embodiment of a pixel circuit PXC for a pixel PX, including a driving transistor and multiple switching transistors. In one embodiment, the scan wiring SL connected to the pixel PX may include a first scan wiring SL1, a second scan wiring SL2, a third scan wiring SL3, and a fourth scan wiring SL4, and the pixel power wiring PL connected to the pixel PX includes a first pixel power wiring VDL, a second pixel power wiring VSL, a first initialization power wiring VIL1, a second initialization power wiring VIL2, and a bias power wiring VOBL. The pixel PX may also be connected to a data wiring DL and a light emission control wiring ECL. The structure of the pixel circuit PXC and the types of wiring connected to the pixel circuit PXC can be varied according to the embodiment.

[0086] A pixel circuit (PXC) can control the emission timing and brightness of a light-emitting element (EL) by controlling the drive current supplied to the EL. For example, a pixel circuit (PXC) may include a pixel transistor (PXT) and a storage capacitor (Cst), wherein the pixel transistor (PXT) controls the drive current in a manner corresponding to at least one scan signal and a data signal supplied to the corresponding pixel (PX). In one embodiment, the pixel transistor (PXT) may include a drive transistor (T1) and first to seventh switching transistors (T2 to T8).

[0087] The driving transistor T1 may include: a gate electrode connected to the first node N1; a first electrode connected to the pixel power supply line VDL via a fourth switching transistor T5; and a second electrode connected to the light-emitting element EL via a fifth switching transistor T6. One of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode. The driving transistor T1 can control the driving current flowing between the first electrode and the second electrode (e.g., the source-drain current of the driving transistor T1) based on the voltage applied to the gate electrode (e.g., the voltage of the first node N1 corresponding to the voltage of the data signal).

[0088] The first switching transistor T2 may include: a gate electrode connected to the first scan line SL1; a first electrode connected to the data line DL; and a second electrode connected to the first electrode of the driving transistor T1. The first switching transistor T2 can be turned on by a first scan signal supplied to the first scan line SL1, thereby connecting the first electrode of the driving transistor T1 to the data line DL. When the first switching transistor T2 is turned on, the voltage of the data signal supplied to the data line DL is applied to the first electrode of the driving transistor T1.

[0089] The second switching transistor T3 may include: a gate electrode connected to the second scan line SL2; a first electrode connected to the second electrode of the driving transistor T1; and a second electrode connected to the gate electrode (or first node N1) of the driving transistor T1. The second switching transistor T3 can be turned on by a second scan signal supplied to the second scan line SL2, thereby connecting the gate electrode of the driving transistor T1 to the second electrode. When the second switching transistor T3 is turned on, the driving transistor T1 functions as a diode.

[0090] The third switching transistor T4 may include: a gate electrode connected to the third scan line SL3; a first electrode connected to the gate electrode of the driving transistor T1; and a second electrode connected to the first initialization power line VIL1. The third switching transistor T4 can be turned on by a third scan signal supplied to the third scan line SL3, thereby connecting the gate electrode of the driving transistor T1 to the first initialization power line VIL1. When the third switching transistor T4 is turned on, a first initialization voltage VINT1 (e.g., a gate initialization voltage) of the first initialization power line VIL1 is applied to the gate electrode of the driving transistor T1.

[0091] The fourth switching transistor T5 may include: a gate electrode connected to the light emission control line ECL; a first electrode connected to the first pixel power supply line VDL; and a second electrode connected to the first electrode of the driving transistor T1. The fourth switching transistor T5 can be turned on by a light emission control signal supplied to the light emission control line ECL, thereby connecting the first electrode of the driving transistor T1 to the first pixel power supply line VDL, to which a first pixel power supply voltage ELVDD is applied. When the fourth switching transistor T5 is turned on, the first pixel power supply voltage ELVDD is applied to the first electrode of the driving transistor T1. In one embodiment, the first pixel power supply voltage ELVDD may be a high-level pixel driving voltage.

[0092] The fifth switching transistor T6 may include: a gate electrode connected to the light-emitting control wiring ECL; a first electrode connected to the second electrode of the driving transistor T1; and a second electrode connected to the light-emitting element EL. The fifth switching transistor T6 can be turned on by a light-emitting control signal supplied to the light-emitting control wiring ECL, thereby connecting the driving transistor T1 to the light-emitting element EL. When both the fourth switching transistor T5 and the fifth switching transistor T6 are turned on, a driving current corresponding to the voltage of the gate electrode of the driving transistor T1 (e.g., the voltage of the first node N1) flows through the light-emitting element EL.

[0093] The sixth switching transistor T7 may include: a gate electrode connected to the fourth scan line SL4; a first electrode connected to the first electrode (e.g., the anode electrode) of the light-emitting element EL; and a second electrode connected to the second initialization power line VIL2. The sixth switching transistor T7 can be turned on by a fourth scan signal supplied to the fourth scan line SL4, thereby connecting the first electrode of the light-emitting element EL to the second initialization power line VIL2. The fourth scan signal may be the same as or a different signal than the first scan signal. When the sixth switching transistor T7 is turned on, the second initialization voltage VINT2 (e.g., the anode initialization voltage) of the second initialization power line VIL2 is applied to the first electrode of the light-emitting element EL.

[0094] The seventh switching transistor T8 may include: a gate electrode connected to the fourth scan line SL4; a first electrode connected to the bias power supply line VOBL; and a second electrode connected to the first electrode of the driving transistor T1. The seventh switching transistor T8 can be turned on by a fourth scan signal supplied to the fourth scan line SL4, thereby connecting the first electrode of the driving transistor T1 to the bias power supply line VOBL. When the seventh switching transistor T8 is turned on, a bias voltage VOBS supplied to the bias power supply line VOBL is applied to the first electrode of the driving transistor T1. In one embodiment, the bias voltage VOBS may have a voltage level suitable for compensating for the hysteresis characteristics of the driving transistor T1. With the seventh switching transistor T8 turned on, the first electrode of the driving transistor T1 can be initialized to the bias voltage VOBS.

[0095] The storage capacitor Cst can be connected between the gate electrode of the driving transistor T1 (or the first node N1) and the first pixel power supply line VDL. The storage capacitor Cst can be charged with a voltage corresponding to the voltage of the data signal applied to the gate electrode of the driving transistor T1.

[0096] The active layer (e.g., a semiconductor pattern including the channel region) of each transistor in the pixel transistor PXT can comprise a semiconductor material selected from polysilicon, amorphous silicon, and oxide semiconductor. In one embodiment, a portion and another portion of the pixel transistor PXT can be formed as transistors of different conductivity types. Furthermore, a portion and another portion of the pixel transistor PXT can comprise different types of semiconductor materials.

[0097] For example, the driving transistor T1 and the first, fourth, fifth, sixth, and seventh switching transistors T2, T5, T6, T7, and T8 can be formed as P-type transistors (e.g., P-type polysilicon transistors) including active layers formed of polysilicon, and the second and third switching transistors T3 and T4 can be formed as N-type transistors (e.g., N-type oxide transistors) including active layers formed of oxide semiconductors. In one embodiment, the active layers formed of polysilicon and the active layers formed of oxide semiconductors can be disposed as different layers on the substrate 110 of the display panel 100.

[0098] The light-emitting element EL can be connected between the pixel circuit PXC and the second pixel power line VSL. The second pixel power line VSL can be supplied with a second pixel power supply voltage ELVSS. In one embodiment, the second pixel power supply voltage ELVSS can be a low-potential pixel drive voltage. The light-emitting element EL can emit light in a manner corresponding to the drive current supplied by the pixel circuit PXC.

[0099] In one embodiment, a pixel PX may include one light-emitting element EL, but is not limited thereto. For example, a pixel PX may also include at least two light-emitting elements EL.

[0100] The light-emitting element (EL) can be an organic light-emitting diode, but is not limited to this. For example, the light-emitting element (EL) can be an inorganic light-emitting element, a quantum dot light-emitting element, or other types of light-emitting elements.

[0101] Figure 5 This is a cross-sectional view illustrating a display panel 100 according to one embodiment. For example, Figure 5 A cross-section of the display panel 100 is shown schematically, representing a portion of the display area DA corresponding to the pixel area PXA where a pixel PX is located.

[0102] exist Figures 1 to 4 Further references on the basis Figure 5 The display panel 100 may include: a substrate 110, a circuit layer 120, a light-emitting element layer 130, and an encapsulation layer 140 disposed on the substrate 110. In one embodiment, the circuit layer 120, the light-emitting element layer 130, and the encapsulation layer 140 may be sequentially disposed on the substrate 110 along a third direction D3. Although the circuit layer 120 and the light-emitting element layer 130 are described separately in the description of the embodiment, the embodiment is not limited thereto. For example, the circuit layer 120 and the light-emitting element layer 130 may also be integrated together.

[0103] Substrate 110 is a base component for forming display panel 100, and it can be a rigid substrate or a flexible substrate (or film). In one embodiment, substrate 110 may contain an insulating material such as glass and have rigid properties. Alternatively, substrate 110 may contain polyimide or other insulating materials and have deformable flexible properties such as bending, folding, and rolling. The type and / or material of substrate 110 may vary depending on the embodiment.

[0104] The substrate 110 may include a display area DA and a non-display area NA. The display area DA may include a pixel area PXA for providing pixels PX. The non-display area NA may include a driving circuit area for providing a first driving circuit DRV, etc.

[0105] The circuit layer 120 may include pixel circuits PXC and wiring for each pixel PX. For example, the circuit layer 120 may include circuit elements constituting the pixel circuits PXC of each pixel PX (e.g., Figure 4 The circuit layer 120 includes pixel transistors (PXT) and storage capacitors (Cst), as well as wiring connected to the pixel PX (e.g., pixel power wiring PL, scan wiring SL, light emission control wiring ECL, and data wiring DL). In one embodiment, the circuit layer 120 may further include circuit elements constituting a first driving circuit DRV and wiring connected to the first driving circuit DRV. In one embodiment, the circuit layer 120 may be formed on the entire surface of one side of the substrate 110.

[0106] Figure 5 As an example of elements that may be provided in the circuit layer 120 in the display area DA, the figure illustrates a first pixel transistor PXT1, a second pixel transistor PXT2, and a storage capacitor Cst provided in the pixel region PXA of each pixel PX. In one embodiment, the first pixel transistor PXT1 may represent a first type of transistor (e.g., a P-type polysilicon transistor) that contains a first semiconductor material (e.g., polysilicon) in the pixel transistor PXT constituting each pixel circuit PXC. For example, the first pixel transistor PXT1 may be one of a driving transistor T1 and a first, fourth, fifth, sixth, and / or seventh switching transistor T2, T5, T6, T7, and T8. Figure 5 The first pixel transistor PXT1 is exemplified as a transistor of the first type that is connected to the light-emitting element EL via at least one bridging electrode (e.g., Figure 4The fifth switching transistor T6). In one embodiment, the second pixel transistor PXT2 may represent a second type of transistor (e.g., an N-type oxide transistor) in the pixel transistor PXT that contains a second semiconductor material (e.g., an oxide semiconductor). For example, the second pixel transistor PXT2 may be one of the second and third switching transistors T3 and T4.

[0107] The cross-section of a pixel PX can be varied depending on the type and / or structure of each pixel PX and the display panel 100 including it. For example, the position and formation order of the first pixel transistor PXT1, the second pixel transistor PXT2, and the storage capacitor Cst can vary depending on the embodiment.

[0108] The circuit layer 120 may include a semiconductor layer, a conductive layer, and an insulating layer disposed between and / or around the semiconductor layer and the conductive layer for forming circuit elements and wiring, etc. For example, the circuit layer 120 may include a first semiconductor layer SCL1 (e.g., a polysilicon semiconductor layer), a first insulating layer 122 (e.g., a first inorganic insulating layer), a first conductive layer CDL1 (e.g., a first gate conductive layer), a second insulating layer 123 (e.g., a second inorganic insulating layer), a second conductive layer CDL2 (e.g., a second gate conductive layer), a third insulating layer 124 (e.g., a third inorganic insulating layer), a second semiconductor layer SCL2 (e.g., an oxide semiconductor layer), a fourth insulating layer 125 (e.g., a fourth inorganic insulating layer), a third conductive layer CDL3 (e.g., a third gate conductive layer), a fifth insulating layer 126 (e.g., a fifth inorganic insulating layer), a fourth conductive layer CDL4 (e.g., a first source-drain conductive layer or a first data conductive layer), and a sixth insulating layer 127 (e.g., a first organic insulating layer) disposed sequentially on the substrate 110 with reference to a third direction D3.

[0109] In one embodiment, the circuit layer 120 may further include at least one conductive layer and at least one insulating layer disposed on the sixth insulating layer 127. For example, the circuit layer 120 may further include a fifth conductive layer CDL5 (e.g., a second source-drain conductive layer or a second data conductive layer) and a seventh insulating layer 128 (e.g., a second organic insulating layer) disposed sequentially on the sixth insulating layer 127.

[0110] In one embodiment, the circuit layer 120 may further include at least one conductive layer and / or at least one insulating layer disposed between the substrate 110 and the first semiconductor layer SCL1. For example, the circuit layer 120 may further include a barrier layer and / or a buffer layer 121 disposed between the substrate 110 and the first semiconductor layer SCL1. Furthermore, the circuit layer 120 may optionally include a lower conductive layer (e.g., a bottom metal layer) disposed between the substrate 110 and the buffer layer 121.

[0111] A buffer layer 121 may be disposed on the substrate 110. The buffer layer 121 protects elements disposed on the circuit layer 120 and the light-emitting element layer 130 from moisture that may penetrate through the poorly moisture-permeable substrate 110. The buffer layer 121 may comprise at least one inorganic film containing an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials). The material of the buffer layer 121 may vary depending on the embodiment.

[0112] A pixel transistor PXT, including a first pixel transistor PXT1 and a second pixel transistor PXT2, and a storage capacitor Cst can be configured on the buffer layer 121.

[0113] The first pixel transistor PXT1 may include a first active layer ACT1A and a first gate electrode GE1A.

[0114] The first active layer ACT1A may be provided and / or disposed on the substrate 110 as a first semiconductor layer SCL1. The first active layer ACT1A may comprise a first semiconductor material (e.g., polysilicon). In one embodiment, the semiconductor patterns provided and / or disposed on the first semiconductor layer SCL1 (e.g., the active layer of at least one pixel transistor PXT and / or at least one driving transistor) may be formed simultaneously using the same material.

[0115] The first gate electrode GE1A may overlap with a portion of the first active layer ACT1A (e.g., the channel region). In one embodiment, the first gate electrode GE1A may be provided and / or configured on a first conductive layer CDL1 over a first insulating layer 122 covering the first semiconductor layer SCL1.

[0116] In one embodiment, the first pixel transistor PXT1 may further include a first electrode (e.g., a source electrode) connected to a portion (e.g., a source region) of the first active layer ACT1A and a second electrode (e.g., a drain electrode) connected to another portion (e.g., a drain region) of the first active layer ACT1A. Alternatively, the first pixel transistor PXT1 may not include additional source electrodes and / or additional drain electrodes, but rather the source electrodes and / or drain electrodes of the first pixel transistor PXT1 may be formed by the source regions and / or drain regions of the first active layer ACT1A. Figure 5 The illustration shows an embodiment where the first pixel transistor PXT1 does not include additional source and drain electrodes, but rather uses the source and drain regions of the first active layer ACT1A as the source and drain electrodes, respectively. In one embodiment, the first pixel transistor PXT1 may be integrally formed and / or connected to the active layer of at least one other pixel transistor PTX, which includes an active layer provided in the first semiconductor layer SCL1.

[0117] The first pixel transistor PXT1 can be connected to other circuit elements, wiring, and / or light-emitting elements EL, etc., as needed via at least one bridging electrode. For example, the first pixel transistor PXT1 can be connected to the light-emitting element EL of the corresponding pixel PX via a first bridging electrode BRE1 and a second bridging electrode BRE2.

[0118] The storage capacitor Cst may include a first capacitor electrode CE1A and a second capacitor electrode CE2A. A second insulating layer 123 may be disposed between the first capacitor electrode CE1A and the second capacitor electrode CE2A, and the first capacitor electrode CE1A and the second capacitor electrode CE2A overlap each other.

[0119] A first capacitor electrode CE1A may be provided and / or configured in the first conductive layer CDL1. In one embodiment, the first capacitor electrode CE1A may be integrally formed and / or connected with the gate electrode of at least one pixel transistor PTX storing capacitance Cst. For example, the first capacitor electrode CE1A may be... Figure 4 The gate electrode of the driving transistor T1 is integrally formed and / or connected.

[0120] The second capacitor electrode CE2A may be provided and / or configured in the second conductive layer CDL2. In one embodiment, the second conductive layer CDL2 may be provided and / or configured on the second insulating layer 123 covering the first conductive layer CDL1.

[0121] The second pixel transistor PXT2 may include a second active layer ACT2A and a second gate electrode GE2A. In one embodiment, the second pixel transistor PXT2 may also include a bottom electrode BG. In one embodiment, the second pixel transistor PXT2 may also include a source electrode SE2 (also referred to as the "second source electrode") and a drain electrode DE2 (also referred to as the "second drain electrode") connected to the second active layer ACT2A.

[0122] The bottom electrode BG of the second pixel transistor PXT2 can be disposed below the second active layer ACT2A, such that it overlaps with at least a portion of the second active layer ACT2A (e.g., at least a portion of the second active layer ACT2A including a channel region overlapping with the second gate electrode GE2A). In one embodiment, the bottom electrode BG can be provided and / or disposed in the second conductive layer CDL2. In one embodiment, the bottom electrode BG can be connected to the gate electrode (e.g., the second gate electrode GE2A) or the source electrode SE2 of the second pixel transistor PXT2, thereby serving as a back-gate electrode for adjusting the characteristics of the second pixel transistor PXT2.

[0123] The second active layer ACT2A may be provided and / or disposed on the substrate 110 as a second semiconductor layer SCL2. In one embodiment, the second semiconductor layer SCL2 may be provided and / or disposed on the third insulating layer 124 covering the second conductive layer CDL2. The second active layer ACT2A may contain a second semiconductor material (e.g., an oxide semiconductor) different from the first semiconductor material. For example, the second active layer ACT2A may include at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), indium-zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium-gallium oxide (IGO), indium-gallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-zinc-tin oxide (IZTO), indium-tin-gallium-zinc oxide (ITGZO), or other oxide semiconductors. In one embodiment, the semiconductor patterns (e.g., the active layer of at least one pixel transistor PXT and / or at least one driving transistor) provided and / or disposed on the second semiconductor layer SCL2 may be formed simultaneously using the same material.

[0124] The second gate electrode GE2A may overlap with a portion of the second active layer ACT2A (e.g., the channel region). In one embodiment, the second gate electrode GE2A may be provided and / or configured on a third conductive layer CDL3 over a fourth insulating layer 125 covering the second semiconductor layer SCL2.

[0125] The source electrode SE2 and drain electrode DE2 of the second pixel transistor PXT2 may be provided and / or disposed on a fourth conductive layer CDL4 above a fifth insulating layer 126 covering the third conductive layer CDL3. In one embodiment, the second pixel transistor PXT2 may also not include an additional source electrode SE2 and / or drain electrode DE2, but instead include a source electrode and / or drain electrode integrally formed with the source region and / or drain region of the second active layer ACT2A.

[0126] In one embodiment, at least one bridging electrode may also be provided in the fourth conductive layer CDL4. For example, a first bridging electrode BRE1 connected to the first pixel transistor PXT1 may be provided in the fourth conductive layer CDL4.

[0127] In one embodiment, the first bridging electrode BRE1 can be connected to the light-emitting element EL of the corresponding pixel PX via the second bridging electrode BRE2. In one embodiment, the second bridging electrode BRE2 can be provided and / or configured on the fifth conductive layer CDL5 above the sixth insulating layer 127 covering the fourth conductive layer CDL4.

[0128] The electrodes, conductive patterns, and / or wirings provided on the conductive layers of circuit layer 120 may include at least one conductive material. For example, the electrodes, conductive patterns, and / or wirings provided on the first conductive layer CDL1, the second conductive layer CDL2, the third conductive layer CDL3, the fourth conductive layer CDL4, and the fifth conductive layer CDL5 may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, or other conductive materials. In one embodiment, the electrodes, conductive patterns, and / or wirings disposed on the same conductive layer may be formed simultaneously using the same conductive material.

[0129] In one embodiment, the electrodes, conductive patterns, and / or wirings provided on the conductive layers of circuit layer 120 may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns, and / or wirings provided in the first conductive layer CDL1, the second conductive layer CDL2, the third conductive layer CDL3, the fourth conductive layer CDL4, and the fifth conductive layer CDL5 may have a single-layer or multi-layer structure.

[0130] In one embodiment, the electrodes, conductive patterns, and / or wirings provided in the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may comprise a metal (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and other metals, or alloys thereof), and have a single-layer or multi-layer structure. For example, the electrodes, conductive patterns, and / or wirings provided in the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may be formed as a three-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). The fourth conductive layer CDL4 and the fifth conductive layer CDL5 may comprise the same material or different materials. The materials comprised in each conductive layer of the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may vary in various ways depending on the embodiment.

[0131] In one embodiment, circuit layer 120 may include multiple inorganic insulating layers. For example, each of the insulating layers below the fourth conductive layer CDL4 (e.g., buffer layer 121, first insulating layer 122, second insulating layer 123, third insulating layer 124, fourth insulating layer 125, and fifth insulating layer 126) may be a single-layer or multi-layer inorganic insulating layer. Each inorganic insulating layer may contain an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials).

[0132] The first insulating layer 122 may be disposed on the buffer layer 121 (or the substrate 110). The first insulating layer 122 may cover the pattern provided on the first semiconductor layer SCL1 (e.g., the first active layer ACT1A). In one embodiment, the first insulating layer 122 may include a silicon oxide layer containing silicon oxide.

[0133] The second insulating layer 123 may be disposed over the first insulating layer 122. The second insulating layer 123 may cover the pattern provided on the first conductive layer CDL1 (e.g., the first gate electrode GE1A and the first capacitor electrode CE1A). In one embodiment, the second insulating layer 123 may include a silicon nitride layer containing silicon nitride or a silicon oxynitride layer containing silicon oxynitride.

[0134] A third insulating layer 124 may be disposed over the second insulating layer 123. The third insulating layer 124 may cover the pattern provided on the second conductive layer CDL2 (e.g., the bottom electrode BG of the second pixel transistor PXT2 and the second capacitor electrode CE2A). In one embodiment, the third insulating layer 124 may include a first layer 124A containing silicon nitride or silicon oxynitride (e.g., a silicon nitride layer or a silicon oxynitride layer) and a second layer 124B containing silicon oxide (e.g., a silicon oxide layer).

[0135] A fourth insulating layer 125 may be disposed over the third insulating layer 124. The fourth insulating layer 125 may cover the pattern provided on the second semiconductor layer SCL2 (e.g., the second active layer ACT2A). In one embodiment, the fourth insulating layer 125 may comprise a silicon oxide layer.

[0136] A fifth insulating layer 126 may be disposed over the fourth insulating layer 125. The fifth insulating layer 126 may cover the pattern provided on the third conductive layer CDL3 (e.g., the second gate electrode GE2A). In one embodiment, the fifth insulating layer 126 may include a first layer 126A containing silicon oxide (e.g., a silicon oxide layer) and a second layer 126B containing silicon nitride or silicon oxynitride (e.g., a silicon nitride layer or a silicon oxynitride layer).

[0137] In one embodiment, circuit layer 120 may further include at least one organic insulating layer. For example, each of the insulating layers above the fourth conductive layer CDL4 (e.g., the sixth insulating layer 127 and the seventh insulating layer 128) may include an organic insulating layer. Each organic insulating layer may contain an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or other organic insulating materials).

[0138] The sixth insulating layer 127 may be disposed on the fifth insulating layer 126. The sixth insulating layer 127 may cover the pattern provided on the fourth conductive layer CDL4 (e.g., the source electrode SE2, drain electrode DE2 and first bridging electrode BRE1 of the second pixel transistor PXT2).

[0139] The seventh insulating layer 128 may be disposed above the sixth insulating layer 127. The seventh insulating layer 128 may cover the pattern (e.g., the second bridging electrode BRE2) provided on the fifth conductive layer CDL5.

[0140] A light-emitting element layer 130 may be disposed above the circuit layer 120. For example, the light-emitting element layer 130 may be located at least in the display area DA and may be disposed above the seventh insulating layer 128. In embodiments where the circuit layer 120 does not include the fifth conductive layer CDL5 and the seventh insulating layer 128, the light-emitting element layer 130 may be disposed above the sixth insulating layer 127.

[0141] The light-emitting element layer 130 may include light-emitting elements EL of pixels PX. For example, the light-emitting element layer 130 may include: a pixel definition film 131 that divides each pixel PX into a light-emitting region EA; and light-emitting elements EL located in each light-emitting region EA. In one embodiment, the light-emitting element layer 130 may also include spacers 132 disposed on a portion of the pixel definition film 131.

[0142] Each light-emitting element EL may include: a first electrode ET1 (e.g., an anode electrode) located in each light-emitting region EA; a light-emitting layer EML and a second electrode ET2 (e.g., a positive electrode) sequentially disposed on the first electrode ET1. The first electrode ET1 of the light-emitting element ED may be connected to at least one pixel transistor PXT included in the corresponding pixel PX.

[0143] The first electrode ET1 of the light-emitting element EL can be a single-layer or multi-layer electrode containing a conductive material. In one embodiment, the first electrode ET1 can contain a metallic material with high reflectivity. For example, the first electrode ET1 can have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or a multi-layer structure containing indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), or nickel (Ni) (e.g., ITO / Mg, ITO / MgF, ITO / Ag, ITO / Ag / ITO, etc.).

[0144] The emissive layer (EML) of a light-emitting element (EL) can contain either high-molecular-weight or low-molecular-weight materials. Light emitted from the EML contributes to image display.

[0145] The second electrode ET2 of the light-emitting element EL may contain a conductive material. In one embodiment, the second electrode ET2 may be a common film formed by covering the light-emitting layer EML and the pixel definition film PDL throughout the display area DA. In one embodiment, the second electrode ET2 may be made of a transparent conductive material such as ITO, IZO, ZnO, or ITZO that allows light to pass through, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0146] The pixel defining film 131 may have openings corresponding to each light-emitting region EA and surround the light-emitting region EA. For example, the pixel defining film 131 may be formed to cover the edge of the first electrode ET1 of the light-emitting element EL, and may include openings that expose the remaining portion of the first electrode ET1. The area of ​​the exposed first electrode ET1 that overlaps with (or includes) the light-emitting layer EML may be defined as the light-emitting region EA of each pixel PX. In one embodiment, the pixel defining film 131 may include an organic insulating layer.

[0147] Spacer 132 may be disposed on a portion of pixel definition film 131. In one embodiment, spacer 132 may include an organic insulating layer. Spacer 132 may contain the same material as pixel definition film 131 or a different material. Pixel definition film 131 and spacer 132 may be formed sequentially by their respective masking processes, or simultaneously and / or integrally formed using a halftone mask.

[0148] The encapsulation layer 140 can be disposed on the light-emitting element layer 130. The encapsulation layer 140 can cover the light-emitting element layer 130 in the display area DA and extend into the non-display area NA and connect with the circuit layer 120. The encapsulation layer 140 can prevent oxygen or moisture from penetrating into the light-emitting element layer 130 and mitigate electrical and / or physical shocks to the circuit layer 120 and the light-emitting element layer 130.

[0149] In one embodiment, the encapsulation layer 140 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 sequentially disposed on the light-emitting element layer 130. Each of the encapsulation layers 141 and 143 may be an inorganic encapsulation layer containing inorganic materials. The second encapsulation layer 142 may be an organic encapsulation layer containing organic materials.

[0150] Figure 6 This is a top view showing a portion of a display panel 100 according to one embodiment. For example, Figure 6 Showing targets Figure 3 An embodiment of region A1.

[0151] Figure 7 This is a top view schematically illustrating a driving transistor (DRT) and a dummy pattern (DMP) of one embodiment. For example, Figure 7 Showing targets Figure 6 An embodiment of region A2.

[0152] exist Figures 1 to 5 Further reference Figure 6 and Figure 7The non-display area NA may include a driving circuit area DRA located around the display area DA and a dummy area DMA. In one embodiment, the dummy area DMA may be located inside and / or around the display area DA and / or the driving circuit area DRA. For example, the display panel 100 may include at least one dummy area DMA located around the display area DA and / or the driving circuit area DRA; and at least one dummy area DMA located inside the driving circuit area DRA (e.g., between a portion of the hierarchical circuits ST).

[0153] The drive circuit region DRA may be configured with hierarchical circuits ST of the first drive circuit DRV. For example, the drive circuit region DRA may include a hierarchical region for configuring the hierarchical circuits ST provided in the first drive circuit DRV.

[0154] Each hierarchical circuit ST may include at least one scan hierarchical circuit for generating at least one scan signal and / or at least one light emission hierarchical circuit for generating at least one light emission control signal. Each hierarchical circuit ST may include multiple driving transistors DRT and at least one capacitor (e.g., at least one driving capacitor provided at the output of each hierarchical circuit ST). The structure of each hierarchical circuit ST and the first driving circuit DRV including the hierarchical circuit ST is not particularly limited and may be varied according to embodiments.

[0155] Figure 7 Based on a pattern of a semiconductor layer (e.g., a first semiconductor layer SCL1) and a conductive layer (e.g., a fourth conductive layer CDL4) provided on circuit layer 120, only the approximate shape of the driving transistor DRT is shown. The shape, configuration, and / or structure of the driving transistor DRT can be varied according to embodiments.

[0156] In one embodiment, the driving transistor DRT may include an active layer ACT, a source electrode SE connected to different portions of the active layer ACT, and a drain electrode DE. The driving transistor DRT may also include a gate electrode overlapping the active layer ACT.

[0157] In one embodiment, the source electrode SE of the driving transistor DRT may be disposed on a portion of the active layer ACT (e.g., the source region) and may be connected to the active layer ACT via at least one contact hole CH. In another embodiment, the drain electrode DE of the driving transistor DRT may be disposed on another portion of the active layer ACT (e.g., the drain region) and may be connected to the other portion of the active layer ACT via at least one other contact hole CH.

[0158] In one embodiment, the hierarchical circuit ST can be configured on the display panel 100 in a shape adapted to the shape of the display area DA and / or the display panel 100. For example, the hierarchical circuit ST located around the corner portions of the display area DA and / or the main area MA can be configured in each hierarchical region extending along an oblique direction inclined relative to the first direction DR1 and the second direction DR2. In one embodiment, a dummy area DMA can be configured in the space between the hierarchical circuit STs extending in different directions and / or angles around the corner portions of the display area DA and / or the main area MA.

[0159] At least one dummy pattern (DMP) can be configured in each dummy region (DMA). In one embodiment, multiple dummy pattern DMPs can be configured in each dummy region (DMA) with a generally uniform size and / or spacing.

[0160] In one embodiment, the dummy region DMA may include patterns formed on the display panel 100, such as patterns (e.g., active layers and electrodes) constituting circuit elements (e.g., transistors and capacitors) located in the display region DA and / or driving circuit region DRA, and dummy patterns DMP for making the density of wiring located inside and / or around the display region DA and / or driving circuit region DRA more uniform. For example, the dummy pattern DMP may be located around the circuit elements and wiring formed in the circuit layer 120 of the display panel 100, and may be suitably configured in empty spaces where the circuit elements and wiring are not configured. In one embodiment, the dummy pattern DMP located at the edge of the dummy region DMA may be adjacent to at least one pixel transistor PXT or driving transistor located around it, and may be spaced apart from the pixel transistor PXT or driving transistor and configured in the first semiconductor layer SCL1.

[0161] Although not in Figure 6 As shown, scan lines SL and / or light emission control lines ECL can be configured between the hierarchical circuit ST and the pixel PX. In one embodiment, the dummy pattern DMP is appropriately and / or uniformly configured in the remaining areas of the display area DA and / or the driving circuit area DRA, excluding dense areas such as circuit elements, scan lines SL and / or light emission control lines ECL.

[0162] By configuring a dummy pattern (DMP), the density of the pattern formed on the display panel 100 can be made more uniform. This reduces process deviations in individual circuit components and / or wiring, and allows the pattern on the display panel 100 to be formed appropriately according to the desired shape and / or size.

[0163] In one embodiment, each dummy region (DMA) may be configured with at least one dummy via (DMH) corresponding to each dummy pattern (DMP). In another embodiment, each dummy via (DMH) may be configured on top of each dummy pattern (DMP). The dummy via (DMH) is formed in such a way that it penetrates multiple inorganic insulating layers covering the dummy pattern (DMP), thereby exposing a portion of each dummy pattern (DMP). According to an embodiment, at least one masking layer and / or a connecting pattern may also be configured on top of the dummy pattern (DMP). Detailed descriptions related to this will follow.

[0164] By forming a dummy via DMH, the characteristics of circuit elements (e.g., transistors) formed on the display panel 100 can be made more uniform. For example, by forming a dummy via DMH, the organic insulating layer (e.g., transistors) formed in the circuit layer 120 of the display panel 100 can be uniformly controlled. Figure 5 The dehydrogenation of the sixth insulating layer 127) thereby controls the circuit elements of the circuit layer 120 to have more uniform characteristics.

[0165] Power wiring can be configured inside and / or around the display area DA and / or the driving circuit area DRA. For example, pixel power wiring PL can be configured inside and / or around the display area DA. Pixel power wiring PL will transmit power voltages to drive pixel PX, such as a first pixel power voltage ELVDD, a second pixel power voltage ELVSS, a first initialization voltage VINT1, a second initialization voltage VINT2, and / or a bias voltage VOBS, etc., to pixel PX. Figure 6 In the diagram, the pixel power lines PL represent the approximate locations and shapes of two pixel power lines PL passing through the area between the display area DA and the driving circuit area DRA. In one embodiment, the two pixel power lines PL may be a first initialization power line VIL1 and a second initialization power line VIL2, but are not limited thereto. In one embodiment, the two pixel power lines PL may be configured in the fourth conductive layer CDL4 or the fifth conductive layer CDL5 of the circuit layer 120, respectively. For example, the two pixel power lines PL may be configured spaced apart from each other in the fifth conductive layer CDL5 of the circuit layer 120.

[0166] A drive power supply line DPL may be configured inside and / or around the drive circuit region DRA. The drive power supply line DPL supplies the power supply voltage used to drive the first drive circuit DRV, such as a high-potential first drive power supply voltage (e.g., gate high-level voltage) and a low-potential second drive power supply voltage (e.g., gate low-level voltage), to the hierarchical circuit ST. Figure 6The diagram shows the approximate location and shape of multiple (e.g., six) drive power lines DPL passing through the drive circuit region DRA. In one embodiment, a portion of the multiple drive power lines DPL can supply a high-potential first drive power voltage to the hierarchical circuit ST, and another portion of the multiple drive power lines DPL can supply a low-potential second drive power voltage to the hierarchical circuit ST. In one embodiment, each of the multiple drive power lines DPL can be configured in the fourth conductive layer CDL4 or the fifth conductive layer CDL5 of the circuit layer 120. The type, number, location, and / or shape of the pixel power lines PL and drive power lines DPL provided on the display panel 100 can be varied according to embodiments.

[0167] Figure 8 This is a cross-sectional view showing a display panel 100 according to one embodiment. Figure 9 This is a cross-sectional view showing a display panel 100 according to one embodiment. Figure 10 This is a cross-sectional view illustrating a display panel 100 according to one embodiment. For example, Figures 8 to 10 A cross-section of the display panel 100 is shown schematically of a portion of the non-display area NA, which includes a portion of the drive circuit area DRA and a portion of the dummy area DMA. Figures 8 to 10 Different embodiments of the connection pattern CNP for the masking layer SHL connected in the dummy region DMA are shown.

[0168] exist Figures 1 to 7 Further reference Figures 8 to 10 The circuit layer 120 may further include circuit elements (e.g., driving transistors DRT and driving capacitors DRC of each hierarchical circuit ST) constituting the first driving circuit DRV, and dummy patterns DMP located around the circuit elements. In one embodiment, the dummy patterns DMP may also be disposed around pixels PX (e.g., pixels PX located at the edge of the display area DA). At least one power supply line (e.g., at least one driving power supply line DPL and / or pixel power supply line PL) may be disposed around the dummy patterns DMP.

[0169] Figures 8 to 10 As an example of elements that can be provided in the drive circuit region DRA of circuit layer 120, a first drive transistor DRT1, a drive capacitor DRC, and a second drive transistor DRT2 are shown provided in the hierarchical region of each hierarchical circuit ST. Furthermore, Figures 8 to 10 As an example of an element that can be provided in the dummy region DMA of circuit layer 120, two dummy patterns DMPs adjacent to each other and a dummy via DMH disposed on the dummy patterns DMPs, as well as a masking layer SHL, are shown. Further, in Figures 8 to 10As an example of power wiring that can be configured around a dummy pattern DMP, a drive power wiring DPL provided on the fifth conductive layer CDL5 is shown.

[0170] In one embodiment, the first driving transistor DRT1 (also referred to as the "first transistor") may represent a first type of transistor (e.g., a P-type polysilicon transistor) in the driving transistors DRT constituting each hierarchical circuit ST, which contains a first semiconductor material (e.g., polysilicon). In one embodiment, the second driving transistor DRT2 (also referred to as the "second transistor") may represent a second type of transistor (e.g., an N-type oxide transistor) in the driving transistor DRT, which contains a second semiconductor material (e.g., oxide semiconductor). In one embodiment, the first driving circuit DRV may be formed as a CMOS circuit including the first driving transistor DRT1 and the second driving transistor DRT2.

[0171] The first driving transistor DRT1 may include a first active layer ACT1B and a first gate electrode GE1B.

[0172] The first active layer ACT1B may be provided and / or disposed on the substrate 110 as a first semiconductor layer SCL1. The first active layer ACT1B may contain a first semiconductor material.

[0173] The first gate electrode GE1B may overlap with a portion (e.g., a channel region) of the first active layer ACT1B. In one embodiment, the first gate electrode GE1B may be provided and / or configured in the first conductive layer CDL1.

[0174] In one embodiment, the first driving transistor DRT1 may further include a first electrode connected to a portion of the first active layer ACT1B (e.g., a source electrode or drain electrode integrally connected to the first electrode TE1 of the second driving transistor DRT2). In one embodiment, the first driving transistor DRT1 may further include a second electrode connected to another portion of the first active layer ACT1B (e.g., a drain electrode or source electrode provided in the fourth conductive layer CDL4). Alternatively, the first driving transistor DRT1 may not include additional source and / or drain electrodes, but rather the source and / or drain electrodes of the first driving transistor DRT1 may be formed by the source and / or drain regions of the first active layer ACT1B. In one embodiment, the first driving transistor DRT1 may also be integrally formed and / or connected to the active layer of at least one other first driving transistor DRT1, said at least one other first driving transistor DRT1 including each active layer provided in the first semiconductor layer SCL1.

[0175] The driving capacitor DRC may include a first capacitor electrode CE1B and a second capacitor electrode CE2B. A second insulating layer 123 is disposed between the first capacitor electrode CE1B and the second capacitor electrode CE2B, and the first capacitor electrode CE1B and the second capacitor electrode CE2B overlap each other.

[0176] The first capacitor electrode CE1B may be provided and / or disposed in the first conductive layer CDL1. In one embodiment, the first capacitor electrode CE1B may be integrally formed and / or connected to the first gate electrode GE1B of at least one first driving transistor DRT1.

[0177] The second capacitor electrode CE2B may be provided and / or disposed on the second conductive layer CDL2. In one embodiment, the second conductive layer CDL2 may be provided and / or disposed on the second insulating layer 123.

[0178] The second driving transistor DRT2 may include a second active layer ACT2B and a second gate electrode GE2B. In one embodiment, the second driving transistor DRT2 may or may not include a bottom electrode provided in the second conductive layer CDL2, etc. In one embodiment, the second driving transistor DRT2 may further include a first electrode TE1 and a second electrode TE2 connected to different portions of the second active layer ACT2B.

[0179] The first electrode TE1 can be one of the source electrode and the drain electrode of the second driving transistor DRT2, and the second electrode TE2 can be the other of the source electrode and the drain electrode of the second driving transistor DRT2. For example, the first electrode TE1 can be connected to one of the source region and the drain region of the second active layer ACT2B using at least one contact hole CH penetrating the fourth and fifth insulating layers 125 and 126, and the second electrode TE2 can be connected to the other of the source region and the drain region of the second active layer ACT2B using at least one other contact hole CH penetrating the fourth and fifth insulating layers 125 and 126. In one embodiment, the first electrode TE1 can also be connected to the source region or the drain region of the first active layer ACT1B provided in the first driving transistor DRT1 using at least one contact hole CH penetrating the first, second, third, fourth, and fifth insulating layers 122, 123, 124, 125, and 126.

[0180] The second active layer ACT2B may be provided and / or configured in the second semiconductor layer SCL2. The second active layer ACT2B may contain a second semiconductor material (e.g., an oxide semiconductor) that is different from the first semiconductor material. For example, the second active layer ACT2B may include at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), indium-zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium-gallium oxide (IGO), indium-gallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-zinc-tin oxide (IZTO), indium-tin-gallium-zinc oxide (ITGZO), or other oxide semiconductors.

[0181] The second gate electrode GE2B may overlap with a portion of the second active layer ACT2B (e.g., the channel region). In one embodiment, the second gate electrode GE2B may be provided and / or configured in the third conductive layer CDL3.

[0182] The first electrode TE1 and the second electrode TE2 of the second driving transistor DRT2 may be provided and / or disposed on the fourth conductive layer CDL4. In one embodiment, the second driving transistor DRT2 may also not include the additional first electrode TE1 and / or second electrode TE2, but instead include a source electrode and / or a drain electrode integrally formed with the source region and / or drain region of the second active layer ACT2B.

[0183] The dummy pattern (DMP) can be configured in the first semiconductor layer SCL1. For example, each dummy pattern (DMP) can be a semiconductor pattern containing the first semiconductor material.

[0184] Each dummy pattern (DMP) can be configured at a distance from the driving transistor (DRT) and the pixel transistor (PXT). For example, each dummy pattern (DMP) can be configured in the first semiconductor layer (SCL1) at a distance from the first active layer (ACT1B) of the first driving transistor (DRT1) and / or the first active layer (ACT1A) of the first pixel transistor (PXT1) located on the periphery.

[0185] The first active layer ACT1B and first gate electrode GE1B of the first driving transistor DRT1, the first capacitor electrode CE1B and second capacitor electrode CE2B of the driving capacitor DRC, the second active layer ACT2B and second gate electrode GE2B of the second driving transistor DRT2, and the dummy pattern DMP can be covered by an inorganic insulating layer above the first semiconductor layer SCL1. For example, the first active layer ACT1B and first gate electrode GE1B, the first capacitor electrode CE1B and second capacitor electrode CE2B, the second active layer ACT2B and second gate electrode GE2B, and the dummy pattern DMP can be covered by first, second, third, fourth, and fifth insulating layers 122, 123, 124, 125, and 126.

[0186] A dummy via (DMH) can be disposed on a dummy pattern (DMP). The DMH can penetrate the inorganic insulating layer covering the dummy pattern (DMP) to expose a portion of each dummy pattern (DMP). For example, the DMH can be formed by penetrating the first, second, third, fourth, and fifth insulating layers 122, 123, 124, 125, and 126 on each dummy pattern (DMP).

[0187] A masking layer SHL can be disposed on the dummy pattern DMP. In one embodiment, the masking layer SHL can be provided on the fourth conductive layer CDL4 together with the first electrode TE1 and the second electrode TE2 of the second driving transistor DRT2, and can be disposed at least inside each dummy via DMH. For example, each masking layer SHL can be disposed inside the dummy via DMH disposed on each dummy pattern DMP and around the periphery of the dummy via DMH, and can cover the side of the inorganic insulating layer exposed through the dummy via DMH. Each masking layer SHL can partially or completely fill the interior of each dummy via DMH.

[0188] In one embodiment, the masking layers SHL disposed on the dummy pattern DMP can be separate from each other, but are not limited thereto. For example, the masking layers SHL disposed on at least two dummy pattern DMPs can also be integrally formed, thereby substantially forming a single pattern.

[0189] In one embodiment, each shielding layer SHL can be a single-layer or multi-layer conductive pattern containing metal. For example, the shielding layer SHL can be formed simultaneously using the same conductive material as the first electrode TE1 and the second electrode TE2 of the second driving transistor DRT2. In one embodiment, each of the shielding layer SHL, the first electrode TE1, and the second electrode TE2 of the second driving transistor DRT2 can be a metal pattern formed from a three-layer structure of titanium / aluminum / titanium (Ti / Al / Ti).

[0190] In one embodiment, each shielding layer SHL can be connected to a power supply line located on its periphery. For example, each shielding layer SHL can be connected to a power supply line (e.g., a drive power supply line DPL or a pixel power supply line PL) provided on a fourth conductive layer CDL4 or a fifth conductive layer CDL5, which is disposed on the inorganic insulating layer of the circuit layer 120. By connecting the conductive shielding layers SHL to power supply lines to which a constant voltage is applied, the operation of the display panel 100 can be stabilized.

[0191] In one embodiment, the display panel 100 may further include at least one connection pattern CNP connecting at least one shielding layer SHL to its surrounding power wiring. In one embodiment, the connection pattern CNP may be located in a conductive layer between a first semiconductor layer SCL1 configured with a dummy pattern DMP and a fourth conductive layer CDL4 configured with the shielding layer SHL. For example, as Figure 8 , Figure 9 as well as Figure 10 As shown in the figures, the connection pattern CNP can be provided in the first conductive layer CDL1, the second conductive layer CDL2, or the third conductive layer CDL3. Alternatively, the connection pattern CNP can also be formed by a multilayer pattern provided in at least two of the first conductive layers CDL1, the second conductive layer CDL2, and the third conductive layer CDL3. In one embodiment, considering the patterns of the conductive layers disposed in the regions where the dummy patterns DMPs are located, the conductive layers used to configure the connection pattern CNP can be selected according to each dummy region DMA or a sub-region within each dummy region DMA.

[0192] In one embodiment, the connection pattern CNP can be connected to the power wiring surrounding the dummy pattern DMP via at least one bridging electrode (e.g., Figures 8 to 10 The drive unit power wiring (DPL) is connected. For example, the connection pattern CNP can be connected to the power wiring provided on the fifth conductive layer CDL5 via the third bridging electrode BRE3 provided on the fourth conductive layer CDL4. The third bridging electrode BRE3 can be connected to the connection pattern CNP via at least one contact hole CH formed in the inorganic insulating layer covering the connection pattern CNP. The third bridging electrode BRE3 can be connected to the power wiring (e.g., drive unit power wiring DPL or pixel power wiring PL) of the fifth conductive layer CDL5 via at least one through hole VH formed in the sixth insulating layer 127 covering the third bridging electrode BRE3.

[0193] Alternatively, the connection pattern CNP can be directly connected to the power wiring surrounding the dummy pattern DMP. For example, the connection pattern CNP can also be connected to the power wiring provided on the fourth conductive layer CDL4 without the need for additional bridging electrodes.

[0194] The circuit elements of the driving circuit region DRA and the pattern of the dummy region DMA can be covered by at least one organic insulating layer. For example, the driving transistor DRT, the driving capacitor DRC, the dummy pattern DMP, and the shielding layer SHL can be covered by the sixth insulating layer 127 and / or the seventh insulating layer 128 disposed above the fourth conductive layer CDL4.

[0195] Figure 11 This is a cross-sectional view illustrating a display panel 100 according to one embodiment. For example, Figure 11 The diagram shows a connection structure for the shielding layer SHL and power wiring that differs from the previous one. Figures 8 to 10 Examples of implementations.

[0196] exist Figures 1 to 10 Further reference Figure 11 At least one shielding layer SHL can be directly connected to the surrounding power wiring (e.g., drive power wiring DPL or pixel power wiring PL) without additional connection patterns. For example, the at least one shielding layer SHL can extend into the area where the surrounding power wiring is disposed and overlap with the power wiring, and can be directly connected to the power wiring. In this case, the display panel 100 may not include additional connection patterns for connecting the shielding layer SHL to the power wiring. In one embodiment, the shielding layer SHL can be disposed on the fourth conductive layer CDL4 and connected to the power wiring disposed on the fifth conductive layer CDL5 using at least one via VH through the sixth insulating layer 127. Alternatively, the shielding layer SHL can also be integrally formed with the power wiring disposed on the fourth conductive layer CDL4.

[0197] In one embodiment, at least two adjacent shielding layers SHL can be integrally formed. For example, the at least two shielding layers SHL can substantially form a pattern.

[0198] Figure 12 This is a cross-sectional view showing a display panel 100 according to one embodiment. Figure 13 This is a cross-sectional view illustrating a display panel 100 according to one embodiment. For example, Figure 12 and Figure 13 This shows that the SHL shielding layer is different from Figures 8 to 11 Examples of implementations.

[0199] exist Figures 1 to 11 Further reference Figure 12 and Figure 13 The shielding layer SHL can be an inorganic insulating layer that is fully or partially disposed above the fifth insulating layer 126. For example, as Figure 12As shown, the shielding layer SHL can be configured fully between the fifth insulating layer 126 and the sixth insulating layer 127, and can cover the pattern provided on the fourth conductive layer CDL4. Alternatively, as... Figure 13 The shielding layer SHL shown may be partially disposed on the fifth insulating layer 126. For example, the shielding layer SHL may be an insulating pattern disposed only inside and around each dummy via DMH. The shielding layer SHL may be covered by the sixth insulating layer 127.

[0200] In one embodiment, the shielding layer SHL can be a single-layer or multi-layer inorganic insulating layer containing nitrogen. For example, the shielding layer SHL can include a silicon nitride layer or a silicon oxynitride layer. In one embodiment, the shielding layer SHL can be a single-layer inorganic insulating layer composed of a silicon nitride layer or a silicon oxynitride layer. Alternatively, the shielding layer SHL can be a multi-layer inorganic insulating layer including a silicon nitride layer or a silicon oxynitride layer and a silicon oxide layer. By using a nitrogen-containing shielding layer SHL to cover the sides of the inorganic insulating layer exposed through the dummy via DMH, moisture penetration can be effectively prevented. This prevents damage to circuit components caused by outgassing of the organic insulating layer. For example, even if a transistor including an oxide semiconductor (e.g., a second driving transistor DRT2 or a second pixel transistor PXT2) is disposed around the dummy via DMH, the shielding layer SHL can cover the sides of the inorganic insulating layer, thereby preventing transistor degradation or malfunction caused by outgassing of the organic insulating layer.

[0201] In one embodiment, the shielding layer SHL can be an inorganic insulating layer with a high nitrogen content. For example, the shielding layer SHL can be an inorganic insulating layer with a high nitrogen content and a refractive index of 1.6 or higher. This provides more stable protection for surrounding circuit components.

[0202] according to Figures 8 to 13In some embodiments, dummy patterns (DMPs) and dummy vias (DMHs) can be formed around a first driving circuit DRV, including oxide transistors, and / or a pixel PX. For example, dummy patterns (DMPs) and dummy vias (DMHs) can be configured around the first driving circuit DRV, including a first driving transistor DRT1 and a second driving transistor DRT2, and / or in the space between a hierarchical circuit ST located in a driving circuit region DRA where the first driving circuit DRT1 is disposed. The first driving transistor DRT1 includes a first active layer ACT1B provided in a first semiconductor layer SCL1, and the second driving transistor DRT2 includes a second active layer ACT2B provided in a second semiconductor layer SCL2. Similarly, dummy patterns DMP and dummy vias DMH can be configured around the pixel circuit PXC of a pixel PX (e.g., a pixel PX located at at least one corner of the display area DA) that includes a first pixel transistor PXT1 and a second pixel transistor PXT2. The first pixel transistor PXT1 includes a first active layer ACT1A provided in the first semiconductor layer SCL1, and the second pixel transistor PXT2 includes a second active layer ACT2A provided in the second semiconductor layer SCL2. This allows for a more uniform and accurate formation of the patterns (e.g., circuit elements and / or wiring) of the circuit layer 120 configured on the display panel 100. Furthermore, it allows for a more uniform overall characteristic of the circuit elements (e.g., pixel transistors PXT and / or driving transistors DRT) configured on the circuit layer 120.

[0203] Furthermore, according to Figures 8 to 13In one embodiment, a shielding layer SHL can be formed inside and / or around each dummy via DMH. The shielding layer SHL covers the sides of the inorganic insulating layers (e.g., first, second, third, fourth, and fifth insulating layers 122, 123, 124, 125, 126) exposed through the dummy via DMH. In another embodiment, the shielding layer SHL may contain a moisture-blocking material. For example, the shielding layer SHL may be formed from a conductive pattern (or wiring) containing a metal with moisture-absorbing properties, such as titanium (Ti), or from an inorganic insulating layer (or inorganic insulating pattern) containing an inorganic insulating material such as nitrogen. This prevents or reduces the degradation and / or malfunction of circuit elements caused by the release of gas from organic insulating layers (e.g., sixth insulating layer 127, etc.). For example, by covering each dummy via DMH with the shielding layer SHL, degradation and / or malfunction of circuit elements can be prevented even if circuit elements such as oxide transistors are positioned close to the periphery of the dummy via DMH. Furthermore, since the surrounding circuit components can be stably protected by the shielding layer SHL, the dummy via DMH can be positioned closer to the periphery of the circuit components when necessary. This improves the design efficiency of the display panel 100. For example, the distance between the circuit components and the dummy via DMH can be appropriately shortened as needed, and the area of ​​the non-display area NA can be reduced.

[0204] In several embodiments, the shielding layer SHL can be formed as a conductive pattern (or wiring) and connected to the surrounding power wiring. For example, each shielding layer SHL can be connected to the surrounding power wiring through at least one connection pattern CNP and / or a third bridging electrode BRE3, or each shielding layer SHL can be directly connected to the surrounding power wiring without additional connection patterns or bridging electrodes. This prevents malfunctions of the display panel 100 caused by the shielding layer SHL and ensures the electrical stability of the display panel 100.

[0205] Figures 14 to 18 This is a cross-sectional view illustrating a method of manufacturing a display device 10 according to an embodiment. For example, Figures 14 to 18 Manufacturing process shown in sequence Figure 8 The steps of forming the display panel 100 include the steps of forming a circuit layer 120 such as a dummy pattern DMP, a dummy hole DMH, and a masking layer SHL.

[0206] Figures 14 to 17 The steps for forming a pattern of a non-display area NA, including a drive circuit region DRA and a dummy region DMA, are illustrated. The configuration in the pattern of the display area DA and / or the pattern formed on the same layer as the pattern of the non-display area NA can be formed simultaneously with the pattern of the non-display area NA. For example, Figure 5The first pixel transistor PXT1 and the second pixel transistor PXT2 can be formed simultaneously with the first driving transistor DRT1 and the second driving transistor DRT2, respectively.

[0207] exist Figures 1 to 13 Further reference Figure 14 Multiple semiconductor layers, conductive layers, and inorganic insulating layers can be formed on the substrate 110. In one embodiment, a buffer layer 121 can be formed first on the substrate 110, and a semiconductor layer, a conductive layer, and an inorganic insulating layer covering the semiconductor layer and the conductive layer can be formed on the buffer layer 121.

[0208] For example, on the substrate 110 on which the buffer layer 121 is formed, a first semiconductor layer SCL1 including a first active layer ACT1B of the first driving transistor DRT1 and a dummy pattern DMP, a first insulating layer 122 covering the pattern of the first semiconductor layer SCL1, a first conductive layer CDL1 including the first gate electrode GE1B of the first driving transistor DRT1 and / or the first capacitor electrode CE1B of the driving capacitor DRC, a second insulating layer 123 covering the pattern of the first conductive layer CDL1, a second conductive layer CDL2 including the second capacitor electrode CE2B of the driving capacitor DRC, a third insulating layer 124 covering the pattern of the second conductive layer CDL2, a second semiconductor layer SCL2 including the second active layer ACT2B of the second driving transistor DRT2, a fourth insulating layer 125 covering the pattern of the second semiconductor layer SCL2, a third conductive layer CDL3 including the second gate electrode GE2B of the second driving transistor DRT2, and a fifth insulating layer 126 covering the pattern of the third conductive layer CDL3 can be formed sequentially. In one embodiment, when manufacturing a display panel 100 that does not include the second conductive layer CDL2, the steps of forming the second conductive layer CDL2 and / or forming the second insulating layer 123 or the third insulating layer 124 can be omitted.

[0209] In one embodiment, in manufacturing such as Figures 8 to 10 In this embodiment of the display panel 100 including the connection pattern CNP, the connection pattern CNP can be formed during the steps of forming the first conductive layer CDL1, the second conductive layer CDL2, and / or the third conductive layer CDL3. For example, the connection pattern CNP overlapping a portion of each dummy pattern DMP can be formed in the first conductive layer CDL1.

[0210] In one embodiment, during the steps of forming each semiconductor layer or conductive layer, patterns of each semiconductor layer or conductive layer may also be formed in each pixel region PXA of the display region DA. For example, the first active layer ACT1A of the first pixel transistor PXT1 may be formed in the step of forming the first semiconductor layer SCL1, and the first gate electrode GE1B of the first pixel transistor PXT1 and / or the first capacitor electrode CE1A of the storage capacitor CsT may be formed in the step of forming the first conductive layer CDL1. Similarly, the second capacitor electrode CE2A of the storage capacitor CsT and / or the bottom electrode BG of the second pixel transistor PXT2 may be formed in the step of forming the second conductive layer CDL2, the second active layer ACT2A of the second pixel transistor PXT2 may be formed in the step of forming the second semiconductor layer SCL2, and the second gate electrode GE2 of the second pixel transistor PXT2 may be formed in the step of forming the third conductive layer CDL3.

[0211] exist Figures 1 to 14 Further reference Figure 15 Contact holes CH can be formed through an inorganic insulating layer (e.g., first, second, third, fourth, and fifth insulating layers 122, 123, 124, 125, 126) that penetrates the first semiconductor layer SCL1 to expose a portion of the first active layer ACT1B of the first driving transistor DRT1, and dummy holes DMH can be formed through the inorganic insulating layer to expose a portion of each of the dummy patterns DMP. In one embodiment, during the step of forming the dummy holes DMH, contact holes CH can also be formed to expose a portion of each of the second active layer ACT2B of the second driving transistor DRT2, the first active layer ACT1A of the first pixel transistor PXT1, the second active layer ACT2A of the second pixel transistor PXT2, and / or the connection pattern CNP.

[0212] exist Figures 1 to 15 Further reference Figure 16 A fourth conductive layer CDL4, including a first electrode TE1 and / or a second electrode TE2 of the second driving transistor DRT2, can be formed on the inorganic insulating layer. The first electrode TE1 of the second driving transistor DRT2 can be connected to a portion of the second driving transistor DRT2 through a contact hole CH that exposes a portion of the second driving transistor DRT2. In the step of forming the fourth conductive layer CDL4, the source electrode SE2 and / or drain electrode DE2 of the second pixel transistor PXT2, as well as the first bridging electrode BRE1, can be formed in each pixel region PXA of the display region DA.

[0213] In several embodiments, during the step of forming the fourth conductive layer CDL4, a shielding layer SHL can be formed inside the dummy via DMH. For example, a conductive material containing metal can be used to simultaneously form the first electrode TE1 and the second electrode TE2 of the second driving transistor DRT2 with the shielding layer SHL. In this case, the shielding layer SHL can be included in the fourth conductive layer CDL4. The shielding layer SHL can cover the side of the inorganic insulating layer exposed through the dummy via DMH. In one embodiment, the shielding layer SHL can be connected to each dummy pattern DMP and / or connection pattern CNP in the region where each dummy via DMH is formed. By forming the first electrode TE1 and the second electrode TE2 of the second driving transistor DRT2 simultaneously with the shielding layer SHL, the manufacturing process of the display panel 100 can be simplified and manufacturing efficiency improved.

[0214] In one embodiment, in manufacturing such as Figures 8 to 10 In this embodiment of the display panel 100 including the third bridging electrode BRE3, the third bridging electrode BRE3 can be formed during the step of forming the fourth conductive layer CDL4. The third bridging electrode BRE3 can be connected to the connection pattern CNP through the contact hole CH formed in the connection pattern CNP.

[0215] exist Figures 1 to 16 Further reference Figure 17 A sixth insulating layer 127, patterned to cover the fourth conductive layer CDL4, can be formed on the inorganic insulating layer. For example, the sixth insulating layer 127 may cover the first electrode TE1 and the second electrode TE2 of the second driving transistor DRT2, the shielding layer SHL, and / or the third bridging electrode BRE3, etc. In one embodiment, the sixth insulating layer 127 may include an organic insulating layer. In manufacturing such... Figures 8 to 10 In an embodiment of this display panel 100 including a third bridging electrode BRE3, a through-hole VH can be formed through the sixth insulating layer 127 to expose a portion of the third bridging electrode BRE3. For example... Figure 11 In one embodiment, where the shielding layer SHL is directly connected to the power wiring (e.g., the drive power wiring DPL) disposed on top of it, a through-hole VH can be formed through the sixth insulating layer 127 to expose a portion of the shielding layer SHL.

[0216] In one embodiment, during the step of forming the fourth conductive layer CDL4, at least one power line may also be formed on the inorganic insulating layer. Furthermore, a shielding layer SHL on the dummy pattern DMP adjacent to the power line may be integrally formed with the power line.

[0217] exist Figures 1 to 17 Further reference Figure 18Power wiring connected to at least one shielding layer SHL can be formed on the inorganic insulating layer and the sixth insulating layer 127. In one embodiment, the power wiring may be a driving power wiring DPL and / or a pixel power wiring PL provided on the fifth conductive layer CDL5. In one embodiment, during the step of forming the fifth conductive layer CDL5, a second bridging electrode BRE2, etc., may be formed in each pixel region PXA of the display area DA.

[0218] Subsequently, a seventh insulating layer 128 can be formed covering the pattern of the fifth conductive layer CDL5. In one embodiment, the seventh insulating layer 128 may include an organic insulating layer.

[0219] Through the above process, the circuit layer 120 of the display panel 100 can be formed. In one embodiment, the display panel 100 includes... Figure 5 and Figure 8 In the case of the light-emitting element layer 130 and the encapsulation layer 140 shown in the figure, the light-emitting element layer 130 and the encapsulation layer 140 can be sequentially formed on the circuit layer 120. Through the above process, the display panel 100 of the embodiment and the display device 10 including the display panel 100 can be obtained.

[0220] Figure 19 and Figure 20 This is a cross-sectional view illustrating a method of manufacturing a display device 10 according to an embodiment. For example, Figure 19 and Figure 20 Show Figure 12 The steps of forming the dummy hole DMH and the shielding layer SHL in the manufacturing process of the display panel 100.

[0221] exist Figures 1 to 18 Further reference Figure 19 and Figure 20 The pattern of the fourth conductive layer CDL4 and the masking layer SHL can be formed sequentially using different materials. For example, after forming the first electrode TE1 and the second electrode TE2 of the second driving transistor DRT2 on the inorganic insulating layer of the circuit layer 120 using a conductive material, the masking layer SHL can be formed on the inorganic insulating layer using a nitrogen-containing inorganic insulating material. In one embodiment, the masking layer SHL can be formed overlapping the pattern of the fourth conductive layer CDL4, or only partially formed in the dummy region DMA.

[0222] Subsequently, they formed in sequence. Figure 12 and Figure 13 The sixth insulating layer 127, the fifth conductive layer CDL5, and the seventh insulating layer 128 shown herein can form the circuit layer 120 of the display panel 100. In one embodiment, the display panel 100 includes... Figure 5 and Figure 12In the case of the light-emitting element layer 130 and the encapsulation layer 140 shown, the light-emitting element layer 130 and the encapsulation layer 140 can be sequentially formed on the circuit layer 120.

[0223] While embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art should understand that other specific embodiments can be implemented without altering the technical concept or essential technical features of the present invention. Therefore, the embodiments described above should be understood as merely examples and not limitations in all respects.

Claims

1. A display device, characterized in that, include: substrate; The first transistor includes a first active layer of a first semiconductor layer disposed on the substrate and a first gate electrode overlapping the first active layer. The second transistor includes a second active layer of a second semiconductor layer disposed on the substrate and a second gate electrode overlapping the second active layer. A dummy pattern is spaced apart from the first active layer and disposed on the first semiconductor layer; An inorganic insulating layer is disposed on the substrate and covers the first active layer, the dummy pattern, the first gate electrode, the second active layer, and the second gate electrode. A dummy hole penetrates the inorganic insulating layer above the dummy pattern; as well as A shielding layer is disposed at least inside the dummy hole and covers the sides of the inorganic insulating layer exposed through the dummy hole.

2. The display device according to claim 1, characterized in that, Also includes: An organic insulating layer is disposed on the inorganic insulating layer and covers the first transistor, the second transistor, and the shielding layer.

3. The display device according to claim 1, characterized in that, The shielding layer is a metallic conductive pattern.

4. The display device according to claim 3, characterized in that, The second transistor further includes a first electrode, which is disposed on the inorganic insulating layer and connected to the source region or drain region of the first active layer. The first electrode and the shielding layer are disposed on the same layer above the substrate.

5. The display device according to claim 3, characterized in that, It also includes power wiring located around the periphery of the dummy pattern. The shielding layer is connected to the power supply wiring.

6. The display device according to claim 5, characterized in that, The power wiring is configured on the inorganic insulation layer. The display device further includes a connection pattern disposed between a conductive layer having the shielding layer and the first semiconductor layer, and connecting the shielding layer and the power wiring.

7. The display device according to claim 6, characterized in that, The connection pattern is disposed on the same layer as the first gate electrode or the second gate electrode.

8. The display device according to claim 6, characterized in that, It also includes a capacitor electrode disposed between a conductive layer on the substrate on which the first gate electrode is disposed and a conductive layer on which the second gate electrode is disposed. The connection pattern is disposed on the same layer as the capacitor electrode.

9. The display device according to claim 1, characterized in that, Also includes: Pixels, a display area located on the substrate, and A driving circuit is located in the non-display area above the substrate and is connected to the pixel; The first transistor and the second transistor are provided in the driving circuit.

10. The display device according to claim 9, characterized in that, The dummy pattern, the dummy hole, and the shielding layer are located around the driving circuit.

11. The display device according to claim 9, characterized in that, The dummy pattern, the dummy hole, and the masking layer are located between the hierarchical circuits provided in the driving circuit.

Images