Display panel and display device
By setting a stepped planarization layer and a pixel definition layer in the OLED display panel, the problem of conductive material residue caused by the step difference between the organic and inorganic layers is solved, thereby improving the reliability and performance of the display panel.
Patent Information
- Application Number
- CN202422980078.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-03
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2034-12-03
AI Technical Summary
During the manufacturing process of OLED display panels, the large difference between the organic and inorganic layers can cause conductive material to remain in the edge areas, resulting in short circuits and affecting the normal operation of the display panel.
By setting a stepped flat layer and a pixel definition layer in the display panel, the organic layer is prevented from stacking at the edge, the step difference between the organic and inorganic layers is reduced, and conductive material residue is avoided.
It effectively reduces the residual conductive material in the corner area between the organic and inorganic layers, prevents short circuits, and improves the reliability and performance of the display panel.
Smart Images
Figure CN223503354U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology
[0002] Organic light-emitting diodes (OLEDs) are a new type of current-driven semiconductor light-emitting device that displays light by controlling the charge carriers in the device and exciting organic materials.
[0003] In the current OLED display panel manufacturing process, because the array layer contains multiple metal layers, multiple organic layers are required to ensure the flatness of the film structure. This results in a large step difference between the organic and inorganic layers at the edge of the display panel. Consequently, in the subsequent conductive layer process, there is residual conductive material in the corner area between the edge of the organic layer and the inorganic layer, which leads to technical problems such as short circuits in the edge area and causes abnormalities in the display panel. Utility Model Content
[0004] This application provides a display panel and display device to improve the technical problem of conductive material residue in the corner area between the edge of the organic layer and the inorganic layer of the existing display panel.
[0005] To address the above issues, the technical solution provided in this application is as follows:
[0006] This application discloses a display panel comprising:
[0007] Substrate;
[0008] A first insulating layer is disposed on one side of the substrate.
[0009] A first planarization layer is disposed on the side of the first insulating layer away from the substrate.
[0010] A second planarization layer is disposed on the side of the first planarization layer away from the substrate, the second planarization layer covers the edge of the first planarization layer and contacts the first insulating layer;
[0011] The first pixel definition layer is disposed on the side of the second flat layer away from the substrate.
[0012] The second pixel definition layer is disposed on the side of the first pixel definition layer away from the substrate.
[0013] Wherein, the edge of the second pixel definition layer is set at least close to the edge of the first flat layer, and the edge of the first pixel definition layer is recessed relative to the edge of the second pixel definition layer.
[0014] Optionally, the display panel further includes a third flat layer disposed between the second flat layer and the first pixel definition layer, the third flat layer covering the edge of the second flat layer and contacting the first insulating layer;
[0015] Wherein, the second pixel definition layer covers the edge of the third flat layer and is in contact with the first insulating layer; or, the edge of the second pixel definition layer is recessed relative to the edge of the first flat layer.
[0016] Optionally, the edge of the second flattening layer includes a first leveling segment, and the edge of the third flattening layer includes a second leveling segment, wherein the leveling length of the first leveling segment is greater than the leveling length of the second leveling segment.
[0017] Optionally, the minimum distance between the end face of the first leveling segment away from the first flattening layer and the end face of the second leveling segment away from the first flattening layer is equal to the leveling length of the first leveling segment.
[0018] Optionally, the minimum distance between the end face of the second leveling segment away from the first leveling layer and the end face of the first insulating layer is less than the leveling length of the first leveling segment.
[0019] Optionally, when the edge of the second pixel definition layer is recessed relative to the edge of the first flat layer, the minimum distance between the end face of the second pixel definition layer and the end face of the first leveling segment near the first flat layer is less than the leveling length of the first leveling segment.
[0020] Optionally, the minimum distance between the end face of the second pixel definition layer and the end face of the first leveling segment near the first flattening layer, and the leveling length of the first leveling segment are both greater than or equal to 10 μm.
[0021] Optionally, the thickness of the third flattening layer is less than the thickness of the second flattening layer.
[0022] Optionally, the thickness of the first pixel definition layer is less than the thickness of the second pixel definition layer.
[0023] This application also proposes a display device, which includes the above-described display panel.
[0024] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.
[0027] Figure 1 A simplified structural diagram of the display panel provided in the embodiments of this application;
[0028] Figure 2 A film layer diagram of a display panel provided in an embodiment of this application;
[0029] Figure 3 for Figure 1 The first cross-sectional view of a portion of the membrane layer in the mid-section MM;
[0030] Figure 4 for Figure 1 A second cross-sectional view of a portion of the membrane layer in the mid-section MM. Detailed Implementation
[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.
[0032] Please see Figures 1 to 4 This application proposes a display panel, which includes a substrate, a first insulating layer, a first planarization layer, a second planarization layer, a first pixel definition layer, and a second pixel definition layer. The first insulating layer is disposed on one side of the substrate, the first planarization layer is disposed on the side of the first insulating layer away from the substrate, the second planarization layer is disposed on the side of the first planarization layer away from the substrate, the first pixel definition layer is disposed on the side of the second planarization layer away from the substrate, and the second pixel definition layer is disposed on the side of the first pixel definition layer away from the substrate.
[0033] In this embodiment, the second flattening layer covers the edge of the first flattening layer and contacts the first insulating layer, the edge of the second pixel definition layer is disposed at least close to the edge of the first flattening layer, and the edge of the first pixel definition layer is recessed relative to the edge of the second pixel definition layer.
[0034] This application avoids the first and second flattening layers from stacking at the edges by setting the edges of the first flattening layer and the second flattening layer in a stepped manner. At the same time, the edge of the first pixel definition layer is recessed relative to the edge of the second pixel definition layer, so that the edge of the first pixel definition layer does not extend to the edge of the display panel. This further avoids the stacking of organic layers of the display panel at the edges, reduces the stacking height of organic layers at the edges, reduces the step difference between organic and inorganic layers at the edges of the display panel, and avoids the residue of conductive material in the corner area between the edge of the organic layer and the inorganic layer.
[0035] The technical solution of this application will now be described in conjunction with specific embodiments.
[0036] Please see Figure 1 The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains a plurality of sub-pixels PX that implement its display functions. The non-display area NA may be a border area of the display panel 100, and it may contain functional components that assist the sub-pixels PX within the display area AA in displaying information.
[0037] Please see Figure 1 A bonding terminal is provided on the lower side of the display area AA. The bonding terminal can be connected to an external circuit and transmits the signals input from the external circuit to the data traces, thereby driving the display panel 100 to display the image. For example, the bonding terminal can be bonded to a chip or a flip-chip film to provide power and drive signals to the display panel 100.
[0038] Please see Figure 2 The display panel 100 may include a substrate 10, an array layer 20 disposed on the substrate 10, a pixel layer 30 disposed on the array layer 20, a light-emitting functional layer 40 and an encapsulation layer 50, a color filter layer 60 disposed on the encapsulation layer 50, and a cover plate layer 70 disposed on the color filter layer 60.
[0039] In this embodiment, the substrate 10 can be made of materials such as glass, quartz, or polyimide; for example, when the display panel 100 is a flexible panel, the substrate 10 can be made of flexible materials such as polyimide, or can be composed of a laminate of flexible materials and inorganic materials; when the display panel 100 is a rigid panel, the substrate 10 can be made of rigid materials such as glass or quartz.
[0040] In this embodiment, please refer to Figure 2The array layer 20 may include multiple thin-film transistors, which may be etch-block type, back-channel etch type, or classified as bottom-gate thin-film transistors, top-gate thin-film transistors, etc., depending on the position of the gate and the active layer 201; there are no specific limitations. For example, Figure 2 The thin-film transistor shown is a top-gate thin-film transistor. This thin-film transistor may include an active layer 201 disposed on the substrate 10, a first gate insulating layer 202 disposed on the active layer 201, a first gate layer GE1 disposed on the first gate insulating layer 202, a second gate insulating layer 203 disposed on the first gate layer GE1, a second gate layer GE2 disposed on the second gate insulating layer 203, a first inter-insulating layer 204 disposed on the second gate layer GE2, a second inter-insulating layer 205 disposed on the first inter-insulating layer 204, a first source-drain layer SD1 disposed on the second inter-insulating layer 205, a second insulating layer IL2 disposed on the first source-drain layer SD1, a first planarization layer 206 disposed on the second insulating layer IL2, a second source-drain layer SD2 disposed on the first planarization layer 206, a second planarization layer 207 disposed on the second source-drain layer SD2, and a third planarization layer 208 disposed on the second planarization layer 207.
[0041] It should be noted that the number of source and drain layers can be set according to the wiring space requirements. For example, the source and drain layers in this application can be two layers. At the same time, the number of gate layers can be set according to the wiring space and capacitance requirements. For example, the gate layers in this application can be two layers.
[0042] It should be noted that the first insulating layer IL1 of this application can be at least one of the first gate insulating layer 202, the second gate insulating layer 203, the first interlayer insulating layer 204, and the second interlayer insulating layer 205, and the first gate insulating layer 202, the second gate insulating layer 203, the first interlayer insulating layer 204, and the second interlayer insulating layer 205 are all inorganic materials composed of elements such as nitrogen, nitric acid, oxygen, and aluminum.
[0043] It should be noted that the leveling layer in this application is set to ensure the flatness of the film layer. The number of leveling layers is set according to the flatness requirements. For example, the leveling layer in this application can be three leveling layers.
[0044] Please see Figure 2 The pixel layer 30 may include a first pixel definition layer 310 and a second pixel definition layer 320. The first pixel definition layer 310 is disposed on the side of the first insulating layer IL1 away from the substrate 10, and the second pixel definition layer 320 is disposed on the surface of the first pixel definition layer 310 away from the substrate 10.
[0045] It should be noted that, since the light-emitting layer 402 of this application is prepared using inkjet printing technology, in order to reduce the precision of inkjet printing, the first pixel definition layer 310 of this application may include a plurality of horizontally and vertically intersecting first pixel dams 311. The horizontally and vertically intersecting first pixel dams 311 enclose a plurality of pixel openings corresponding to sub-pixels. The second pixel definition layer 320 includes a plurality of horizontally or vertically intersecting second pixel dams 321. The multiple sub-pixels between two adjacent second pixel dams 321 have the same color, so that in the inkjet printing process, multiple sub-pixels between two adjacent second pixel dams 321 can be printed simultaneously along the direction of the second pixel dams 321, thereby reducing the precision of inkjet printing and improving process efficiency.
[0046] In this embodiment, since the second pixel dam 321 mainly serves to isolate sub-pixels of different colors, the thickness of the second pixel dam 321 in this application can be greater than the thickness of the first pixel dam 311.
[0047] It should be noted that the materials of the first flattening layer 206, the second flattening layer 207, the third flattening layer 208, the first pixel definition layer 310, and the second pixel definition layer 320 can all be positive organic materials.
[0048] Please see Figure 2 and Figure 3 The light-emitting functional layer 40 may include an anode layer 401 disposed on the third planarization layer 208, a light-emitting layer 402 disposed on the anode layer 401, and a cathode layer 403 disposed on the light-emitting layer 402. The anode layer 401 includes a plurality of anodes corresponding one-to-one with the pixel openings, and the light-emitting layer 402 may include a plurality of light-emitting pixels corresponding one-to-one with the plurality of anodes.
[0049] Please see Figure 2 The encapsulation layer 50 covers the pixel layer 30 and continuously covers multiple pixel openings and multiple light-emitting pixels; the encapsulation layer 50 may include a first inorganic encapsulation layer 501, an organic encapsulation layer 502, and a second inorganic encapsulation layer 503, which may be stacked sequentially.
[0050] In this embodiment, the first inorganic encapsulation layer 501 and / or the second inorganic encapsulation layer 503 extend from the display area AA to the non-display area NA, and the first inorganic encapsulation layer 501 and / or the second inorganic encapsulation layer 503 overlap the barrier structure, and the organic encapsulation layer 502 extends to the non-display area NA and terminates at the barrier structure.
[0051] Please see Figure 2The color filter layer 60 includes a plurality of color resists 610 and light-blocking units 620 disposed on both sides of the color resists 610, and one color resist 610 corresponds to one light-emitting pixel.
[0052] Please see Figure 2 The cover plate layer 70 is disposed on the side of the color filter layer 60 away from the substrate 10. The cover plate layer 70 can be a glass cover plate or formed directly on the color filter layer 60.
[0053] It should be noted that the display panel 100 of this application may also include a touch layer (not shown), and the touch layer may be positioned between the encapsulation layer 50 and the cover layer 70.
[0054] In this embodiment, because the display area of the display panel 100 is provided with multiple conductive patterns, the flatness of the film layer structure in the array layer 20 is low. In order to ensure the flatness of the film layer in the display panel 100, organic materials are usually formed on the conductive patterns or inorganic materials, such as the first flattening layer 206, the second flattening layer 207 and the third flattening layer 208 in this application. The stacking of the first flattening layer 206, the second flattening layer 207 and the third flattening layer 208 at the edge of the display panel 100 results in a large step difference between the edge of the organic layer and the bottom inorganic layer. This causes the conductive material located in the corner area between the organic layer and the inorganic layer to be unable to be removed in the subsequent etching process of the conductive layer, resulting in a technical problem of short circuit in the edge area, which leads to abnormality of the display panel 100.
[0055] Please see Figure 3 and Figure 4 The third planarization layer 208 is disposed between the second planarization layer 207 and the first pixel definition layer 310, and the third planarization layer 208 covers the edge of the second planarization layer 207 and contacts the first insulating layer IL1. That is, the first planarization layer 206, the second planarization layer 207 and the third planarization layer 208 of this application have a stepped structure at the edge of the display panel 100, with the upper film layer covering the edge of the lower film layer and contacting the first insulating layer IL1. The step difference between the first planarization layer 206, the second planarization layer 207 and the third planarization layer 208 at the edge of the display panel 100 and the first insulating layer IL1 is reduced from the sum of the thicknesses of the original first planarization layer 206, the second planarization layer 207 and the third planarization layer 208 to the thickness of the third planarization layer 208, thus avoiding the residue of conductive material in the corner area between the edge of the organic layer and the inorganic layer.
[0056] Since the thickness of the first pixel definition layer 310 is less than the thickness of the second pixel definition layer 320, and the adhesion between the thinner organic material and the underlying inorganic material is smaller when the organic material extends to the edge of the display panel 100, the technical problem of film separation is likely to occur. Therefore, the first pixel definition layer 310 of this application does not need to extend to the edge of the display panel 100, and the stacking thickness of the organic material at the edge can also be reduced.
[0057] Please see Figure 3 Since the first pixel definition layer 310 does not extend to the edge of the display panel 100, the second pixel definition layer 320 can cover the edge of the third flattening layer 208 and contact the first insulating layer IL1. That is, the first flattening layer 206, the second flattening layer 207, the third flattening layer 208 and the second pixel definition layer 320 are arranged in a stepped manner at the edge of the display panel 100. At the same time, the third flattening layer 208 of this application is used to ensure the flatness of the film layer, while the second pixel definition layer 320 is mainly used to form pixel dams. Therefore, the thickness of the third flattening layer 208 of this application is greater than the thickness of the second pixel definition layer 320. At the edge of the display panel 100, the second pixel definition layer 320 with a smaller thickness is used as the edge of the organic layer, which further reduces the step difference between the stacked organic material and the first insulating layer IL1 and avoids the residue of conductive material in the corner area between the edge of the organic layer and the inorganic layer.
[0058] Please see Figure 3 The edge of the second flattening layer 207 includes a first leveling segment 207a, and the edge of the third flattening layer 208 includes a second leveling segment 208a. The leveling length L1 of the first leveling segment 207a is greater than the leveling length L4 of the second leveling segment 208a.
[0059] In this embodiment, when the second planarization layer 207 covers the first planarization layer 206, the second planarization layer 207 includes a first leveling section 207a that contacts the first insulating layer IL1; when the third planarization layer 208 covers the second planarization layer 207, the third planarization layer 208 includes a second leveling section 208a that contacts the first insulating layer IL1; for example Figure 3 In the structure, the first leveling section 207a is the part of the edge of the second leveling layer 207 that contacts the first insulating layer IL1 and has a constant thickness, and the second leveling section 208a is the part of the edge of the third leveling layer 208 that contacts the first insulating layer IL1 and has a constant thickness.
[0060] In this embodiment, since the third flattening layer 208 is disposed on the second flattening layer 207, and the third flattening layer 208 is disposed to further adjust the flatness of the film layer, the thickness of the third flattening layer 208 in this application can be less than the thickness of the second flattening layer 207 and the first flattening layer 206.
[0061] In this embodiment, since the thickness of the third flattening layer 208 is less than the thickness of the second flattening layer 207, the second flattening layer 207 needs a longer leveling length. That is, the leveling length L1 of the first leveling segment 207a in this application is greater than the leveling length L4 of the second leveling segment 208a.
[0062] In this embodiment, the minimum distance L2 between the end face of the first leveling segment 207a away from the first flattening layer 206 and the end face of the second leveling segment 208a away from the first flattening layer 206 can be equal to the leveling length L1 of the first leveling segment 207a. For example, the leveling length L1 of the first leveling segment 207a can be greater than or equal to 10 μm.
[0063] In this embodiment, the minimum distance L3 between the end face of the second leveling segment 208a away from the first flattening layer 206 and the end face of the first insulating layer IL1 is less than the leveling length L1 of the first leveling segment 207a. For example, the minimum distance L3 between the end face of the second leveling segment 208a away from the first flattening layer 206 and the end face of the first insulating layer IL1 can be greater than or equal to 8 μm.
[0064] Please see Figure 4 , Figure 4 The structure and Figure 3 The structures are the same or similar, except that the edge of the second pixel definition layer 320 is recessed relative to the edge of the first flat layer 206.
[0065] In this embodiment, the film thickness of the second pixel definition layer 320 is relatively small, that is, the adhesion between the second pixel definition layer 320 and the first insulating layer IL1 is relatively small. Therefore, when the second pixel definition layer 320 comes into contact with the first insulating layer IL1, the technical problem of film peeling is likely to occur at the edge of the second pixel definition layer 320. Therefore, this application can make the edge of the second pixel definition layer 320 recessed relative to the edge of the first planarization layer 206, that is, the edge of the second pixel definition layer 320 overlaps the surface of the third planarization layer 208, and the organic material in the edge area of the display panel 100 is the third planarization layer 208 with a larger thickness.
[0066] In this embodiment, the minimum distance L5 between the end face of the second pixel definition layer 320 and the end face of the first leveling segment 207a near the first flattening layer 206 is less than the leveling length L1 of the first leveling segment 207a; for example, the minimum distance L5 between the end face of the second pixel definition layer 320 and the end face of the first leveling segment 207a near the first flattening layer 206 can be greater than or equal to 10μm.
[0067] It should be noted that this application also proposes a display device, which includes the aforementioned display panel, and the display device of this application can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.
[0068] This application provides a display panel and a display device. The display panel includes a substrate and a first insulating layer, a first planarization layer, a second planarization layer, a first pixel definition layer, and a second pixel definition layer disposed on one side of the substrate. The second planarization layer covers the edge of the first planarization layer and contacts the first insulating layer. The edge of the second pixel definition layer is disposed at least close to the edge of the first planarization layer, and the edge of the first pixel definition layer is recessed relative to the edge of the second pixel definition layer. By making the edges of the first and second planarization layers stepped, and the edge of the first pixel definition layer recessed relative to the edge of the second pixel definition layer, this application avoids the stacking of organic layers at the edges of the display panel, reduces the stacking height of organic layers at the edges, reduces the step difference between organic and inorganic layers at the edges of the display panel, and avoids the residue of conductive material in the corner area between the edges of organic and inorganic layers.
[0069] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0070] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0071] In the above embodiments, the structures shown in the accompanying drawings are only schematic diagrams, and the specific structure of the display panel of this application is based on the description in the specification.
[0072] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0073] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A display panel, characterized in that, include: Substrate; A first insulating layer is disposed on one side of the substrate. A first planarization layer is disposed on the side of the first insulating layer away from the substrate. A second planarization layer is disposed on the side of the first planarization layer away from the substrate, the second planarization layer covers the edge of the first planarization layer and contacts the first insulating layer; The first pixel definition layer is disposed on the side of the second flat layer away from the substrate. The second pixel definition layer is disposed on the side of the first pixel definition layer away from the substrate. Wherein, the edge of the second pixel definition layer is set at least close to the edge of the first flat layer, and the edge of the first pixel definition layer is recessed relative to the edge of the second pixel definition layer.
2. The display panel according to claim 1, characterized in that, The display panel further includes a third flat layer disposed between the second flat layer and the first pixel definition layer, the third flat layer covering the edge of the second flat layer and contacting the first insulating layer; Wherein, the second pixel definition layer covers the edge of the third flat layer and is in contact with the first insulating layer; or, the edge of the second pixel definition layer is recessed relative to the edge of the first flat layer.
3. The display panel according to claim 2, characterized in that, The edge of the second flattening layer includes a first leveling segment, and the edge of the third flattening layer includes a second leveling segment, wherein the leveling length of the first leveling segment is greater than the leveling length of the second leveling segment.
4. The display panel according to claim 3, characterized in that, The minimum distance between the end face of the first leveling segment away from the first flattening layer and the end face of the second leveling segment away from the first flattening layer is equal to the leveling length of the first leveling segment.
5. The display panel according to claim 3, characterized in that, The minimum distance between the end face of the second leveling segment away from the end face of the first leveling layer and the end face of the first insulating layer is less than the leveling length of the first leveling segment.
6. The display panel according to claim 3, characterized in that, When the edge of the second pixel definition layer is recessed relative to the edge of the first flat layer, the minimum distance between the end face of the second pixel definition layer and the end face of the first leveling segment near the first flat layer is less than the leveling length of the first leveling segment.
7. The display panel according to claim 6, characterized in that, The minimum distance between the end face of the second pixel definition layer and the end face of the first leveling segment near the first flat layer, and the leveling length of the first leveling segment are both greater than or equal to 10 μm.
8. The display panel according to claim 3, characterized in that, The thickness of the third flattening layer is less than the thickness of the second flattening layer.
9. The display panel according to any one of claims 1 to 8, characterized in that, The thickness of the first pixel definition layer is less than the thickness of the second pixel definition layer.
10. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1 to 9.