Linear array camera dead pixel correction device based on FPGA
By using an FPGA-based linear array camera defect correction device, efficient detection and accurate correction of defects in linear array image detectors are achieved, solving the problems of complex operation and insufficient accuracy in existing technologies, and maintaining good correction effect, especially in high-temperature environments.
Patent Information
- Application Number
- CN202422949029.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2025-11-14
- Estimated Expiration
- 2034-12-02
AI Technical Summary
In existing technologies, the defect correction operation of linear array image detectors is complex and not precise enough. In particular, new defective pixels may appear under long-term aging environments such as high temperature. Moreover, the defective pixel location table provided by the manufacturer is not accurate enough, resulting in low detection and correction efficiency.
A dead pixel correction device for a linear array camera based on FPGA is adopted, including an FPGA chip, an A/D data conversion chip, a storage chip, a coaxial cable connector, and a coaxial cable driver chip. The FPGA chip is used for signal acquisition control, digital signal correction, and storage of dead pixel location information to realize the detection, marking, and correction of dead pixels on the linear array image detector.
It simplifies the defect detection and correction process, improves the accuracy and efficiency of detection, reduces the consumption of manpower and material resources, and can effectively correct newly added defective pixels in high-temperature environments.
Smart Images
Figure CN223553399U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of image data processing technology, and in particular to a dead pixel correction device for a linear array camera based on FPGA. Background Technology
[0002] Due to factors such as defects in semiconductor manufacturing processes and material variations, the photoelectric properties of target surface pixels in linear image detectors are inconsistent, resulting in a non-uniformity problem in detector response. Pixels with poor photoelectric properties become dead pixels, which, in many typical applications, can lead to a high probability of missed detections and false detections in the detection of small targets.
[0003] Common image defects can be categorized as follows: hot pixels: pixels that maintain a consistently high pixel value and appear as bright spots in the image; dead pixels: pixels that maintain a consistently low pixel value and appear as dark spots in the image; and noise pixels: pixels whose signal intensity changes with illumination in a way that does not conform to normal patterns, such as random pixel jumps and alternating bright and dark areas in the image.
[0004] Defective Pixel Correction (DPC) is a key technology for solving pixel defects in detectors. In actual manufacturing, defective pixels are often calibrated and corrected based on the dead pixel location table provided by the sensor manufacturer. However, this approach has the following drawbacks: (1) The calibration method is very complicated and consumes a lot of manpower and resources. (2) Under long-term aging environments such as high temperature, new sporadic defective pixels may appear. (3) The dead pixel location table provided by the manufacturer may not be accurate and can only be used as a reference in large-scale use. Therefore, a defective pixel correction device for linear scan cameras based on FPGA is proposed. Utility Model Content
[0005] To address the technical problems existing in the prior art, this utility model provides a dead pixel correction device for a linear array camera based on FPGA.
[0006] This utility model is achieved using the following technical solution: a FPGA-based linear array camera defect correction device, comprising a PCB substrate, wherein the PCB substrate carries an FPGA chip for defect correction of the linear array camera, the FPGA chip is connected to a linear array image detector, an A / D data conversion chip, a storage chip, a coaxial cable connector and a coaxial cable driver chip, and the A / D data conversion chip, the storage chip, the coaxial cable connector and the coaxial cable driver chip are all disposed on the PCB substrate.
[0007] As a further improvement to the above solution, the FPGA chip is used to send signals to the linear image detector to acquire control information, receive and correct the digital electrical signals converted by the A / D data conversion chip, send the bad pixel location information of the linear image detector to the storage chip, and send control information and bad pixel corrected image data to the coaxial cable driver chip, and realize command interaction with the host computer. The FPGA chip model is Anlu EG4X20BG256.
[0008] As a further improvement to the above solution, the memory chip is used to store the bad pixel location information of the linear array image detector. The memory chip is a non-volatile memory chip, model M25P16.
[0009] As a further improvement to the above solution, the coaxial cable connector is connected to a coaxial cable that is connected to the downstream actuator, and the coaxial cable driver chip is model TDA6509HN.
[0010] As a further improvement to the above scheme, the linear array image detector is used to convert the collected radiation energy into analog electrical signals, and the model of the linear array image detector is GD_NIR512L.
[0011] As a further improvement to the above solution, the A / D data conversion chip is used to convert the analog electrical signal converted by the linear image detector into a digital electrical signal. The model of the A / D data conversion chip is AD9826.
[0012] Compared with the prior art, the beneficial effects of this utility model are as follows:
[0013] This invention enables the conversion and correction of acquired analog electrical signals, reducing the operational complexity of bad pixel detection and marking, and simplifying the detection, marking, and correction of bad pixels. Attached Figure Description
[0014] Figure 1 A schematic diagram of the structure of a dead pixel correction device for a linear array camera based on FPGA provided by this utility model;
[0015] Figure 2 A flowchart of FPGA chip calibration in Embodiment 2 provided by this utility model;
[0016] Figure 3 This is a schematic diagram of the pixel difference calculated for the characteristics of the second row of the linear array image detector in Embodiment 2 of this utility model. Detailed Implementation
[0017] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.
[0018] Example 1:
[0019] Please combine Figure 1 This embodiment of an FPGA-based dead pixel correction device for a line scan camera includes a PCB substrate. The PCB substrate carries an FPGA chip for dead pixel correction of the line scan camera. The FPGA chip is connected to a line scan image detector, an A / D data conversion chip, a storage chip, a coaxial cable connector, and a coaxial cable driver chip. The A / D data conversion chip, the storage chip, the coaxial cable connector, and the coaxial cable driver chip are all disposed on the PCB substrate.
[0020] The FPGA chip is used to send signals to the linear image detector to acquire control information, receive and correct the digital electrical signals converted by the A / D data conversion chip, send the bad pixel location information of the linear image detector to the storage chip, and send control information and bad pixel corrected image data to the coaxial cable driver chip. It also realizes command interaction with the host computer. The FPGA chip model is Anlu EG4X20BG256.
[0021] The memory chip is used to store the location information of bad pixels in the linear image detector. The memory chip is a non-volatile memory chip, model M25P16.
[0022] The coaxial cable connector is connected to a coaxial cable that connects to the downstream actuator. The coaxial cable driver chip is model MAX9273.
[0023] The linear array image detector is used to convert the collected radiation energy into analog electrical signals. The model of the linear array image detector is GD_NIR512L.
[0024] The A / D data conversion chip is used to convert the analog electrical signal converted by the linear image detector into a digital electrical signal. The model of the A / D data conversion chip is AD9826.
[0025] The implementation principle of the FPGA-based dead pixel correction device for a linear array camera in this application embodiment is as follows: the linear array image detector converts the collected radiation energy into an analog electrical signal and inputs it into an A / D data conversion chip under the timing provided by the FPGA chip. The A / D data conversion chip converts the analog electrical signal into a digital electrical signal and transmits it to the FPGA chip under the timing provided by the FPGA chip. Subsequently, the FPGA chip performs dead pixel correction, dark level correction, and non-uniformity correction on the digital electrical signal and transmits it to the coaxial cable driver chip. The driver controls the coaxial cable to transmit the corrected digital electrical signal to the host computer and subsequent devices, and realizes command interaction with the host computer. At the same time, the FPGA chip stores the detected dead pixel location information on the storage chip for easy data retrieval in subsequent corrections.
[0026] Example 2:
[0027] like Figure 2 As shown, the FPGA chip performs correction processing on digital electrical signals by means of bad pixel location detection, bad pixel location marking and storage, and bad pixel cell correction;
[0028] Defect location detection:
[0029] The FPGA chip determines whether a pixel is a dead pixel based on its pixel value under different light field intensities. The specific steps are as follows:
[0030] Step S1: Set the dark light field environment, and the host computer sends the command for bad pixel location detection and the judgment threshold for bad pixel location detection through the coaxial cable;
[0031] Step S2: Utilizing the characteristics of the two rows of the linear image detector, construct a 3*2 neighborhood and calculate the pixel difference between the corresponding center pixel and surrounding pixels in the two rows, such as... Figure 3 As shown;
[0032] Step S3: For a pixel, determine whether the absolute value of the difference between it and the 5 surrounding pixels all exceed the bad pixel location detection threshold issued by the host computer; if they all exceed the threshold, then the pixel is determined to be a bad pixel and its location address is marked.
[0033] Step S4: Adjust the light field intensity to half-saturation and critical saturation, and repeat steps S1 to S3 above to obtain the final blind cell table of bad pixel location address information.
[0034] Accessing the location marker for bad pixels:
[0035] The FPGA chip uses the following steps to create a blind cell table for bad pixel location information:
[0036] Step S11: To avoid multiple detections, after the bad pixel location detection is completed, the FPGA chip will write the bad pixel location information blind table into the memory chip.
[0037] Step S12: After each completion of bad pixel location recording and storage or after each power-on of the device, read the blind table of bad pixel location information from the storage chip and provide it to the FPGA chip for accurate correction.
[0038] Dead pixel correction:
[0039] The following steps are performed to eliminate imaging anomalies caused by bad pixels using an FPGA chip:
[0040] Step S21: The FPGA chip reads the loaded bad pixel location information blind pixel table and accurately locates and matches the bad pixel pixels in the original image in the input image data stream;
[0041] Step S22: No operation is performed on unmarked normal pixels. For bad pixels marked in the blind pixel table, correction is performed using normal pixel data at the same position but different rows. The generated correction data is output to the subsequent image processing module and finally uploaded to the host computer via coaxial cable.
[0042] This invention enables the conversion and correction of acquired analog electrical signals, reducing the operational complexity of bad pixel detection and marking, and simplifying the detection, marking, and correction of bad pixels.
[0043] The above embodiments are merely preferred embodiments of this utility model and should not be construed as limiting the scope of protection of this utility model. Any non-substantial changes and substitutions made by those skilled in the art based on this utility model shall fall within the scope of protection claimed by this utility model.
Claims
1. A dead pixel correction device for a linear scan camera based on FPGA, characterized in that, The device includes a PCB substrate, on which an FPGA chip for dead pixel correction of a line scan camera is mounted. The FPGA chip is connected to a line scan image detector, an A / D data conversion chip, a memory chip, a coaxial cable connector, and a coaxial cable driver chip. The A / D data conversion chip, the memory chip, the coaxial cable connector, and the coaxial cable driver chip are all mounted on the PCB substrate.
2. The FPGA-based dead pixel correction device for a linear scan camera as described in claim 1, characterized in that, The FPGA chip is used to send signals to the linear image detector to acquire control information, receive and correct the digital electrical signals converted by the A / D data conversion chip, send the bad pixel location information of the linear image detector to the storage chip, and send control information and bad pixel corrected image data to the coaxial cable driver chip, and realize command interaction with the host computer. The FPGA chip model is Anlu EG4X20BG256.
3. The FPGA-based dead pixel correction device for a linear scan camera as described in claim 1, characterized in that, The memory chip is used to store the location information of bad pixels of the linear image detector. The memory chip is a non-volatile memory chip, model M25P16.
4. The FPGA-based dead pixel correction device for a linear scan camera as described in claim 1, characterized in that, The coaxial cable connector is connected to a coaxial cable that is connected to the downstream actuator, and the coaxial cable driver chip is model MAX9273.
5. The FPGA-based dead pixel correction device for a linear array camera as described in claim 1, characterized in that, The linear array image detector is used to convert the collected radiation energy into analog electrical signals. The model of the linear array image detector is GD_NIR512L.
6. The FPGA-based dead pixel correction device for a linear scan camera as described in claim 1, characterized in that, The A / D data conversion chip is used to convert the analog electrical signal converted by the linear image detector into a digital electrical signal. The model of the A / D data conversion chip is AD9826.