Card reading controller system based on power line broadband carrier

Abstract

The utility model provides a meter reading controller system based on power line broadband carrier waves, and relates to the technical field of carrier communication, the meter reading controller system comprises a main control circuit, a carrier wave signal processing module, an RF signal processing module, a communication debugging module and a power supply module, the main control circuit is respectively in communication connection with the carrier wave signal processing module, the RF signal processing module and the communication debugging module; the communication debugging module comprises an RJ45 communication circuit, a USB communication circuit and a UART interface module. The RJ45 interface, the USB interface and the UART interface are provided through the communication debugging module, the technical effect that the meter reading controller can be compatible with different types of terminal devices is achieved, the problem that a traditional meter reading controller only supports a single communication interface is solved, the diversified access requirements on site are met, and the adaptability and flexibility of the meter reading controller are greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of carrier communication, and in particular to a copy controller system based on a power line broadband carrier. BACKGROUND

[0002] With the in-depth promotion of the intelligent construction of the power grid, power line carrier communication (PLC) gradually becomes an important communication means in the smart grid as a technology for data transmission using existing power line networks. The power line carrier communication technology has the characteristics of no additional wiring, wide coverage, flexible application, etc., and is widely used in centralized meter reading, intelligent power management, power distribution automation, fault monitoring and other fields. The copy controller, as a special on-site measurement and control tool for power line carrier communication, gradually becomes an indispensable device in the power industry. It not only can complete communication testing, networking testing and other debugging tasks, but also can realize data monitoring, analysis and device parameter management functions, and is an important tool to ensure the stable operation of the power line carrier communication system.

[0003] The currently disclosed copy controller technology can meet the basic communication testing and data acquisition needs, but generally has the following problems: the existing copy controller usually only supports a single communication interface, such as a power line carrier communication interface or a limited wireless communication interface, lacks compatibility of multiple interface methods, and the copy controller is usually matched with a single type of terminal device, which cannot adapt to the access needs of different terminal devices. Therefore, in order to meet the diversification needs of the power line communication site, a copy controller system with multiple communication interfaces is needed. CONTENT OF THE UTILITY MODEL

[0004] In order to meet the diversification needs of the power line communication site, the present application provides a copy controller system based on a power line broadband carrier.

[0005] The present application provides a copy controller system based on a power line broadband carrier, which adopts the following technical solutions:

[0006] A copy controller system based on a power line broadband carrier, comprising: a main control circuit, a carrier signal processing module, an RF signal processing module, a communication debugging module and a power supply module, the input end of the main control circuit is respectively in communication connection with the output end of the carrier signal processing module, the output end of the RF signal processing module and the output end of the communication debugging module, the output end of the main control circuit is respectively in communication connection with the input end of the RF signal processing module and the input end of the communication debugging module, and the power supply module is respectively in electrical connection with the main control circuit, the carrier signal processing module and the communication debugging module;

[0007] The communication debugging module comprises an RJ45 communication circuit, a USB communication circuit and a UART interface module;

[0008] The RJ45 communication circuit comprises an RJ45 interface circuit and a PHY chip circuit, an input end of the PHY chip circuit is in communication connection with an output end of the RJ45 interface circuit and an output end of the master control circuit respectively, and an output end of the PHY chip circuit is in communication connection with an input end of the RJ45 interface circuit and an input end of the master control circuit respectively;

[0009] An output end of the USB communication circuit is in communication connection with an input end of the master control circuit, and an input end of the USB communication circuit is in communication connection with an output end of the master control circuit;

[0010] An output end of the UART interface module is in communication connection with an input end of the master control circuit, and an input end of the UART interface module is in communication connection with an output end of the master control circuit.

[0011] By adopting the technical scheme, the communication debugging module is adopted, the RJ45, USB and UART three communication interface modes are integrated, the interface compatibility of the copy controller is improved, the access requirements of various terminal devices can be adapted, and the technical limitation that the existing copy controller only supports a single interface is effectively solved. Meanwhile, the master control circuit is adopted to uniformly coordinate and manage the RJ45, USB and UART communication interfaces, the integration and efficient cooperation of various interfaces are realized, diversified data access, transmission and processing are supported. In addition, the carrier signal processing module and the RF signal processing module are adopted, the support for power line communication and wireless communication is realized respectively, the communication requirements of the copy controller in various complex scenes are met, and the adaptability and practicality of the system are further enhanced.

[0012] Optionally, the RJ45 interface circuit comprises an RJ45 socket.

[0013] An output end of the RJ45 socket is in communication connection with an input end of the PHY chip circuit, and an input end of the RJ45 socket is in communication connection with an output end of the PHY chip circuit.

[0014] The PHY chip circuit comprises a first crystal oscillator and a PHY chip.

[0015] An input end of the PHY chip is in communication connection with an output end of the RJ45 socket, an output end of the PHY chip is in communication connection with an input end of the RJ45 socket, and the output end and the input end of the PHY chip are both connected with the first crystal oscillator.

[0016] By adopting the above technical scheme, the RJ45 interface circuit is introduced into the RJ45 socket to support the standard Ethernet interface form, has wide compatibility, can meet the access requirements of various terminal devices, and further expands the application range of the copy controller. Moreover, in the conversion process of the digital signal and the analog signal, the first crystal oscillator and the PHY chip are used in cooperation to provide a stable clock signal, ensuring the synchronization and accuracy of the data in the communication process, effectively avoiding data loss and transmission delay. Moreover, the RJ45 interface circuit and the PHY chip circuit are designed in layers, which makes the system have modular characteristics under the condition of ensuring that the system can stably operate in various network environments, facilitating the subsequent maintenance and function expansion of the copy controller.

[0017] Optionally, the USB communication circuit comprises a USB chip and a second crystal oscillator.

[0018] The input end of the USB chip is connected with the output end of the main control module, the output end of the USB chip is connected with the input end of the main control circuit, and the input end and the output end of the USB chip are both connected with the second crystal oscillator.

[0019] By adopting the above technical scheme, the input end and the output end of the USB chip are both connected with the second crystal oscillator, a stable clock signal source is provided, and the data synchronization and transmission reliability in the USB communication process are ensured. In addition, by using the USB chip to adopt a standard USB communication protocol, wide compatibility is achieved, various types of terminal devices can be connected, including computers, debugging devices and external sensors, and the application scenarios of the copy controller are further expanded.

[0020] Optionally, the copy controller system further comprises a bidirectional zero-crossing detection module.

[0021] The output end of the zero-crossing detection module is in communication connection with the input end of the main control circuit, and the zero-crossing detection module is electrically connected with the power module.

[0022] By adopting the above technical scheme, the zero-crossing point of the power line signal can be detected in real time, so that the transmission of the communication signal in the power line matches the power waveform, thereby avoiding the interference of the fluctuation of the power voltage on the carrier signal. Moreover, by accurately detecting the zero-crossing point, the system can transmit data at the best opportunity of the power line carrier signal, improving the communication quality and stability. By detecting the zero-crossing point of the power signal, the transmission opportunity of the signal can be adjusted in time, avoiding the phase conflict between the power line signal and the power, reducing the noise and fluctuation generated by the interference of the power line carrier and the power signal, and improving the clarity and transmission quality of the signal.

[0023] Optionally, the bidirectional zero-crossing detection module comprises a positive half-cycle zero-crossing detection circuit and a negative half-cycle zero-crossing detection circuit.

[0024] The positive half-cycle zero-crossing detection circuit comprises a first zero-crossing detection chip, a first resistor and a first optocoupler, the input end of the first zero-crossing detection chip is electrically connected with the output end of the power module, the output end of the first zero-crossing detection chip is in communication connection with the input end of the first optocoupler through the first resistor, and the output end of the first optocoupler is in communication connection with the input end of the main control circuit;

[0025] The negative half-cycle zero-crossing detection circuit comprises a second zero-crossing detection chip, a second resistor and a second optocoupler, the input end of the second zero-crossing detection chip is electrically connected with the output end of the power module, the output end of the second zero-crossing detection chip is in communication connection with the input end of the second optocoupler through the second resistor, and the output end of the second optocoupler is in communication connection with the input end of the main control circuit.

[0026] By adopting the above technical scheme, the bidirectional zero-crossing detection module can detect the zero-crossing points of the positive and negative half cycles of the power signal at the same time, can more comprehensively monitor the change of the power waveform, can better maintain the synchronism and stability of the system, and can reduce the transmission error caused by the fluctuation of the power waveform. The first resistor is connected between the output end of the zero-crossing detection chip and the input end of the optocoupler, which plays a role of current limiting protection. Since the signal output by the zero-crossing detection chip has a high voltage or current, direct connection to the optocoupler can cause damage or performance degradation of the optocoupler. By connecting the first resistor in series, the current flowing through the optocoupler can be limited, the optocoupler can be protected, and the optocoupler can work normally. Moreover, the bidirectional zero-crossing detection can detect the zero-crossing points of the positive and negative half cycles of the power signal at the same time, and can more comprehensively monitor the change of the power waveform. Moreover, the output end of the optocoupler is in communication connection with the input end of the main control circuit, thereby realizing electrical isolation between the strong and weak electricities, protecting the main control circuit from interference and damage of the strong electricity signal, and improving safety and stability.

[0027] Optionally, the power module comprises a 3V3_DCDC circuit and a DCDC circuit;

[0028] The input end of the 3V3_DCDC circuit is connected to a 12V power supply, and the output end of the 3V3_DCDC circuit is electrically connected with the input end of the main control circuit, the input end of the carrier signal processing module, the input end of the RJ45 communication circuit and the input end of the UART interface module;

[0029] The input end of the DCDC circuit is connected to a 12V power supply, and the output end of the DCDC circuit is electrically connected with the input end of the USB communication circuit.

[0030] By adopting the above technical scheme, the 3V3_DCDC circuit converts the 12V power supply into a 3.3V power supply to provide stable power input for the subsequent circuit. The DCDC circuit performs voltage reduction or voltage increase processing on the 12V power supply to ensure that each module of the system can obtain the required voltage level. Through this combination, the system can flexibly adapt to different voltage requirements to ensure that the copy controller runs stably in various environments.

[0031] Optionally, the data logger system further comprises an indicator light circuit.

[0032] The input end of the indicator light circuit is connected with the output end of the main control circuit.

[0033] By adopting the above technical scheme, the indicator light can reflect the working state of the data logger in real time through the connection with the main control circuit, intuitively feedback the system running state to the user, and reduce the risk of incorrect operation of the user due to lack of real-time information.

[0034] Optionally, the data logger system further comprises a buzzer circuit.

[0035] The input end of the buzzer circuit is connected with the output end of the main control circuit.

[0036] By adopting the above technical scheme, the user can be reminded of the state change or fault condition of the data logger system in time through the sound signal, especially when the vision cannot be directly perceived or the user is far away from the device, the sound reminder of the buzzer can quickly attract attention, helping the operator or maintenance personnel to quickly perceive the abnormal state of the data logger, and enhancing the real-time monitoring capability of the data logger.

[0037] In summary, the present application includes at least one of the following beneficial technical effects:

[0038] 1、The present application integrates three communication interface modes of RJ45, USB and UART through the communication debugging module, improves the interface compatibility of the data logger, can adapt to the access requirements of various terminal devices, and effectively solves the technical limitations that the existing data logger only supports a single interface. At the same time, the present application unifies the coordination and management of the RJ45, USB and UART communication interfaces through the main control circuit, realizes the integration and efficient cooperation of various interfaces, supports diversified data access, transmission and processing. In addition, the carrier signal processing module and the RF signal processing module are adopted to respectively realize the support for power line communication and wireless communication, meet the communication requirements of the data logger in various complex scenes, and further enhance the adaptability and practicality of the system.

[0039] 2、The bidirectional zero-crossing detection module in the application can detect the zero-crossing points of the positive and negative half cycles of the power signal at the same time, can more comprehensively monitor the change of the power waveform, can better maintain the synchronism and stability of the system, and can reduce the transmission error caused by the fluctuation of the power waveform. The first resistor is connected between the output end of the zero-crossing detection chip and the input end of the optocoupler, which plays a current limiting protection role. Since the signal output by the zero-crossing detection chip has a high voltage or current, direct connection to the optocoupler can cause damage to the optocoupler or performance degradation. By connecting the first resistor in series, the current flowing through the optocoupler can be limited, the optocoupler can be protected, and it can work normally. Moreover, the bidirectional zero-crossing detection can detect the zero-crossing points of the positive and negative half cycles of the power signal at the same time, which can more comprehensively monitor the change of the power waveform. Moreover, the output end of the optocoupler is in communication connection with the input end of the main control circuit, realizing electrical isolation between strong and weak electricity, not only protecting the main control circuit from interference and damage of strong electricity signal, but also improving safety and stability. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 It is a signal transmission schematic diagram of the application;

[0041] Figure 2 It is a first part circuit schematic diagram of the main control circuit;

[0042] Figure 3 It is a second part circuit schematic diagram of the main control circuit;

[0043] Figure 4 It is a third part circuit schematic diagram of the main control circuit;

[0044] Figure 5 It is a circuit schematic diagram of the RJ45 interface circuit of the application;

[0045] Figure 6 It is a circuit schematic diagram of the PHY chip circuit of the application;

[0046] Figure 7 It is a circuit schematic diagram of the USB communication circuit of the application;

[0047] Figure 8 It is a circuit schematic diagram of the UART interface module of the application;

[0048] Figure 9 It is a circuit schematic diagram of the RF signal processing circuit of the application;

[0049] Figure 10 It is a circuit schematic diagram of the carrier signal sending circuit of the application;

[0050] Figure 11 It is a circuit schematic diagram of the low-pass filter circuit of the application;

[0051] Figure 12The circuit schematic diagram of the high-pass filter circuit of the present application;

[0052] Figure 13 The circuit schematic diagram of the attenuation circuit of the present application;

[0053] Figure 14 The circuit schematic diagram of the positive half-cycle zero-crossing detection circuit of the present application;

[0054] Figure 15 The circuit schematic diagram of the negative half-cycle zero-crossing detection circuit of the present application;

[0055] Figure 16 The circuit schematic diagram of the DCDC circuit of the present application;

[0056] Figure 17 The circuit schematic diagram of the 3V3_DCDC circuit of the present application;

[0057] Figure 18 The circuit schematic diagram of the indicator lamp circuit of the present application

[0058] Figure 19 The circuit schematic diagram of the buzzer circuit of the present application;

[0059] The reference signs are explained as follows: the first crystal oscillator-X1; the second crystal oscillator-X1001; the first resistor-R65; the second resistor-R106. DETAILED DESCRIPTION

[0060] The following Figures 1 to 15 The present application is further described in detail.

[0061] As Figure 1 shown, the embodiment discloses a copy controller system based on power line broadband carrier, which comprises a master control circuit, a carrier signal processing module, an RF signal processing module, a communication debugging module and a power module, and realizes efficient and stable signal transmission and processing. The composition and connection mode of the embodiment are described as follows:

[0062] The input end of the master control circuit is in communication connection with the output end of the carrier signal processing module, the output end of the RF signal processing module and the output end of the communication debugging module respectively, and the output end of the master control circuit is in communication connection with the input end of the RF signal processing module and the input end of the communication debugging module respectively.

[0063] The master control module can uniformly coordinate and manage the carrier signal processing module, the RF signal processing module and the communication debugging module. Moreover, through the bidirectional communication connection with the carrier signal processing module, the RF signal processing module and the communication debugging module, the master control module can flexibly support various communication interfaces (RJ45, USB, UART, etc.), effectively solves the limitation that the traditional copy controller only supports a single communication mode, and improves the compatibility and adaptability of the equipment.

[0064] The carrier signal processing module includes a carrier signal sending circuit and a carrier signal receiving circuit. The carrier signal sending circuit is responsible for modulating and sending a data signal, completing communication of the master control circuit to the power line. The carrier signal receiving circuit is responsible for extracting and demodulating the data signal, realizing communication of the power line to the master control circuit. Through the carrier signal processing module, the copy controller can simultaneously communicate with multiple terminal devices, realizing efficient management and data acquisition of distributed devices, supporting centralized meter reading, intelligent power consumption management and other complex scenarios.

[0065] The communication debugging module includes an RJ45 communication circuit, a USB communication circuit and a UART interface module. The input end of the RJ45 communication circuit, the USB communication circuit and the UART interface module is in communication connection with the output end of the master control circuit, and the output end of the RJ45 communication circuit, the USB communication circuit and the UART interface module is connected with the communication input end of the master control circuit.

[0066] The RJ45 communication circuit includes an RJ45 interface circuit and a PHY chip circuit. The input end of the PHY chip circuit is in communication connection with the output end of the RJ45 interface circuit and the output end of the master control circuit, and the output end of the PHY chip circuit is in communication connection with the input end of the RJ45 interface circuit and the input end of the master control circuit. The RJ45 interface circuit realizes communication connection with the master control circuit through the PHY chip circuit, integrates the RJ45 communication interface mode, improves the interface compatibility of the copy controller, and can adapt to the access requirements of various terminal devices.

[0067] The output end of the USB communication circuit is in communication connection with the input end of the master control circuit, and the input end of the USB communication circuit is in communication connection with the output end of the master control circuit. The USB communication circuit realizes communication connection with the master control circuit, integrates the USB communication interface mode, improves the interface compatibility of the copy controller, and can adapt to the access requirements of various terminal devices.

[0068] The output end of the UART interface module is in communication connection with the input end of the master control circuit, and the input end of the UART interface module is in communication connection with the output end of the master control circuit. The UART interface module realizes communication connection with the master control circuit, integrates the UART communication interface mode, improves the interface compatibility of the copy controller, and can adapt to the access requirements of various terminal devices.

[0069] The RF signal processing module includes an RF signal processing circuit and an RF antenna. The RF antenna is used for receiving and sending wireless signals, and converting electromagnetic wave signals in the environment into electrical signals transmitted to the RF signal processing circuit. The RF signal processing circuit is responsible for amplifying, filtering, demodulating and other processing of the signals received by the antenna, extracting valid data and transmitting it to the master control circuit; at the same time, modulating and signal converting the data transmitted by the master control circuit to adapt to the transmission requirements of wireless communication.

[0070] The power module is electrically connected with the master control circuit, the carrier signal processing module and the communication debugging module respectively. The power module includes a 3V3_DCDC circuit and a DCDC circuit, and further includes an external mains and an external 12V power supply. The power module provides the required stable power for the copy controller system, and ensures the normal operation of the circuit.

[0071] As shown in Figures 2 to 4 The master control circuit includes a master control chip, and the master control chip adopts D31TV100. The connection mode of the master control circuit is as follows:

[0072] The MDIO pin of the master control chip is connected in communication with the PHY chip, the MDCK pin of the master control chip is connected with the MDC pin of the PHY chip, the ETXD0 pin of the master control chip is connected in signal with the TXD0 pin of the PHY chip circuit, the ETXD1 pin of the master control chip is connected in signal with the TXD1 pin of the PHY chip circuit, the ERXD0 pin of the master control chip is connected in signal with the RXD0 pin of the PHY chip circuit, the ERXD1 pin of the master control chip is connected in signal with the RXD1 pin of the PHY chip circuit, the CRS_DV pin of the master control chip is connected in signal with the CRS / CRS_DV pin of the PHY chip circuit, the ETH_CLK pin of the master control chip is connected in signal with the TXC pin of the PHY chip circuit through the resistor R74, the TH_EN pin of the master control chip is connected in communication with the PHY chip circuit, the TRX_SW pin of the master control chip is connected with the RF signal processing module, the GPIO_15 pin of the master control chip is connected with the indicator light circuit, the GPIO_17 pin of the master control chip is connected with the indicator light circuit, the GPIO_19 pin of the master control chip is connected with the PHY chip circuit, and reset management is realized.The GPIO_20 pin of the master control chip is grounded, the GPIO_21 pin of the master control chip is connected with the indicator light circuit, the UART0_RXD pin of the master control chip is connected with the buzzer circuit, the UART1_RXD pin of the master control chip is connected with the 3.3V power supply through the resistor R18, the UART1_RXD pin of the master control chip is connected with the UART interface module, the UART1_TXD pin of the master control chip is grounded through the resistor R19, the UART1_TXD pin of the master control chip is connected with the UART interface module, the UART2_RXD pin of the master control chip is connected with the BPF_SHORT, the UART2_TXD pin of the master control chip is connected with the ATT_SHORT, the ADC_CH1 pin of the master control chip is connected with the bidirectional zero-crossing detection module, the GPIO_2 pin of the master control chip is connected with the bidirectional zero-crossing detection module, the GPIO_12 pin of the master control chip is grounded, the SPIO_CK pin of the master control chip is grounded, the SPI1_CK pin of the master control chip is connected with the USB communication circuit, the SPI1_CSN pin of the master control chip is connected with the USB communication circuit, the SPI2_CK pin of the master control chip is connected with the USB communication circuit, the SPI2_CSN pin of the master control chip is connected with the USB communication circuit, the SPI2_TXD pin of the master control chip is connected with the USB communication circuit, the SPI2_RXD pin of the master control chip is connected with the USB communication circuit, the I2C0_SCL pin of the master control chip is connected with the USB communication circuit, the I2C0_SDA pin of the master control chip is connected with the indicator light circuit, the RSTN pin of the master control chip is grounded through the capacitor C115, the GPIO_8 pin of the master control chip is connected with the carrier signal sending circuit, the GPIO_8 pin of the master control chip is connected with the 3.3V power supply through the resistor R97, and the GPIO_10 pin of the master control chip is connected with the USB communication circuit.

[0073] The DVDD33_1 pin and the DVDD33_2 pin of the master control chip are grounded through the capacitor C35, the DVDD33_1 pin and the DVDD33_2 pin of the master control chip are grounded through the capacitor C31, the AVDD28_AO pin of the master control chip is grounded through the capacitor C55, the RF_TX pin of the master control chip is connected with the RF signal processing module, the RF_RX pin of the master control chip is connected with the RF signal processing module, the AVDD12_RI pin of the master control chip is grounded through the capacitor C135, the AVDD12_RI pin of the master control chip is grounded through the capacitor C133, the AVDD12_RI pin of the master control chip is connected with the BUCK_1V25 of the master control chip through the inductor LB11, the VDD12_RI pin of the master control chip is grounded through the capacitor C47, the VDD12_RI pin of the master control chip is grounded through the capacitor C46, the VDD12_RI pin of the master control chip is connected with the BUCK_1V25 of the master control chip through the inductor LB1, the AVDD33_PI1 pin and the AVDD33_PI2 pin of the master control chip are grounded through the capacitor C52, the AVDD33_PI1 pin and the AVDD33_PI2 pin of the master control chip are grounded through the capacitor C53, the AVDD33_PI1 pin and the AVDD33_PI2 pin of the master control chip are connected with the DVDD33_RF_PA through the inductor LB2, the AVDD33_RI pin of the master control chip is grounded through the capacitor C130, the AVDD33_RI pin of the master control chip is grounded through the capacitor C129, the AVDD33_RI pin of the master control chip is connected with the DVDD33_RF_PA through the inductor LB10, the VDD11_RO pin of the master control chip is grounded through the capacitor C119, and the VDD11_RO pin of the master control chip is grounded through the capacitor C45.The AVDD28_RO pin of the main control chip is grounded through capacitor C57; the DVDD18_DO pin is grounded through capacitor C29; the PVDD33_BUCK1, PVDD33_BUCK2, and AVDD33_BUCK pins are all grounded through capacitor C30; the PVDD33_BUCK1, PVDD33_BUCK2, and AVDD33_BUCK pins are all grounded through capacitor C36; the BUCK_LX1 and BUCK_LX2 pins are grounded sequentially through inductor L7 and capacitor C64; and the BUCK_LX1 and BUCK_LX2 pins are grounded sequentially through inductor L7 and capacitor C44. The main control chip's VDD_DIG1 and VDD_DIG2 pins are grounded via capacitor C28. The main control chip's TXN pin is connected to the carrier signal transmission circuit via capacitor C83, and the main control chip's TXP pin is connected to the carrier signal transmission circuit via capacitor C86. The main control chip's R_EXT pin is grounded via resistor R79. The main control chip's VREF pin is grounded via capacitor C122 and capacitor C116. The main control chip's RXN pin is connected to the carrier signal receiving circuit, and the main control chip's RXP pin is connected to the carrier signal receiving circuit. The main control chip's AVDD33_2 pin is grounded via capacitor C105 and capacitor C23.

[0074] like Figure 5 As shown, in this embodiment, an RJ45 socket with an LED indicator is used as the physical interface in the RJ45 interface circuit for transmitting network signals, receiving and sending signals. The connection method of the RJ45 interface circuit is as follows:

[0075] The TD+ pin, the TD- pin, the RD+ pin and the RD- pin of the RJ45 socket J501 are in communication connection with the PHY chip circuit, the TCT pin of the RJ45 socket J501 is connected to a 3.3V power supply, the TCT pin of the RJ45 socket J501 is connected to the first end of the capacitor C505, the first end of the capacitor C501 and the first end of the capacitor C502 respectively, the second end of the capacitor C505, the second end of the capacitor C501 and the second end of the capacitor C502 are grounded, the RCT pin of the RJ45 socket J501 is connected to a 3.3V power supply, the RCT pin of the RJ45 socket J501 is connected to the first end of the capacitor C505, the first end of the capacitor C501 and the first end of the capacitor C502 respectively, the positive input end of the indicator lamp L1 in the RJ45 socket J501 is connected to a 3.3V power supply, the negative end of the indicator lamp L1 is connected to the LED1 pin in the PHY chip circuit through the resistor R504, the positive input end of the indicator lamp L2 in the RJ45 socket J501 is connected to a 3.3V power supply, the negative end of the indicator lamp L1 is connected to the LED0 pin in the PHY chip circuit through the resistor R503.

[0076] In the embodiment, the indicator lamp L1 is a connection indicator lamp for indicating the high and low of the network connection speed, and the indicator lamp L2 is a network communication indicator lamp for indicating the network connection and data transmission state.

[0077] As shown in Figure 6 The PHY chip in the PHY chip circuit adopts RTL8201FI, and the connection mode of the PHY chip circuit is as follows:

[0078] The MDIO pin of the PHY chip is connected with the MDIO pin of the master control chip, the MDIO pin of the PHY chip is connected with the first end of the resistor R83, the second end of the resistor R83 is connected with a 3.3V power supply, the second end of the resistor R83 is connected with the first end of the capacitor C4, the first end of the capacitor C37, the first end of the capacitor C31 and the first end of the capacitor C42 respectively, the AVDD33_1 pin of the PHY chip is connected with the first end of the capacitor C37, the AVDD33_2 pin of the PHY chip is connected with the first end of the capacitor C31, the DVDD33 pin of the PHY chip is connected with the first end of the capacitor C42, the second end of the capacitor C4, the second end of the capacitor C37, the second end of the capacitor C31 and the second end of the capacitor C42 are grounded, the AVDD100UT pin of the PHY chip is grounded through the capacitor C54, the DVDD100UT pin of the PHY chip is grounded through the capacitor C56, the MDC pin of the PHY chip is connected with a 3.3V power supply, the CRS / CRS_DV pin of the PHY chip is grounded, the COL pin of the PHY chip is grounded, the TXC pin of the PHY chip is grounded, the TXEN pin of the PHY chip is connected with the TH_EN pin of the master control chip, the TXD0 pin of the PHY chip is grounded, the TXD1 pin of the PHY chip is grounded, the RXD0 pin of the PHY chip is connected with a 3.3V power supply, the RXD1 pin of the PHY chip is connected with a 3.3V power supply, the RXD2 / INTB pin of the PHY chip is connected with a 3.3V power supply through the resistor R138, the RXD3 / CLK_CTL pin of the PHY chip is connected with a 3.3V power supply through the resistor R137, the RXDV pin of the PHY chip is connected with a 3.3V power supply through the resistor R649, the CKXTAL1 pin of the PHY chip is grounded through the capacitor R626, the CKXTAL1 pin of the PHY chip is connected with the first end of the first crystal oscillator X1, the CKXTAL2 pin of the PHY chip is connected with the first end of the resistor R647, the second end of the resistor R647 is connected with the second end of the first crystal oscillator X1 and the first end of the capacitor C39 respectively, the second end of the capacitor C39, the GND1 pin of the first crystal oscillator X1 and the GND2 pin of the first crystal oscillator X1 are grounded, the RSET pin of the PHY chip is grounded through the resistor R16, the E-PAD pin of the PHY chip is grounded, the MDI+0 pin of the PHY chip is connected with the first end of the capacitor C197, the second end of the capacitor C197 is connected with the TD+ pin of the RJ45 socket J501 in the RJ45 interface circuit and the first end of the resistor R650 respectively, the second end of the resistor R650 is connected with the first end of the resistor R645, the second end of the resistor R645 is connected with a 3.3V power supply, the MDI-0 pin of the PHY chip is connected with the first end of the capacitor C196, the second end of the capacitor C196 is connected with the TD-pin of the RJ45 socket J501 in the RJ45 interface circuit and the first end of the resistor R651 respectively, the second end of the resistor R651 is connected with the first end of the resistor R645, the MDI+1 pin of the PHY chip is connected with the first end of the capacitor C195, the second end of the capacitor C195 is connected with the RD+ pin of the RJ45 socket J501 in the RJ45 interface circuit and the first end of the resistor R652 respectively, the second end of the resistor R652 is connected with the 3.3V power supply, the MDI-1 pin of the PHY chip is connected with the first end of the capacitor C194, the second end of the capacitor C194 is connected with the RD-pin of the RJ45 socket J501 in the RJ45 interface circuit and the first end of the resistor R653 respectively, the second end of the resistor R653 is connected with the 3.3V power supply, the LED1 / PHYAD1 pin of the PHY chip is connected with the resistor R504 in the RJ45 interface circuit, the LED1 / PHYAD1 pin of the PHY chip is grounded through the resistor R135, the LED0 / PHYAD0 / PMEB pin of the PHY chip is connected with the 3.3V power supply through the resistor R85, the LED1 / PHYAD1 pin of the PHY chip is connected with the current-limiting resistor R503 in the RJ45 interface circuit, the PHYRSTB pin of the PHY chip is grounded through the capacitor C5, the PHYRSTB pin of the PHY chip is connected with the 3.3V power supply through the resistor R123, and the RXER / FXEN pin of the PHY chip is grounded through the resistor R127.

[0079] In the embodiment, different network terminals (such as PC, server, industrial gateway, etc.) can be accessed through the RJ45 interface circuit, and the PHY chip circuit supports multiple network modes (such as RMII mode, UTP mode, etc.), which can directly access the existing network infrastructure without developing a special protocol.

[0080] As shown in Figure 7 , the USB chip in the USB communication circuit adopts CH376T, and the connection mode of the USB communication circuit is as follows:

[0081] The INT# pin of the USB chip is connected with the GPIO_10 pin of the master control chip through the resistor R1010, the RSTI pin of the USB chip is connected with the I2C0_SCL pin of the master control chip through the resistor R1009, the TXD pin of the USB chip is connected with the SPI1_CK pin of the master control chip through the resistor R1004, the RXD pin of the USB chip is connected with the SPI1_CSN pin of the master control chip through the resistor R1005, the V3 pin of the USB chip is grounded through the capacitor C1010, the VD+ pin of the USB chip is connected with the DP signal line of the USB interface, the VD- pin of the USB chip is connected with the DM signal line of the USB interface, the GND pin of the USB chip is grounded, the VCC pin of the USB chip is grounded through the capacitor C1001, the VCC pin of the USB chip is grounded through the capacitor C1009, the SDO pin of the USB chip is connected with the SPI2_TXD pin of the master control chip, the SDI pin of the USB chip is connected with the SPI2_RXD pin of the master control chip, the SCK pin of the USB chip is connected with the SPI2_CK pin of the master control chip, the SCS pin of the USB chip is connected with the SPI2_CSN pin of the master control chip, the SCS pin of the USB chip is connected with the 3.3V power supply, the XO pin of the USB chip is grounded through the capacitor C1003, the XO pin of the USB chip is connected with the first end of the second crystal oscillator X1001, the XI pin of the USB chip is connected with the second end of the second crystal oscillator X1001, and the GND1 pin and the GND2 pin of the second crystal oscillator X1001 are both grounded.

[0082] In the embodiment, the input end and the output end of the USB chip are both connected with the second crystal oscillator, a stable clock signal source is provided, and the data synchronization and the transmission reliability in the USB communication process are ensured. In addition, by using the USB chip, the standard USB communication protocol is adopted, wide compatibility is achieved, various types of terminal devices can be connected, including computers, debugging devices and external sensors, and the application scenarios of the copy controller are further expanded.

[0083] As shown in Figure 8 , the circuit connection mode of the UART interface module is as follows:

[0084] The A1 end of the interface J4 is connected with the 3.3V power supply, the A2 end of the interface J4 is grounded, the A4 end of the interface J4 is connected with the UART1_TXD pin of the master control chip, the A5 end of the interface J4 is connected with the UART1_RXD pin of the master control chip, and the A2 end of the interface J4 is connected with the A2 end of the interface J4.

[0085] As shown in Figure 9As shown, the RF signal processing module includes RF signal processing circuit and RF antenna, RF signal processing circuit in the radio frequency power amplifier chip U1 uses AW13612FLR, the connection mode of RF signal processing circuit is as follows:

[0086] The RF1 pin of the chip U1 is connected with the first end of the resistor R1832, the second end of the resistor R1832 is connected with the first end of the resistor R1833, the second end of the resistor R1833 is connected with the first end of the capacitor C20, the second end of the capacitor C20 is connected with the first end of the inductor L9 and the first end of the capacitor C48 respectively, the second end of the capacitor C48 is grounded, the second end of the inductor L9 is connected with the RF_RX pin of the main control chip, the GND pin of the chip U1 is grounded, the RF2 pin of the chip U1 is connected with the first end of the inductor L3 and the first end of the capacitor C49 respectively, the second end of the inductor L3 is connected with the first end of the capacitor C50 and the first end of the inductor L2 respectively, the second end of the inductor L2 is connected with the first end of the capacitor C11 and the first end of the resistor R183 respectively, the second end of the capacitor C49, the second end of the capacitor C50 and the second end of the capacitor C11 are grounded, the second end of the resistor R183 is connected with the first end of the inductor L1 and the first end of the capacitor C13 respectively, the second end of the inductor L1 is connected with the RF_TX pin of the main control chip, the second end of the capacitor C13 is grounded, the V1 pin of the chip U1 is connected with the first end of the resistor R701, the second end of the resistor R701 is connected with the TRX_SW pin of the main control chip, the ANT pin of the chip U1 is connected with the first end of the capacitor C7020, the second end of the capacitor C7020 is connected with the test point TP701 and the first end of the resistor R21 respectively, the second end of the resistor R21 is connected with the first end of the capacitor C7, the first end of the diode D1 and the antenna interface J5 respectively, the second end of the diode D1 is connected with the ground interface J3, the second end of the capacitor C7 is grounded, the VDD pin of the chip U1 is grounded through the capacitor C6.

[0087] As shown in the figure, Figures 10 to 13 The carrier signal processing module includes carrier signal sending circuit and carrier signal receiving circuit.

[0088] The carrier signal sending circuit includes carrier signal processing chip U6 and filter circuit, the carrier signal processing chip U6 uses THS6212IRHFR chip, the connection mode of the carrier signal sending circuit is as follows:

[0089] The D1_IN+ pin of the chip U6 is connected with the first end of the resistor R401, the second end of the resistor R401 is connected with the first end of the resistor R68 and the first end of the capacitor C73 respectively, the second end of the resistor R68 is connected with one end of the capacitor C86 away from the TXP pin of the master control chip, the second end of the resistor R68 is connected with the first end of the resistor R2, the second end of the resistor R2 is connected with the first end of the resistor R4, the first end of the resistor R9 and the first end of the resistor R8 respectively, the second end of the resistor R9 is grounded, the second end of the resistor R8 is connected with a 12V power supply, the D2_IN+ pin of the chip U6 is connected with the first end of the resistor R402, the second end of the resistor R402 is connected with the second end of the capacitor C73 and the first end of the resistor R71 respectively, the second end of the resistor R71 is connected with the second end of the resistor R4 and one end of the capacitor C83 away from the TXN pin of the master control chip respectively, the D1_FB pin of the chip U6 is connected with the D2_FB pin of the chip U6 through the resistor R37 and the capacitor C61, the D1_FB pin of the chip U6 is connected with the D1_OUT pin of the chip U6 through the resistor R15, the D2_FB pin of the chip U6 is connected with the D1_OUT pin of the chip U6 through the resistor R3, the BIAS-1 pin and the BIAS-2 pin of the chip U6 are connected with the GPIO_8 pin of the master control chip, the IADJ pin of the chip U6 is grounded through the resistor R5, the VS+ pin of the chip U6 is connected with a 12V power supply, the VS pin of the chip U6 is grounded, the D1_OUT pin of the chip U6 is connected with the first end of the resistor R14, the second end of the resistor R14 is connected with the first end of the diode D7 and IOUT+ respectively, the second end of the diode D7 is connected with a 12V power supply, the third end of the diode D7 is grounded, the D2_OUT pin of the chip U6 is connected with the first end of the resistor R34, the second end of the resistor R34 is connected with the first end of the diode D6 and IOUT- respectively, the second end of the diode D6 is connected with a 12V power supply, the third end of the diode D6 is grounded, the GND pin and the SINK pin of the chip U6 are grounded.

[0090] The connection mode of the filter circuit is as follows:

[0091] The first end of the capacitor C62 and the first end of the capacitor C63 are connected with a 12V power supply, and the second end of the capacitor C62 and the second end of the capacitor C63 are grounded.

[0092] The connection mode of the carrier signal receiving circuit is as follows:

[0093] The first end of the resistor R1206 is connected with RX+_SWITCH and the first end of the capacitor C1202 respectively, the second end of the capacitor C1202 is connected with the first end of the capacitor C41 and the first end of the inductor L1201 respectively, the second end of the capacitor C41 is connected with the first end of the inductor L401 and the first end of the capacitor C16 respectively, the second end of the capacitor C16 is connected with RX+_P, the second end of the inductor L401 is connected with the first end of the capacitor C40 and the first end of the capacitor C38 respectively, the second end of the capacitor C38 is connected with RX-_N, the second end of the capacitor C40 is connected with the first end of the capacitor C1201, the second end of the capacitor C1201 is connected with the second end of the resistor R1206 and RX-_SWITCH respectively.

[0094] The connection mode of the high-pass filter circuit is as follows:

[0095] The first end of the capacitor C14 is connected with the RXP pin of the master control chip in the master control circuit, the second end of the capacitor C14 is connected with the first end of the diode D402, the first end of the resistor R23, the first end of the capacitor C405 and the first end of the inductor L5 respectively, the second end of the diode D402 is grounded, the third end of the diode D402 is grounded through the capacitor C12, the second end of the inductor L5 is connected with RX_SWITCH_P, the second end of the capacitor C405 is connected with the first end of the inductor L6, the second end of the inductor L6 is connected with RX_SWITCH_N, the second end of the inductor L6 is connected with the second end of the resistor R23, the first end of the diode D401 and the first end of the capacitor C15 respectively, the second end of the diode D401 is grounded, the third end of the diode D401 is connected with 3V3_AFE, and the second end of the capacitor C15 is connected with the RXN pin of the master control chip in the master control circuit.

[0096] The connection mode of the attenuation circuit is as follows:

[0097] The first end of the resistor R1 is connected with RX_HPF_P, the second end of the resistor R1 is connected with the first end of the resistor R1202 and the first end of the resistor R1203 respectively, the second end of the resistor R1202 is connected with the first end of the resistor R1204 and RX+ respectively, the second end of the resistor R1204 is connected with RX- and the first end of the resistor R1201 respectively, the second end of the resistor R1201 is connected with the second end of the resistor R1203 and the first end of the resistor R403 respectively, and the second end of the resistor R403 is connected with RX_HPF_N.

[0098] As Figure 14 and Figure 15As shown, the bidirectional zero-crossing detection module includes a positive half-cycle zero-crossing detection circuit and a negative half-cycle zero-crossing detection circuit. The positive half-cycle zero-crossing detection circuit includes a first zero-crossing detection chip U2, a first resistor R65 and a first optocoupler U10, the input end of the first zero-crossing detection chip U2 is electrically connected with the output end of the power module, the output end of the first zero-crossing detection chip U2 is in communication connection with the input end of the first optocoupler U10 through the first resistor R65, and the output end of the first optocoupler U10 is in communication connection with the input end of the main control circuit. The first zero-crossing detection chip U2 adopts a GS1102 chip, the first optocoupler U10 adopts an LTV-816S-D3-TX chip, the positive half-cycle zero-crossing detection circuit collects the signal output by the power module, processes the signal, and transmits the processed signal to the main control circuit through the first optocoupler, so as to realize the zero-crossing detection of the positive half cycle of the alternating current line.

[0099] The connection mode of the positive half-cycle zero-crossing detection circuit is as follows:

[0100] The first end of the resistor R13 is connected with the zero line LINE_N of the commercial power supply, the second end of the resistor R13 is connected with the IN pin of the first zero-crossing detection chip U2 through the resistor R167, the resistor R169 and the resistor R67, the VDD pin of the first zero-crossing detection chip U2 is connected with the first pin of the first optocoupler U10 through the first resistor R65, the VDD pin of the first zero-crossing detection chip U2 is connected with the second pin of the first optocoupler U10, the VSS pin of the first zero-crossing detection chip U2 is connected with the fire line LINE_A of the commercial power supply, the VSS pin of the first zero-crossing detection chip U2 is connected with the first pin of the first optocoupler U10 through the capacitor C58, the third pin of the first optocoupler U10 is grounded through the capacitor C143, the third pin of the first optocoupler U10 is connected with the 3.3V power supply, the fourth pin of the first optocoupler U10 is grounded through the resistor R6, the fourth pin of the first optocoupler U10 is grounded in sequence through the resistor R28 and the capacitor C82, and the fourth pin of the first optocoupler U10 is connected with the ADC_CH1 pin of the main control chip in the main control circuit through the resistor R28.

[0101] The negative half-cycle zero-crossing detection circuit includes a second zero-crossing detection chip U3, a second resistor R106 and a second optocoupler U13, the input end of the second zero-crossing detection chip is electrically connected with the output end of the power module, the output end of the second zero-crossing detection chip is in communication connection with the input end of the second optocoupler U13 through the second resistor R106, and the output end of the second optocoupler U13 is in communication connection with the input end of the main control circuit. The second zero-crossing detection chip U3 adopts a GS1102 chip, the second optocoupler U13 adopts an LTV-816S-D3-TX chip, the negative half-cycle zero-crossing detection circuit collects the signal output by the power module, processes the signal, and transmits the processed signal to the main control circuit through the first optocoupler U13, so as to realize the zero-crossing detection of the negative half cycle of the alternating current line.

[0102] The connection mode of the negative half-cycle zero-crossing detection circuit is as follows:

[0103] The first end of the resistor R91 is connected with the live line LINE A, the second end of the resistor R91 is connected with the IN pin of the second zero-crossing detection chip U3 through the resistor R174, the resistor R175 and the resistor R114, the VDD pin of the second zero-crossing detection chip U3 is connected with the first pin of the second optocoupler U13 through the second resistor R106, the VDD pin of the second zero-crossing detection chip U3 is connected with the second pin of the second optocoupler U13, the VSS pin of the second zero-crossing detection chip U3 is connected with the zero line LINE N, the VSS pin of the second zero-crossing detection chip U3 is connected with the first pin of the second optocoupler U13 through the capacitor C59, the third pin of the second optocoupler U13 is grounded through the capacitor C155, the third pin of the second optocoupler U13 is connected with the 3.3V power supply, the fourth pin of the second optocoupler U13 is grounded through the resistor R78 respectively, the fourth pin of the second optocoupler U13 is grounded through the resistor R51 and the capacitor C109 in turn, and the fourth pin of the second optocoupler U13 is connected with the GPIO_2 pin of the main control chip in the main control circuit through the resistor R51.

[0104] In the embodiment, the bidirectional zero-crossing detection module can detect the zero-crossing points of the positive and negative half cycles of the power supply signal at the same time, can more comprehensively monitor the change of the power supply waveform, can better maintain the synchronization and stability of the system, and can reduce the transmission error caused by the fluctuation of the power supply waveform. The first resistor is connected between the output end of the zero-crossing detection chip and the input end of the optocoupler, which plays a role of current limiting protection. Since the signal output by the zero-crossing detection chip has a high voltage or current, direct connection to the optocoupler can cause damage or performance degradation of the optocoupler. By connecting the first resistor in series, the current flowing through the optocoupler can be limited, the optocoupler can be protected, and the optocoupler can work normally. Moreover, the bidirectional zero-crossing detection can detect the zero-crossing points of the positive and negative half cycles of the power supply signal at the same time, which can more comprehensively monitor the change of the power supply waveform. Moreover, the output end of the optocoupler is in communication connection with the input end of the main control circuit, which realizes the electrical isolation between the strong and weak electricity, not only protects the main control circuit from the interference and damage of the strong electricity signal, but also improves the safety and stability.

[0105] As shown in Figures 16 to 17 The power supply module includes a 3V3_DCDC circuit and a DCDC circuit, the power supply chip U1002 adopts SY8301ABC in the DCDC circuit, and the connection mode of the DCDC circuit is as follows:

[0106] The SW pin of the chip U1002 is connected with the BST pin of the chip U1002 through the resistance R1014 and the capacitor C1014, the SW pin of the chip U1002 is connected with the first end of the inductor L1001, the second end of the inductor L1001 outputs a 5V power supply, the VIN / IN pin of the chip U1002 is connected with the first end of the inductor LB1001, the second end of the inductor LB1001 is connected with a 12V power supply, the EN / DIM pin of the chip U1002 is connected with the first end of the inductor LB1001 through the resistance R1015, the EN / DIM pin of the chip U1002 is grounded through the resistance R1016 and the capacitor C1019 respectively, the first end of the capacitor C1020 and the first end of the C1018 are connected with the first end of the inductor LB1001 respectively, the second end of the capacitor C1020 and the second end of the C1018 are grounded, the GND pin of the chip U1002 is grounded, the FB pin of the chip U1002 is grounded through the resistance R1017, the FB pin of the power supply chip U1002 is connected with the second end of the inductor L1001 through the resistance R1013 and the capacitor 1015 respectively, the first end of the capacitor C1017 and the first end of the capacitor C1016 are connected with the second end of the inductor L1001 respectively, the second end of the capacitor C1017 and the second end of the capacitor C1016 are grounded.

[0107] The connection mode of the 3V3_DCDC circuit is as follows:

[0108] The SW pin of the chip U15 is connected with the BST pin of the chip U15 through the resistance R141 and the capacitor C69, the SW pin of the chip U15 is connected with the first end of the inductor L4, the second end of the inductor L4 outputs a 3.3V power supply, the VIN / IN pin of the chip U15 is connected with the first end of the inductor LB3, the second end of the inductor LB3 is connected with a 12V power supply, the VIN / IN pin of the chip U15 is connected with the first end of the resistance R94, the first end of the capacitor C67 and the first end of the capacitor C24 respectively, the second end of the resistance R94 is connected with the EN / DIM pin of the chip U15, the second end of the capacitor C67 and the second end of the capacitor C24 are grounded, the EN / DIM pin of the chip U15 is grounded through the resistance R131 and the capacitor C70 respectively, the GND pin of the chip U15 is grounded, the FB pin of the chip U15 is connected with the first end of the resistance R26, the first end of the resistance R93 and the first end of the capacitor C22 respectively, the second end of the resistance R26 and the second end of the capacitor C22 are connected with the second end of the inductor L4, the second end of the resistance R93 is grounded, the first end of the capacitor C3 and the first end of the capacitor C8 are connected with the second end of the inductor L4, the second end of the capacitor C3 and the second end of the capacitor C8 are grounded.

[0109] As Figure 18As shown, the input end of the indicator lamp circuit is connected with the output end of the main control circuit, the indicator lamp circuit includes the running lamp D4, the carrier wave communication indicator lamp D36, the RF communication indicator lamp D3 and the uplink communication indicator lamp D5, and the connection mode of the indicator lamp circuit is as follows:

[0110] The first end of the resistor R146 is connected with the GPIO_21 pin of the main control chip, the second end of the resistor R146 is connected with the positive electrode of the running lamp D4, the negative electrode of the running lamp D4 is grounded, the first end of the resistor R148 is connected with the GPIO_15 pin of the main control chip, the second end of the resistor R148 is connected with the positive electrode of the carrier wave communication indicator lamp D36, the negative electrode of the carrier wave communication indicator lamp D36 is grounded, the first end of the resistor R150 is connected with the GPIO_17 pin of the main control chip, the second end of the resistor R150 is connected with the positive electrode of the RF communication indicator lamp D3, the negative electrode of the RF communication indicator lamp D3 is grounded, the first end of the resistor R147 is connected with the I2C0_SDA pin of the main control chip, the second end of the resistor R147 is connected with the positive electrode of the uplink communication indicator lamp D5, and the negative electrode of the uplink communication indicator lamp D5 is grounded.

[0111] As shown in the figure, Figure 19 The input end of the buzzer circuit is connected with the output end of the main control circuit, the buzzer circuit includes the triode Q501 and the buzzer SP501, and the connection mode of the buzzer circuit is as follows:

[0112] The first end of the capacitor C514 and the first end of the capacitor C513 are connected with the 3.3V power supply, the second end of the capacitor C514 and the second end of the capacitor C513 are grounded, the first end of the resistor R509 is connected with the 3.3V power supply, the second end of the resistor R509 is connected with the collector of the triode Q501, the base of the triode Q501 is connected with the first end of the resistor R508, the second end of the resistor R508 is connected with the UART0_RXD pin of the main control chip, the emitter of the triode Q501 is grounded through the capacitor C512, the emitter of the triode Q501 is connected with the positive electrode of the buzzer SP501, and the negative electrode of the buzzer SP501 is grounded.

[0113] The application integrates three communication interface modes of RJ45, USB and UART through the communication debugging module, improves the interface compatibility of the copy controller, can adapt to the access needs of various terminal devices, and effectively solves the technical limitations that the existing copy controller only supports a single interface. At the same time, the application unifies the coordination and management of the RJ45, USB and UART communication interfaces through the main control circuit, realizes the integration and efficient cooperation of various interfaces, supports diversified data access, transmission and processing. In addition, the carrier signal processing module and the RF signal processing module are adopted, which respectively realizes the support for power line communication and wireless communication, meets the communication needs of the copy controller in various complex scenes, and further enhances the adaptability and practicality of the system.

[0114] The above are all preferred embodiments of the present application, and do not limit the protection scope of the present application, so that: all equivalent changes made according to the structure, shape, principle of the present application should be covered within the protection scope of the present application.

Claims

1. A power line broadband carrier based meter reading system, characterized by, The application relates to a controller system, which comprises a main control circuit, a carrier signal processing module, an RF signal processing module, a communication debugging module and a power module. The communication debugging module comprises an RJ45 communication circuit, a USB communication circuit and a UART interface module. The RJ45 communication circuit comprises an RJ45 interface circuit and a PHY chip circuit. The output end of the USB communication circuit is in communication connection with the input end of the main control circuit, and the input end of the USB communication circuit is in communication connection with the output end of the main control circuit. The output end of the UART interface module is in communication connection with the input end of the main control circuit, and the input end of the UART interface module is in communication connection with the output end of the main control circuit. The RJ45 interface circuit comprises an RJ45 socket.

2. The power line broadband carrier based meter reading system of claim 1 wherein, The output end of the RJ45 socket is in communication connection with the input end of the PHY chip circuit, and the input end of the RJ45 socket is in communication connection with the output end of the PHY chip circuit. The PHY chip circuit comprises a first crystal oscillator and a PHY chip. The input end of the PHY chip is in communication connection with the output end of the RJ45 socket, the output end of the PHY chip is in communication connection with the input end of the RJ45 socket, and the output end and the input end of the PHY chip are both connected with the first crystal oscillator. The USB communication circuit comprises a USB chip and a second crystal oscillator.

3. The power line broadband carrier based meter reading controller system according to claim 1, wherein, The input end of the USB chip is connected with the output end of the main control module, the output end of the USB chip is connected with the input end of the main control circuit, and the input end and the output end of the USB chip are both connected with the second crystal oscillator. The controller system further comprises a bidirectional zero-crossing detection module.

4. The power line broadband carrier based meter reading controller system according to claim 1, wherein, The output end of the zero-crossing detection module is in communication connection with the input end of the main control circuit, and the zero-crossing detection module is electrically connected with the power module. The bidirectional zero-crossing detection module comprises a positive half-cycle zero-crossing detection circuit and a negative half-cycle zero-crossing detection circuit.

5. The power line broadband carrier based load controller system of claim 4 wherein, The positive half-cycle zero-crossing detection circuit comprises a first zero-crossing detection chip, a first resistor and a first optocoupler. The input end of the first zero-crossing detection chip is electrically connected with the output end of the power module, the output end of the first zero-crossing detection chip is in communication connection with the input end of the first optocoupler through the first resistor, and the output end of the first optocoupler is in communication connection with the input end of the main control circuit. The negative half-cycle zero-crossing detection circuit comprises a second zero-crossing detection chip, a second resistor and a second optocoupler.

6. The power line broadband carrier based meter reading system of claim 1 wherein, The input end of the second zero-crossing detection chip is electrically connected with the output end of the power module, the output end of the second zero-crossing detection chip is in communication connection with the input end of the second optocoupler through the second resistor, and the output end of the second optocoupler is in communication connection with the input end of the main control circuit. The power module comprises a 3V3_DCDC circuit and a DCDC circuit. 3V3_DCDC circuit input end access 12V power supply, 3V3_DCDC circuit output end and master control circuit input end, carrier signal processing module input end, RJ45 communication circuit input end and UART interface module input end electric connection; DCDC circuit input end access 12V power supply, DCDC circuit output end and USB communication circuit input end electric connection.

7. The power line broadband carrier based meter reading system of claim 1 wherein, The system further comprises an indicator circuit. The input end of the indicator circuit is connected with the output end of the master control circuit.

8. The power line broadband carrier based meter reading system of claim 1 wherein, The system further comprises a buzzer circuit. The input end of the buzzer circuit is connected with the output end of the master control circuit.

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