High-speed password card based on array quantum random number chip
By using a high-speed cryptographic card based on an array of quantum random number chips, and utilizing multiple quantum random number chipsets and processing modules, the problem of insufficient encryption and decryption speed of existing quantum cryptographic cards is solved, and high-speed encryption and decryption processing is achieved.
Patent Information
- Application Number
- CN202423322988.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-11-28
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Existing quantum cryptographic cards, due to their use of built-in random number generators, have limited encryption and decryption speeds, which cannot meet the needs of processing large amounts of data.
A high-speed cryptographic card based on array quantum random number chips is adopted. Multiple quantum random number chip groups are used as random number generation sources, and combined with the first processing module and the second processing module, the encryption and decryption speed is improved.
It enables the rapid generation of a large number of random numbers, significantly improving the encryption and decryption speed and meeting the needs of high-speed data processing.
Smart Images
Figure CN223611933U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to password card technical field, concretely relates to a high -speed password card based on array quantum random number chip. BACKGROUND
[0002] Quantum random number generator (QRNG) is based on quantum effect, is the only theoretically provable true random number generator so far, has higher true randomness, security.
[0003] With the data processing speed sudden increase and optimization of quantum algorithm brought by quantum technology development, the traditional data encryption technology depending on complex algorithm can be cracked in theory, and the security of encrypted data is seriously threatened.
[0004] The security of quantum encryption technology is based on the basic principle of quantum mechanics, provides absolute security guarantee that cannot be eavesdropped and cracked by calculation. However, the existing quantum password card uses the random number generator built in the security chip as the random number generation source, and the rate of generating random numbers is limited by the number and process of the built-in random number generator, cannot generate random numbers at high speed, causes the encryption and decryption work rate to be hindered, cannot be applied to the occasion needing to handle a large amount of data.
[0005] Therefore, it is necessary to improve the existing quantum password card, and propose a quantum password card with higher encryption and decryption rate. CONTENT OF UTILITY MODEL
[0006] The utility model discloses in order to solve the problem of the encryption and decryption rate of the existing quantum password card not enough high, propose a high -speed password card based on array quantum random number chip.
[0007] In order to achieve the above object, the technical scheme adopted by the utility model is as follows:
[0008] A high -speed password card based on array quantum random number chip, including quantum random number chip group, first processing module, second processing module, key storage module and communication interface;
[0009] The quantum random number chip group includes a plurality of quantum random number chips;
[0010] The first processing module is connected with quantum random number chip group, second processing module and key storage module respectively, and the second processing module is connected with communication interface.
[0011] In the scheme, the quantum random number chip set including multiple quantum random number chips is used as a random number generation source, so that a large number of random numbers can be quickly generated, and the random numbers generated by the quantum random number chip set are used for encryption and decryption processing by the first processing module and the second processing module respectively, so that the encryption and decryption rate is improved.
[0012] Preferably, the quantum random number chip set includes four quantum random number chips.
[0013] Preferably, the first processing module is a cryptographic algorithm chip set.
[0014] Preferably, the cryptographic algorithm chip set includes multiple national cryptographic algorithm chips.
[0015] Preferably, the second processing module is an FPGA.
[0016] Preferably, a first crystal oscillator is further included.
[0017] The first crystal oscillator is connected with a global clock pin of the FPGA.
[0018] The frequency of the first crystal oscillator is 200MHz.
[0019] Preferably, a second crystal oscillator is further included.
[0020] The second crystal oscillator is connected with a high-speed transceiver clock pin of the FPGA.
[0021] The frequency of the first crystal oscillator is 156.25MHz.
[0022] Preferably, a FLASH configuration chip is further included; the FLASH configuration chip is connected with the FPGA.
[0023] Preferably, the communication interface includes a PCIE interface and an Ethernet interface; the PCIE interface and the Ethernet interface are connected with the second processing module respectively.
[0024] Preferably, the communication interface further includes an Ethernet PHY chip; the Ethernet interface is connected with the second processing module through the Ethernet PHY chip.
[0025] The beneficial technical effects of the utility model are as follows:
[0026] The utility model discloses a high-speed cryptographic card based on array quantum random number chip, and the quantum random number chip set including multiple quantum random number chips is used as a random number generation source, so that a large number of random numbers can be quickly generated, and the random numbers generated by the quantum random number chip set are used for encryption and decryption processing by the first processing module and the second processing module respectively, so that the encryption and decryption rate is improved. BRIEF DESCRIPTION OF DRAWINGS
[0027] Figure 1 The module connection schematic diagram of the utility model;
[0028] Among them: 1, quantum random number chip set; 2, first processing module; 3, second processing module; 4, key storage module; 5, communication interface; 51, PCIE interface; 52, Ethernet interface; 53, Ethernet PHY chip; 6, first crystal oscillator; 7, second crystal oscillator; 8, FLASH configuration chip. DETAILED DESCRIPTION
[0029] In order to make the utility model's purpose, technical scheme and advantage more clearly, the following with example further detailedly explains the utility model, but the utility model's scope of protection is not limited to the following specific embodiment.
[0030] Example 1
[0031] As Figure 1 Indicated, a kind of high-speed cryptographic card based on array quantum random number chip, including quantum random number chip set 1, first processing module 2, second processing module 3, key storage module 4 and communication interface 5;
[0032] The quantum random number chip set 1 includes multiple quantum random number chips;
[0033] The first processing module 2 is connected with quantum random number chip set 1, second processing module 3 and key storage module 4 respectively, and the second processing module 3 is connected with communication interface 5.
[0034] In the specific implementation process, quantum random number chip set 1 including multiple quantum random number chips is used as the generation source of random number, so that a large number of random numbers can be quickly generated, and the random numbers generated by quantum random number chip set 1 are used in different encryption and decryption scenarios by first processing module 2 and second processing module 3 respectively, so as to improve the encryption and decryption rate.
[0035] Example 2
[0036] A kind of high-speed cryptographic card based on array quantum random number chip, including quantum random number chip set 1, first processing module 2, second processing module 3, key storage module 4 and communication interface 5;
[0037] More specifically, the quantum random number chip set 1 includes four quantum random number chips.
[0038] In the specific implementation process, the rate that quantum random number chip set 1 generates random number can reach 400Mbps, completely satisfies the demand of using random number as key seed source in existing cryptographic application.
[0039] More specifically, the first processing module 2 is a cryptographic algorithm chip set.
[0040] More specifically, the cryptographic algorithm chip set includes a plurality of national cryptographic algorithm chips.
[0041] In the specific implementation process, the cryptographic algorithm chip set is mainly composed of a plurality of existing national cryptographic algorithm chips capable of performing cryptographic algorithm operations such as SM1, SM2, and SM3. A large number of keys are generated by receiving the random number sequence generated by the quantum random number chip set 1, and the generated keys are stored in the key storage module 4. At the same time, data can also be transmitted to the cryptographic algorithm chip set for SM1, SM2, and SM3 encryption and decryption processing.
[0042] More specifically, the second processing module 3 is an FPGA.
[0043] In the specific implementation process, the FPGA receives the data to be encrypted and decrypted transmitted by the external device through the communication interface 5, and sends the data to be encrypted and decrypted to the cryptographic algorithm chip set for encryption and decryption processing. At the same time, the FPGA preloads existing encryption and decryption algorithms (such as DES), so it can also obtain quantum keys from the key storage module 4 to encrypt and decrypt the data to be encrypted and decrypted.
[0044] More specifically, it also includes a first crystal oscillator 6.
[0045] The first crystal oscillator 6 is connected to the global clock pin of the FPGA.
[0046] The frequency of the first crystal oscillator 6 is 200MHz.
[0047] In the specific implementation process, the 200MHz crystal oscillator is used as the system working clock of the FPGA, and the clock signal enters the FPGA through the global clock pin of the FPGA. The FPGA works at high speed according to the clock.
[0048] More specifically, it also includes a second crystal oscillator 7.
[0049] The second crystal oscillator 7 is connected to the high-speed transceiver clock pin of the FPGA.
[0050] The frequency of the first crystal oscillator 6 is 156.25MHz.
[0051] In the specific implementation process, the 156.25MHz clock crystal oscillator is used as the high-speed transceiver clock of the FPGA, and the clock signal enters the FPGA through the clock input pin of the high-speed transceiver. Its main function is to serve as the reference clock of the PCIE interface 51 of the FPGA. The PCIE interface 51 interacts with the external device at high speed according to the reference clock.
[0052] More specifically, the FLASH configuration chip 8 is further included; the FLASH configuration chip 8 is connected with the FPGA.
[0053] In the specific implementation process, the FLASH configuration chip 8 is used to store the start-up image program of the FPGA, and the FPGA is initialized and configured when the device is initially powered on.
[0054] More specifically, the communication interface 5 includes the PCIE interface 51 and the Ethernet interface 52; the PCIE interface 51 and the Ethernet interface 52 are respectively connected with the second processing module 3.
[0055] More specifically, the communication interface 5 further includes the Ethernet PHY chip 53; the Ethernet interface 52 is connected with the second processing module 3 through the Ethernet PHY chip 53.
[0056] In the specific implementation process, the quantum random number chip set 1 outputs the quantum random number source sequence to the cryptographic algorithm chip set at high speed, the cryptographic algorithm chip set obtains the quantum key according to the quantum random number source sequence by using the built-in key algorithm, and the quantum key is transmitted to the key storage module 4. When the external device transmits the data to be encrypted and decrypted to the FPGA through the PCIE interface 51 or the Ethernet interface 52, the FPGA transmits the data to be encrypted and decrypted to the data cache space in the FPGA, and the FPGA judges the data to be encrypted and decrypted at the same time.
[0057] If the data request uses the SM1, SM2, SM3 and the like for encryption and decryption, the data encryption and decryption is performed in the cryptographic algorithm chip set, and the working principle is as follows:
[0058] The FPGA sends an encryption and decryption request command to the cryptographic algorithm chip set, and transmits the data to the cryptographic algorithm chip set, the cryptographic algorithm chip set reads the quantum key in the key storage module 4 according to the encryption and decryption request command, and uses the quantum key to perform the encryption and decryption work on the data; after the encryption and decryption is completed, the cryptographic algorithm chip set transmits the data to the FPGA, and the FPGA transmits the data to the external device through the PCIE interface 51 or the Ethernet interface;
[0059] If the data request uses the DES cryptographic algorithm for encryption and decryption, the data encryption and decryption is performed in the FPGA, and the working principle is as follows:
[0060] The FPGA sends a key request command to the cryptographic algorithm chip set, the cryptographic algorithm chip set reads the quantum key in the key storage module 4 according to the key request command and sends it to the FPGA, the FPGA takes out the data from the data cache space, uses the quantum key to perform the encryption and decryption on the data; after the encryption and decryption is completed, the FPGA transmits the data to the external device through the PCIE interface 51 or the Ethernet interface.
[0061] Further modifications and changes to the embodiments disclosed herein can occur to those skilled in the art with the disclosures and teachings provided in the above descriptions. As such, the specifics of the embodiments disclosed herein are not to be taken as limiting the present application, but rather are to be taken as merely representative of the generic application described. In addition, while the particular terminology used through out this specification has been chosen for the sake of clarity, no limitation of the application is intended thereby.
Claims
1. A high-speed cryptographic card based on an array quantum random number chip, characterized in that, It includes a quantum random number chipset, a first processing module, a second processing module, a key storage module, and a communication interface; The quantum random number chipset includes multiple quantum random number chips; The first processing module is connected to the quantum random number chipset, the second processing module, and the key storage module, respectively, and the second processing module is connected to the communication interface.
2. A high-speed cryptographic card based on an array quantum random number chip according to claim 1, characterized in that, The quantum random number chipset includes four quantum random number chips.
3. A high-speed cryptographic card based on an array quantum random number chip according to claim 1, characterized in that, The first processing module is a cryptographic algorithm chipset.
4. A high-speed cryptographic card based on an array quantum random number chip according to claim 3, characterized in that, The cryptographic algorithm chipset includes multiple national cryptographic algorithm chips.
5. A high-speed cryptographic card based on an array quantum random number chip according to claim 1, characterized in that, The second processing module is an FPGA.
6. A high-speed cryptographic card based on an array quantum random number chip according to claim 5, characterized in that, It also includes a first crystal oscillator; The first crystal oscillator is connected to the global clock pin of the FPGA; The frequency of the first crystal oscillator is 200MHz.
7. A high-speed cryptographic card based on an array quantum random number chip according to claim 6, characterized in that, It also includes a second crystal oscillator; The second crystal oscillator is connected to the clock pin of the FPGA's high-speed transceiver; The frequency of the first crystal oscillator is 156.25MHz.
8. A high-speed cryptographic card based on an array quantum random number chip according to claim 5, characterized in that, It also includes a FLASH configuration chip; the FLASH configuration chip is connected to the FPGA.
9. A high-speed cryptographic card based on an array quantum random number chip according to claim 1, characterized in that, The communication interface includes a PCIe interface and an Ethernet interface; the PCIe interface and the Ethernet interface are respectively connected to the second processing module.
10. A high-speed cryptographic card based on an array quantum random number chip according to claim 9, characterized in that, The communication interface also includes an Ethernet PHY chip; the Ethernet interface is connected to the second processing module through the Ethernet PHY chip.