Image display system

Abstract

The utility model relates to an image display system, which comprises a frame image signal generator, a frame image divider, a frame image distributor, a frame image processor, a frame image divider and at least one image display which are sequentially in communication connection, wherein the frame image splitter splits the frame image to be transmitted to the frame image processor in a predetermined splitting manner and the frame image distributor transmits at least some of the frame image portions in combination into the at least one frame image pipeline in a predetermined distribution manner. The frame image divider correspondingly displays each of the processed combined frame image portions at a corresponding location of the at least one image display. By means of the method and the device, the frame image pipeline can be efficiently used in a saving manner, so that the occupation of the frame image displayed on the oversize screen is reduced.

Description

Technical Field

[0001] This application relates to an image display system. Background Technology

[0002] In the field of display systems, ultra-wide screens, ultra-long screens, or ultra-large screens (hereinafter collectively referred to as oversized displays and will be defined in detail later) are gradually becoming popular, such as 8K ultra-wide narrow screens, whose total number of pixels is, for example, 7680x2160 pixels.

[0003] As is known to those skilled in the art, existing GPUs or CPUs have at least one frame image pipeline for receiving and processing frame images. As is known, each frame image pipeline is typically configured and set with a limit on the total number of frame image pixels, for example, supporting only frame images with a length of L1 pixels and a width of L2 pixels, such that the total length of the frame image pixels it can process must not be greater than L1 and its width must not be greater than L2.

[0004] In this context, in the prior art, for the aforementioned oversized screen, if at least one of the length or width of the pixels in the displayed frame image exceeds the corresponding limit of the total number of pixels in the frame image, an additional frame image pipeline is required to process the excess residual image. For example, for a frame image pipeline that supports frame images with a length of L1 = 3840 pixels and a width of L2 = 4320 pixels, if it is required to process a 7680 (length) x 2160 (width) pixel frame image for display on an 8K oversized screen, at least two frame image pipelines are needed to process two portions of the 3840 (length) x 2160 (width) image respectively (the image segmentation is implemented using frame image capturers known in the prior art, either integrated into or independent of the GPU or CPU). This obviously reduces the number of frames that a GPU or CPU can process in a frame pipeline when dealing with oversized screens (because each oversized screen occupies more frame pipeline lines, and the frame pipeline lines of each GPU or CPU are usually deterministic or finite), thus preventing it from supporting the display of as many screens as possible.

[0005] Therefore, there is a need for an image display system that can save on the footprint of the frame image pipeline. Utility Model Content

[0006] According to a first aspect of this application, an image display system is provided, including a frame image signal generator, a frame image splitter, a frame image distributor, a frame image processor, a frame image splitter, and at least one image display that are sequentially and communicatively connected.

[0007] The frame image signal generator is configured to generate a frame image to be displayed on at least one image display.

[0008] At least one image display is configured to display a frame image with a pixel length of L3 and a pixel width of L4;

[0009] The frame image processor is configured with at least one frame image pipeline, and the at least one frame image pipeline is configured to support frame images with a length limit of L1 pixels and a width limit of L2 pixels.

[0010] The frame image segmenter is communicatively connected to the frame image signal generator and is configured to segment the frame image to be transmitted to the frame image processor based on a predetermined segmentation method according to a length limit L1, a width limit L2, a pixel length L3, and a pixel width L4, so that each resulting frame image portion is within the range defined by the length limit L1 and the width limit L2.

[0011] The frame image distributor is communicatively connected between the frame image segmenter and the frame image processor and is configured to transmit at least some of the frame image portions in combination to at least one frame image pipeline in a predetermined allocation manner based on a length limit L1 and a width limit L2, wherein the combined dimensions of at least some of the frame image portions are within the range defined by the length limit L1 and the width limit L2; and

[0012] The frame image splitter is communicatively connected to the frame image processor and displays each of the processed and combined frame image portions at a corresponding position on at least one image display.

[0013] Optionally, the image display system also includes a parallel-to-serial converter and a serial-to-parallel converter disposed between the frame image processor and the frame image splitter.

[0014] Optionally, at least one image display is configured to display a frame image with a pixel length L3 of 7680 and a pixel width L4 of 2160, and at least one frame image pipeline has a length limit L1 of 5000 pixels and a width limit L2 of 5000 pixels.

[0015] Optionally, the frame image segmenter divides the frame image from the frame image signal generator into two frame image portions, each with a length of 3840 pixels and a width of 2160 pixels, using a length-average segmentation method, to obtain two frame image portions, each with a length of 3840 pixels and a width of 2160 pixels.

[0016] Optionally, the frame image distributor transmits two frame image portions in a combined manner to at least one frame image pipeline in an aligned side-by-side distribution to obtain a combined frame image portion with a pixel length of 3840 and a loudness width of 4320.

[0017] Optionally, the frame image splitter is configured to determine the actual position of each frame image portion within the complete frame image based on the segmentation and allocation methods of the frame images.

[0018] Optionally, at least one of the frame image segmenter and the frame image allocator is integrated into the frame image processor.

[0019] Optionally, the frame image splitter is integrated into a serial-to-parallel converter; or the frame image splitter is integrated into at least one image display.

[0020] Optionally, the frame image processor transmits the processed combined frame image portions in the form of a DP signal or an HDMI signal; and / or, the frame image splitter displays each frame image portion at a corresponding position on at least one image display in the form of a DP signal or an HDMI signal.

[0021] Optionally, the image display is an image display for a vehicle, and / or the image display is an oversized display.

[0022] With the help of this application, the frame image pipeline can be used efficiently in a cost-effective manner, thereby reducing the amount of frame images used for display on large screens, thus enabling the display of more screens with fewer GPUs or CPUs. Attached Figure Description

[0023] Other notable features and advantages of this application will be apparent from the following non-limiting description provided for illustrative purposes with reference to the accompanying drawings, wherein:

[0024] Figure 1 A schematic diagram of the structure of an image display system according to a first embodiment of this application is shown;

[0025] Figure 2 A schematic diagram of the structure of an image display system according to a second embodiment of this application is shown; and

[0026] Figure 3 A schematic diagram is shown during frame image transmission according to a specific embodiment of this application. Detailed Implementation

[0027] The following description is merely illustrative and is not intended to limit this application or its application or use. It is also understood that in all the drawings, the corresponding reference numerals denote the same or corresponding parts and features.

[0028] Before proceeding with the following description, the term "oversized screen" is defined herein. In embodiments of this application, an oversized screen refers to a screen in which at least one of the pixel length or pixel width of the frame image it displays exceeds the corresponding length limit or width limit of a single frame image pipeline. Referring to the preceding description, if a single frame image pipeline is configured to only support frame image processing with a length of L1 pixels and a width of L2 pixels (i.e., the maximum total number of pixels is L1xL2), and the pixel length and pixel width of the frame image to be displayed on a screen are set to L3 and L4 respectively (i.e., the total number of image pixels is L3xL4), then if L3 is greater than L1 or L4 is greater than L2, the screen is referred to as an "oversized screen".

[0029] The following will refer to Figure 1-3 Detailed embodiments of the image display system according to this application are described. It should be noted that, in the various embodiments of this application, unless explicitly stated that one or more features cannot be combined with each other or are clearly contradictory, the corresponding features in different embodiments can be combined with each other without departing from the scope of this application.

[0030] Figure 1 A schematic diagram of the structure of an image display system 1 according to a first embodiment of this application is shown. Figure 1 In the illustrated embodiment, the image display system is sequentially communicatively connected to: a frame image signal generator 100, optionally a comparator (not shown), a frame image splitter 102, a frame image distributor 104, a frame image processor 106, a frame image splitter 108, and at least one image display 110.

[0031] like Figure 1 As shown, in an embodiment of this application, the image display system 1 includes a frame image signal generator 100, which is configured to generate a frame image or frame image signal to be displayed.

[0032] like Figure 1 As shown in the embodiments of this application, the image display system 1 further includes at least one image display 110, which is configured to display a frame image with a pixel length of L3 and a pixel width of L4 (or L3xL4).

[0033] like Figure 1As shown, the image display system 1 includes a frame image processor 106, which is configured with at least one frame image pipeline 1060, the at least one frame image pipeline 1060 being configured to support frame images with a length limit of L1 pixels and a width limit of L2 pixels. As those skilled in the art know, the total number of pixels (i.e., pixel length x pixel width) of the image displayed by the image display 110 is consistent with the total number of pixels of the frame image received by the frame processor. Therefore, it can be determined that the frame image processor 106 is configured to receive an input frame image consistent with the total number of pixels of the image displayed by the image display 110. That is, in the embodiments of this application, the frame image processor 106 receives a frame image with a pixel length of L3 and a pixel width of L4.

[0034] It should be understood that the structure and function of the frame image processor 106 are well known to those skilled in the art. Further details will not be provided here. It is also well known to those skilled in the art that the frame image processor 106 includes frame image pipelines 1060 (also known as pipelines in English), and that these pipelines 1060 impose limitations or limits on the pixel length and pixel width of the processed frame images; these limitations will not be described further here. As is known to those skilled in the art, the frame image processor 106 can be configured to perform operations such as rendering on the received frame images via the frame image pipelines 1060. This description is only provided for clarity as it is known to those skilled in the art. As an example, the frame image processor 106 can be a GPU or a CPU. More specifically, the GPU can be a discrete graphics card or an integrated graphics card without departing from the scope of this application. Furthermore, as those skilled in the art will understand, in the field of frame image display, frame images generally have a specified total number of pixels, such as 1080P, 2K, 4K, 8K, etc.

[0035] Optionally or additionally, in embodiments of this application, the image display system 1 further includes a parameter collector (not shown), which is communicatively connected to at least one image display 110 and the frame image processor 106 to obtain the pixel length L3 and pixel width L4 of the image to be displayed on the image display, and the length limit L1 and width limit L2 of at least one frame image pipeline 1060 of the frame image processor 106. The parameter collector is optional because, as mentioned above, for each image display 110, the pixel length and pixel width of the frame image it will display are known in advance. Correspondingly, the length limit L1 and width limit L2 of at least one frame image pipeline 1060 are also inherent parameters that can be known in advance. Therefore, in practice, the relevant parameters of the pixel length L3 and pixel width L4 of the image to be displayed and the length limit L1 and width limit L2 of at least one frame image pipeline 1060 of the frame image processor 106 can be known in advance without needing to be determined by the parameter collector.

[0036] In an embodiment of this application, the image display system 1 further includes a frame image segmenter 102, which is communicatively connected to the frame image signal generator 100 and configured to segment the frame image received by the frame image processor 106 based on a predetermined segmentation method according to a length limit L1, a width limit L2, a pixel length L3, and a pixel width L4, such that each segmented frame image portion is within the range defined by the length limit L1 and the width limit L2.

[0037] In embodiments of this application, the image display system further includes a frame image distributor 104, which is communicatively connected between the frame image divider 102 and the frame image processor 106 and is configured to transmit at least some of the frame image portions in combination to at least one frame image pipeline 1060 in a predetermined distribution manner based on a length limit L1 and a width limit L2, wherein the combined size of at least some of the frame image portions is also within the range defined by the length limit L1 and the width limit L2.

[0038] Both frame image segmenter 102 and frame image distributor 104 are common components in the art. Frame image segmenter 102 is configured to segment a frame image in a predetermined segmentation manner, while frame image distributor 104 is configured to transmit at least some of the frame image portions in a predetermined distribution manner to corresponding frame image pipelines in at least one frame image pipeline 1060. The related structures and functions of frame image segmenter 102 and frame image distributor 104 are well known to those skilled in the art, and the predetermined segmentation manner for cutting the frame image and the predetermined distribution manner for combining and distributing the frame image portions can be optionally preset by those skilled in the art without exceeding the scope of their understanding. It should be understood that, in various embodiments of this application, the predetermined distribution manner includes various distribution methods such as translation, flipping, rotation, and combination of the various frame image portions without departing from the scope of this application. It should be understood that the frame image segmenter 102 and frame image allocator 104 used here do not change the original structure of the frame image segmenter and frame image allocator except for the setting of the predetermined mode. Therefore, the specific structural forms of the relevant frame image segmenter 102 and frame image allocator 104 will not be described in detail here to avoid obscuring the focus of this application.

[0039] As previously described, at least some of the frame image portions are communicated to the frame image processor 106 via the frame image distributor 104, and in particular, the corresponding frame image pipeline 1060 performs operations known to those skilled in the art, such as rendering, so as to maximize the processing power of each frame image pipeline and minimize the waste of processing resources of any frame image pipeline.

[0040] In embodiments of this application, the image display system 1 further includes a frame image splitter 108, which is communicatively connected to the frame image processor 106 and, for example, displays each frame image portion correspondingly at a corresponding position on the corresponding image display 110 after receiving each frame image portion that has been processed in combination. As an example, the frame image splitter 108 may optionally be configured to record the desired display position of each frame image portion on the image display 110 based on the segmentation method of the frame image splitter 102 and the allocation method of the frame image allocator 104, and map each processed frame image portion to a corresponding portion or position on the image display 110. The structure and configuration of this frame image splitter (also known as a splitter in English) are well known to those skilled in the art, and therefore will not be described in detail here. It should be noted that the frame image splitter 108, as described above, is able to display the processed and segmented frame image portions correspondingly on an image display, especially on an image display, so that each frame image portion can be accurately displayed in the corresponding area of ​​the image display and thus ultimately display a complete frame image corresponding to the desired total number of pixels (pixel length x pixel width) on the image display.

[0041] As previously described, this method of first dividing the frame image into frame image parts and then collectively allocating at least some, and especially all, of the frame image parts to the frame image processor can maximize the processing resources of each frame image pipeline in the frame image processor. This allows, in some cases, the number of frame image pipelines required to process frame images corresponding to the total number of display pixels of the image display to be saved. As a result, the frame image processor can support as many additional image displays as possible, which is particularly advantageous for applications with multiple oversized screens.

[0042] Figure 3 A schematic diagram illustrating frame image transmission according to a specific embodiment of this application is shown. The following will be combined with... Figure 3 The specific embodiments described in the text describe the arrangement and construction relationship of the various components of the image display system 1 according to the first embodiment.

[0043] In this specific embodiment, the image display is configured, for example, to display a frame image with a pixel length L3 of 7680 and a pixel width L4 of 2160; that is, an oversized (here, overlength) display selected to display a frame image with a length of 7680 pixels and a width of 2160 pixels. In this specific embodiment, it is also envisioned that, for example, the length limit L1 and width limit L2 that each frame image pipeline 1060 can process are 5000 pixels. For a conventional image display system 110, since the pixel length 7680 of the image display 110 is greater than the length limit of 5000 pixels that a single frame image pipeline 1060 can process, the processing of frame images for the image display 110 would occupy two frame image pipelines. If the frame image processor has a limited number of frame image pipelines, for example, four frame image pipelines, then the frame image processor 106 will support the display of at most two oversized frame images with a length of 7680 pixels and a width of 2160 pixels as described above.

[0044] However, in this application Figure 1 In the illustrated embodiment, the combination of frame image segmenter 102, frame image allocator 104, and frame image splitter 108 can significantly solve this problem of excessive occupancy. As those skilled in the art know, the display parameters of the image display 110 are known specifications (pixel length of 7680 and pixel width of 2160), and the length and width limits (both 5000 pixels) that a single frame image pipeline can handle are also known specifications. Therefore, in the embodiments of this application, the parameter collector described above can be omitted; however, it is understood that the relevant parameters of the image display 110 and the frame image pipeline 1060 can be known by means of the parameter collector.

[0045] Therefore, since the frame image generator 100 is communicatively connected to the frame image segmenter, the frame image generated by the frame image generator 100 (with a total pixel count of 7680 pixels in length x 2160 pixels in width, consistent with the total display pixels of the image display) is transmitted to the frame image segmenter 102 and segmented in a predetermined manner, here using a length-average segmentation method, to ensure that each segmented frame image portion is within the length and width limits of the frame image pipeline. As mentioned above, this predetermined segmentation method is determined by those skilled in the art based on the pixel length and pixel width L3, L4 of the frame image displayed on the image display 110 and the length and width limits L1, L2 of the frame image pipeline. That is, the frame image segmenter 102 is configured to segment the frame image received by the frame image processor 106 in a predetermined segmentation method based on the length limit L1, the width limit L2, the pixel length L3, and the pixel width L4. Clearly, as described above, each segmented frame image portion is within 5000 pixels x 5000 pixels (L1 x L2), which in this case means two frame image portions, each 3840 pixels long x 2160 pixels wide. This segmentation method is preset by the operator based on L1, L2, L3, and L4. Of course, those skilled in the art can conceive of other segmentation methods without departing from the scope of this application, such as segmenting into two frame image portions of 5000 pixels long x 2160 pixels wide and 2680 pixels long x 2160 pixels wide; or segmenting into two frame image portions of 5000 pixels long x 2160 pixels wide and 2680 pixels long x 2160 pixels wide; or segmenting into more frame image portions with other pixel totals. No limitation is made here, and these specific or pre-defined segmentation methods are related to the settings of the frame image segmenter 102. However, as will be understood, it is advantageous to segment the frame image as few times as possible, which will be described in detail later.

[0046] When the aforementioned frame image is divided into two equal parts, each 3840 pixels long and 2160 pixels wide, the frame image distributor 104 transmits these two parts side-by-side (i.e., arranged side-by-side along the 3840-pixel length to form a combination of 3840 pixels long and 4320 pixels wide) to at least one frame image pipeline 1060, in this case, a single frame image pipeline. Clearly, the combined size of these two frame image parts in the side-by-side allocation method is also within the range defined by the length limit L1 and the width limit L2. It should be noted that in this embodiment, the allocation method of the two frame image parts is limited by L1 and L2; that is, it is necessary to ensure that the combined size transmitted to the frame image pipeline in the corresponding allocation method does not exceed the limits of the frame image pipeline. Obviously, in this specific embodiment, the 3840-pixel length and 4320-pixel width meet the relevant limitations. It is important to understand that this predetermined allocation method, here referring to an aligned side-by-side allocation, is pre-set by the operator based on L1 and L2 so that the combined size of those portions of the frame image segment transmitted to the corresponding frame image pipeline is within the range defined by the length limit L1 and the width limit L2. This predetermined allocation method may also be referred to as a predetermined distribution method in some cases. Obviously, the above predetermined allocation method is merely exemplary and not limiting. As another example, although not shown, it is conceivable to combine the first frame image segment and the second frame image segment of the two frame image segments in a side-by-side but not aligned allocation method. For example, the first and second frame image segments are side-by-side, but the first pixel of the first frame image segment in the length direction and the first pixel of the second frame image segment in the length direction are not aligned with each other but are offset to a certain extent. Obviously, this predetermined allocation method is feasible, as long as it ensures that the combined size is within the range defined by the length limit L1 and the width limit L2. Clearly, a simpler allocation method is more conducive to the combined transmission of the frame image segments.

[0047] Clearly, the frame image portions combined in this way by the frame image distributor 104 only need to occupy one frame image pipeline 1060 to complete the rendering and other operations of the entire frame image, without occupying an additional frame image pipeline, thereby saving frame image pipelines to support other image displays.

[0048] The combined frame image portion processed by the frame image pipeline 1060 in the frame image processor 106, in this specific embodiment of the application, that is, two frame image portions processed in the form of a length of 3840 pixels and a width of 4320 pixels, are transmitted to the frame image splitter 108. The frame image splitter 108 can display the two frame image portions correspondingly at the desired or expected positions on a single image display 110, so that the image display can display the desired final frame image.

[0049] Optionally, the frame image splitter 108 can, for example, reversely determine the actual position of each frame image portion in the complete frame image based on a predetermined segmentation method and a predetermined allocation method of the frame image. Alternatively, the frame image splitter can identify the determined position of each frame image portion in the complete frame image based on additional fields added to each frame image portion during frame image segmentation and allocation, and display the corresponding frame image portion at the appropriate position based on that position to achieve display of the complete frame image. For embodiments that add additional fields, for example, an identification field can be added at the segmentation boundary, and additional fields indicating displacement can be added when moving frame image portions in the predetermined allocation method to ensure the identification and repositioning of frame image positions. In any case, it is obvious that fewer frame image portions (fewer segments) and a simpler allocation method help the frame image splitter to accurately and quickly position the corresponding frame image portion at a predetermined position on the image display.

[0050] It should be noted that the function of the frame image splitter 108 in displaying the corresponding frame image portion at a predetermined position on the image display 110 is well known to those skilled in the art, and its structure will not be described in detail here. Obviously, based on different predetermined segmentation and predetermined allocation methods, there is a possibility of adjusting some setting parameters of the frame image splitter 108 accordingly. These adjustments obviously do not lead to structural changes or reconstruction of the frame image splitter 108.

[0051] In short, for a frame image with a pixel length L3 of 7680 and a pixel width L4 of 2160, the frame image segmenter 102 divides it into two frame image parts with a pixel length of 3840 and a pixel width of 2160 in a length-average manner. Then, the frame image distributor 104 transmits the two frame image parts in a combined manner in an aligned and side-by-side distribution manner, that is, the combined frame image part with a pixel length of 3840 and a pixel width of 4320 is transmitted to the single frame image pipeline 1060. The processed combined frame image part is transmitted to the frame image splitter 108, and the image splitter 108 identifies each frame image part and displays it respectively at the appropriate or corresponding position on the image display 110 to display the complete frame image, that is, to display the frame image with a pixel length L3 of 7680 and a pixel width L4 of 2160.

[0052] It should be noted that although the functions of each module or component have been described, their structure and construction are known to those skilled in the art and have been omitted. Even though the functions of each module or component have been described here, these functions are all well-known and can be clearly understood by those skilled in the art.

[0053] Figure 2 A schematic diagram of the structure of an image display system 1 according to a second embodiment of this application is shown. Figure 1 Compared to the first embodiment shown, this image display system further includes a parallel-to-serial converter 112 and a serial-to-parallel converter 114 disposed between the frame image processor 106 and the frame image splitter 108. As those skilled in the art will understand, the combined multiple frame image portions processed by the frame image processor 106 are essentially parallel signals of the individual frame image portions. Obviously, the more frame image portions there are, the more lines are required to transmit each frame image portion, which is detrimental to line simplification. In this case, the introduction of the parallel-to-serial converter 112 and the serial-to-parallel converter 114, such as Ser-Des, enables the conversion of the parallel signals of the multiple frame image portions into serial signals of the multiple frame image portion signals to reduce line occupation during signal transmission. Then, before being displayed separately by the frame image splitter 108, the corresponding serial signals are decomposed into parallel signals of the corresponding multiple frame image portions to facilitate the operation of the frame image splitter 108. It should be understood that the parallel-to-serial converter 112 and the serial-to-parallel converter 114 are well known to those skilled in the art, and their structure and construction will not be described in detail here.

[0054] It is conceivable that at least one of the frame image splitter 102 and the frame image allocator 114 can be integrated into the frame image processor 106 without departing from the scope of this application. In this case, the circuitry of the corresponding frame image splitter 102 and frame image allocator 104 would need to be merged into the frame image processor 106. Although such integration would change the external shape of the image display system 1, it is foreseeable that the corresponding circuitry of each module would still be preserved. Similarly, alternatively, the frame image splitter 108 can be integrated with the serial-to-parallel converter 114 as a single component without departing from the scope of this application.

[0055] Of course, the frame image splitter 108 can be integrated into the associated image display 110 without departing from the scope of this application.

[0056] Optionally, the frame image processor 106 transmits the processed combined frame image portions in the form of a DP signal or an HDMI signal. Similarly, the frame image splitter 108 displays each frame image portion at the corresponding position on the image display in the form of a DP signal or an HDMI signal.

[0057] As an example, and optionally, in embodiments of this application, the image display is, for example, an image display for a vehicle. Preferably, the image display is an oversized display or an oversized screen.

[0058] Although embodiments of this application have been described in detail above with reference to the accompanying drawings, those skilled in the art can make various modifications or substitutions to the above embodiments based on the teachings of this application without departing from the scope of the application.

Claims

1. An image display system, characterized in that, The image display system includes a frame image signal generator, a frame image splitter, a frame image distributor, a frame image processor, a frame image splitter, and at least one image display that are sequentially and communicatively connected. The frame image signal generator is configured to generate a frame image to be displayed on the at least one image display. The at least one image display is configured to display a frame image with a pixel length of L3 and a pixel width of L4; The frame image processor is configured with at least one frame image pipeline, which is configured to support frame images with a length limit of L1 pixels and a width limit of L2 pixels. The frame image segmenter is communicatively connected to the frame image signal generator and is configured to segment the frame image to be transmitted to the frame image processor based on the length limit L1, the width limit L2, the pixel length L3, and the pixel width L4 in a predetermined segmentation manner, such that each resulting frame image portion is within the range defined by the length limit L1 and the width limit L2. The frame image allocator is communicatively connected between the frame image segmenter and the frame image processor and is configured to transmit at least some of the frame image portions in combination to the at least one frame image pipeline in a predetermined allocation manner based on the length limit L1 and the width limit L2, wherein the combined dimensions of at least some of the frame image portions are within the range defined by the length limit L1 and the width limit L2; and The frame image splitter is communicatively connected to the frame image processor and displays each of the processed combined frame image portions at a corresponding position on the at least one image display.

2. The image display system according to claim 1, characterized in that, The image display system further includes a parallel-to-serial converter and a serial-to-parallel converter disposed between the frame image processor and the frame image splitter.

3. The image display system according to claim 1 or 2, characterized in that, The at least one image display is configured to display a frame image with a pixel length L3 of 7680 and a pixel width L4 of 2160, and the length limit L1 and width limit L2 of the at least one frame image pipeline are 5000 pixels and 5000 pixels respectively.

4. The image display system according to claim 3, characterized in that, The frame image segmenter divides the frame image from the frame image signal generator into two frame image portions, each with a length of 3840 pixels and a width of 2160 pixels, using a length-average segmentation method, to obtain two frame image portions, each with a length of 3840 pixels and a width of 2160 pixels.

5. The image display system according to claim 4, characterized in that, The frame image distributor transmits the two frame image portions in a combined manner to the at least one frame image pipeline in an aligned and side-by-side distribution to obtain a combined frame image portion with a pixel length of 3840 and a loudness width of 4320.

6. The image display system according to claim 5, characterized in that, The frame image splitter is configured to determine the actual position of each frame image portion within the complete frame image based on the segmentation and allocation methods of the frame image.

7. The image display system according to claim 1, characterized in that, At least one of the frame image segmenter and the frame image allocator is integrated into the frame image processor.

8. The image display system according to claim 1, characterized in that, The frame image splitter is integrated into a serial-to-parallel converter; or the frame image splitter is integrated into the at least one image display.

9. The image display system according to claim 1, characterized in that, The frame image processor transmits the processed combined frame image portions in the form of DP signals or HDMI signals; and / or, the frame image splitter displays each of the frame image portions at a corresponding position on the at least one image display in the form of DP signals or HDMI signals.

10. The image display system according to claim 1, characterized in that, The image display is a vehicle image display, and / or the image display is an oversized display.

Images