High short circuit protection design device

Abstract

A high-short-circuit protection design device relates to the technical field of semiconductors. Comprising a Sub layer; the top corner of the Drift layer is provided with a pair of etching parts which are of a right trapezoid structure, and the two sides of the top of the Drift layer form an inclined plane; a pair of P-body regions are arranged and extend inwards from the outer side surface of the top of the Drift layer; the NP region extends downwards from the top surface of the P-body region; the PP area extends inwards from the side surface of the P-body area; the PP region is connected with the NP region; the gate oxide layer is arranged on the top surfaces of the Drift layer, the P-body region and the NP region; the Poly layer is arranged on the top surface of the gate oxide layer; when the device works in a saturation region, a deeper P-type junction and a depletion layer generated by a Drift layer can block current, so that the short-circuit endurance capability of the device is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor, especially relates to high short circuit protection device. BACKGROUND

[0002] In the field of power electronics, voltage-controlled power switching devices are applied in various system scenarios and are the most important power components. For a long time, voltage-controlled switching devices are mainly Si-based devices, such as Si MOSFET, Si IGBT, and Si FET, which is due to the high reserves, easy access of Si raw materials, and the stable and mature process and performance of Si devices. However, with the continuous development of society, Si-based devices are increasingly unable to meet the needs of the rapidly developing power electronics field, so researchers have begun to develop new raw materials to produce higher performance devices. The third-generation wide-bandgap semiconductor power device represented by SiC MOSFET is considered to be the key product in the future in high-voltage, high-temperature, and high-frequency fields due to its excellent performance.

[0003] SiC MOSFET has the advantages of MOSFET unipolar structure and high physical performance of SiC, so it has good performance in both static and dynamic aspects, and can achieve higher efficiency in the system. Although SiC MOSFET has more advantages than Si-based devices, the interface state density of the gate oxide layer of SiC MOSFET is large and has many defects, so there is a risk of failure during use. At the same time, the poor short circuit resistance of SiC MOSFET also easily causes short circuit failure of the tube. Therefore, SiC MOSFET has significant long-term use problems and still needs to be optimized and improved. SUMMARY

[0004] To solve the above problems, the utility model provides a high short circuit protection device that improves the protection of the gate oxide layer of SiC MOSFET, reduces the failure risk of the device gate oxide layer, and improves the short circuit resistance of the device when it works in the saturation region.

[0005] The technical scheme of the utility model is:

[0006] The high short circuit protection device comprises:

[0007] a Sub layer;

[0008] a Drift layer having a pair of etching parts in a right-angle trapezoidal structure, and the top of the Drift layer has a slope on both sides;

[0009] a P-body region having a pair of extensions from the top of the Drift layer to the inside;

[0010] NP region, extending downward from the top surface of the P-body region;

[0011] PP region, extending inward from the side surface of the P-body region; the PP region is connected with the NP region;

[0012] gate oxide layer, disposed on the top surface of the Drift layer, P-body region and NP region;

[0013] Poly layer, disposed on the top surface of the gate oxide layer;

[0014] isolation medium layer, disposed on the top surface of the Poly layer, and extending downward on the side to connect with the NP region;

[0015] ohmic contact alloy layer, disposed on the outer side surface of the PP region, and connected with the isolation medium layer on the top;

[0016] front electrode metal layer, disposed on the top of the device.

[0017] Specifically, the Sub layer is N-type, and the thickness is 100-450um.

[0018] Specifically, the P-body region is 0.6-2um deep.

[0019] Specifically, the NP region is 0.3-1.2um deep.

[0020] Specifically, the PP region is 0.3-1.5um deep.

[0021] The utility model relates to a plane type SiC MOSFET device, through etching at the top corner of Drift layer, make its top section appear trapezoidal structure, then through ion implantation and form P type knot on the surface of inverted trapezoidal groove, realize deeper P type knot structure, and deeper P type knot is better for the gate oxide layer protection of SiC MOSFET device, reduce the failure risk of device gate oxide layer, and when the device works in saturation region, deeper P type knot and the depletion layer generated by Drift layer also hinder the current, thereby improve the short circuit resistance of device. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 It is the structure schematic diagram of the utility model step S100;

[0023] Figure 2 It is the structure schematic diagram of the utility model step S200;

[0024] Figure 3 It is the structure schematic diagram of the utility model step S300;

[0025] Figure 4 is the structural schematic diagram of step S400 of the utility model;

[0026] Figure 5 is the structural schematic diagram of step S500 of the utility model;

[0027] Figure 6 is the structural schematic diagram of step S600 of the utility model;

[0028] Figure 7 is the structural schematic diagram of step S700 of the utility model;

[0029] Figure 8 is the structural schematic diagram of step S800 of the utility model;

[0030] Figure 9 is the structural schematic diagram of step S900 of the utility model;

[0031] Figure 10 is the structural schematic diagram of step S1000 of the utility model;

[0032] In the figure, 1 is a Sub layer, 2 is a Drift layer, 3 is a P-body region, 4 is an NP region, 5 is a PP region, 6 is a gate oxide layer, 7 is a Poly layer, 8 is an isolation dielectric layer, 9 is an ohmic contact alloy layer, and 10 is a front electrode metal layer. DETAILED DESCRIPTION

[0033] The utility model will be explained in detail in combination with specific actual cases. The examples of the embodiments are shown in the drawings, and the illustrative embodiments of the utility model and their explanations are only used to explain the utility model and not as a limitation on the utility model.

[0034] High short-circuit protection device, including the following steps:

[0035] S100, the top surface of Sub layer 1 is formed by epitaxial deposition Drift layer 2;

[0036] The conductive type of Sub layer 1 in step S100 is N type, the thickness is 100um-450um, and the doping concentration is 1E19-3E19cm -2 , the conductive type of Drift layer 2 is N type, the thickness is 5um-15um, and the doping concentration is 5E15-5E16cm -2 .

[0037] S200, the top surface of Drift layer 2 is formed by etching downward, and the top of Drift layer 2 is formed into a trapezoidal structure;

[0038] In step S200, the depth of etching vertically downward from the top surface of the Drift layer 2 is 2-6 μm.

[0039] In step S300, the P-body region 3 is formed by Al ion implantation on the top of the Drift layer 2.

[0040] In step S300, the depth of implantation of the P-body region 3 is 0.6-2 μm, and the doping concentration is 1E17-3E18 cm -2 .

[0041] In step S400, the NP region 4 is formed by N ion implantation on the top surface of the P-body region 3.

[0042] In step S400, the depth of implantation of the NP region 4 is 0.3-1.2 μm, and the doping concentration is 1E18-3E19 cm -2 .

[0043] In step S500, the PP region 5 is formed by Al ion implantation on the P-body region 3, and then all the implanted regions are activated by high-temperature annealing.

[0044] In step S500, the depth of implantation of the PP region 5 is 0.3-1.5 μm, and the doping concentration is 1E18-3E19 cm -2 .

[0045] In step S600, the gate oxide layer 6 is formed by dry oxygen oxidation growth on the top surface of the Drift layer 2, the P-body region 3 and the NP region 4.

[0046] In step S600, the thickness of the gate oxide layer 6 is 40-60 nm.

[0047] In step S700, the Poly layer 7 is formed by polycrystalline silicon deposition on the top surface of the gate oxide layer 6.

[0048] In step S800, the isolation medium layer 8 is formed by oxide deposition on the top surface of the NP region 4 and the Poly layer 7.

[0049] In step S900, the ohmic contact alloy layer 9 is formed by Ni metal sputtering or deposition and then thermal annealing on the top surface of the NP region 4 and the PP region 5.

[0050] In step S900, the thickness of the Ni metal is 0.3-1 μm.

[0051] In step S1000, the front electrode metal layer 10 is formed by Ti and AlCu metal sputtering on the top surface of the isolation medium layer 8 and the ohmic contact alloy layer 9.

[0052] In step S1000, the thickness of the Ti metal is 0.1-0.6 μm, and the thickness of the AlCu metal is 2-5 μm.

[0053] A high short circuit protection device, comprising:

[0054] Sub layer 1;

[0055] Drift layer 2, top corner is provided with a pair of etching parts in right-angled trapezoidal structure, and the top two sides of the Drift layer 2 are provided with a slope;

[0056] P-body region 3, provided with a pair of extending from the top outer side of the Drift layer 2 to the inside; a pair of the P-body region 3 is provided with a spacing between the top;

[0057] NP region 4, extending downward from the top surface of the P-body region 3;

[0058] PP region 5, extending inward from the side surface of the P-body region 3, and provided with a spacing between the inner side surface of the P-body region 3; the PP region 5 is connected with the NP region 4;

[0059] Gate oxide layer 6, provided on the top surface of the Drift layer 2, the P-body region 3 and the NP region 4;

[0060] Poly layer 7, provided on the top surface of the gate oxide layer 6;

[0061] Isolation medium layer 8, provided on the top surface of the Poly layer 7, and extending downward to connect with the NP region 4;

[0062] Ohmic contact alloy layer 9, provided on the outer side surface of the PP region 5, and connected with the isolation medium layer 8 at the top;

[0063] Front electrode metal layer 10, provided on the top of the device.

[0064] The bottom of the front electrode metal layer 10 is connected with the ohmic contact alloy layer 9 and the isolation medium layer 8 respectively.

[0065] Because SiC contains C element, interface state density in gate oxide layer is large, defects are many, breakdown failure is easy to occur in use process, thereby affecting safe use. And short circuit resistance of SiC MOSFET is also poor, about 3us, if system design is improper in use process, breakdown failure is also easy to occur due to short circuit problem. The utility model discloses a plane type SiC MOSFET device, through etching out the groove of the section being right trapezoid structure on the Drift layer, then forming P type knot on the groove surface through ion implantation, deeper P type knot structure is realized. The benefit brought by this design is that deeper P type knot is better for the protection of gate oxide layer of SiC MOSFET device, can reduce the failure risk of device gate oxide layer to some extent, and when the device works in saturation region, the depletion layer generated by deeper P type knot and Drift layer will also hinder current, thereby improving the short circuit resistance of the device.

Claims

1. A high short circuit protection device, characterized in that, Comprise: Sub layer (1); Drift layer (2), the top corner is provided with a pair of etching parts in right-angled trapezoidal structure, the top two sides of the Drift layer (2) are inclined surfaces; P-body region (3), provided with a pair, from the top outer side of the Drift layer (2) extends inwardly; NP region (4), from the top surface of the P-body region (3) extends downwardly; PP region (5), from the side surface of the P-body region (3) extends inwardly; the PP region (5) is connected with the NP region (4); Gate oxide layer (6), arranged on the top surface of the Drift layer (2), the P-body region (3) and the NP region (4); Poly layer (7), arranged on the top surface of the gate oxide layer (6); Isolation dielectric layer (8), arranged on the top surface of the Poly layer (7), and the side portion extends downwardly and is connected with the NP region (4); Ohmic contact alloy layer (9), arranged on the outer side surface of the PP region (5), and the top portion is connected with the isolation dielectric layer (8); Front electrode metal layer (10), arranged on the top portion of the device.

2. The high short circuit protection design component of claim 1, wherein, The conductive type of the Sub layer (1) is N type, and the thickness is 100um-450um.

3. The high short circuit protection design component of claim 1, wherein, The depth of the P-body region (3) is 0.6um-2um.

4. The high short circuit protection design component of claim 1, wherein, The depth of the NP region (4) is 0.3um-1.2um.

5. The high short circuit protection design component of claim 1, wherein, The depth of the PP region (5) is 0.3um-1.5um.

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