Watchdog circuit and electronic equipment
By introducing counting and comparison circuits into the watchdog circuit, the problem of the watchdog not being enabled before system startup is solved, enabling real-time monitoring and anomaly handling of the equipment's operating status, and improving the system's stability and security.
Patent Information
- Application Number
- CN202422709964.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-07
- Publication Date
- 2025-12-09
- Estimated Expiration
- 2034-11-07
AI Technical Summary
In conventional circuits, the watchdog function cannot be enabled before system startup, resulting in the inability to monitor the device's operating status and the inability to handle abnormalities such as deadlocks in a timely manner, thus reducing system stability and security.
Design a watchdog circuit including a watchdog chip, a counting circuit and a comparator circuit. The counting circuit records the number of timeouts of the watchdog chip after power-on startup, and the comparator circuit outputs a reset signal when the number of timeouts reaches a preset value, enabling the monitored device to be reset, and ensuring that the system status can be monitored during startup.
It enables real-time monitoring of device operating status during system startup, timely handling of abnormal states, improves system stability and security, and allows configuration of hardware watchdog timeout cycles to adapt to the startup time requirements of different devices.
Smart Images
Figure CN223650992U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of electronic circuits, and particularly relates to a watchdog circuit and an electronic device. BACKGROUND
[0002] At present, the watchdog function in a conventional circuit can only be enabled by software after system startup. During the period from power-on to system startup completion, the watchdog cannot be enabled, and the running state of the device cannot be monitored, so that abnormal states such as deadlock cannot be effectively handled in time, thereby reducing the stability and safety of the system. CONTENT OF THE UTILITY MODEL
[0003] In view of the above problems, the application provides a watchdog circuit and an electronic device, aiming to solve the problem that the watchdog cannot be enabled during the period from power-on to system startup completion in a conventional circuit, and the running state cannot be monitored.
[0004] In a first aspect, an embodiment of the application provides a watchdog circuit, comprising:
[0005] a watchdog chip, an input end of the watchdog chip being connected with an output end of a monitored device,
[0006] a counting circuit, an input end of the counting circuit being connected with an output end of the watchdog chip, the counting circuit being configured to record a timeout number of the output end of the watchdog chip after first power-on startup and watchdog chip startup, and output a corresponding counting signal according to the timeout number;
[0007] a comparison circuit, the comparison circuit being connected with an output end of the counting circuit, a preset counting signal and a reset end of the monitored device, the comparison circuit being configured to output a reset signal in a case where the counting signal is greater than or equal to the preset counting signal, the reset signal being used for enabling the monitored device to reset.
[0008] In the technical scheme of the embodiment of the application, the watchdog circuit is configured with the counting circuit and the comparison circuit based on the watchdog chip to constitute the entire circuit. The counting circuit monitors the timeout number of the output end of the watchdog chip after first power-on startup and watchdog chip startup, and outputs a corresponding counting signal according to the timeout number. The comparison circuit outputs a reset signal to enable the monitored device to reset when the counting signal is not lower than the preset counting signal. As a result, during the period from power-on to system startup completion, even if the watchdog chip cannot be directly enabled, the running state of the monitored device can be monitored, and abnormal states such as deadlock can also be effectively handled in time, thereby improving the stability and safety of the system. Meanwhile, after the watchdog chip is started, the running state of the monitored device can still be monitored. Moreover, since the preset counting signal is a preset value, the hardware watchdog timeout can be adjusted.
[0009] In some embodiments, the output of the counting circuit includes a plurality of sub-outputs, the counting circuit is configured to change the level state of the output level of one of the plurality of sub-outputs each time the output of the watchdog chip is preset time-out, and the plurality of sub-outputs are arranged in a first direction so that each output level constitutes a counting signal.
[0010] In the technical scheme of the embodiments of the present application, the counting circuit records each time-out of the output of the watchdog chip by using a plurality of sub-outputs, and records the number of time-outs by using a digital signal, and the time-out recording result is intuitive.
[0011] In some embodiments, the comparison circuit includes a plurality of first inputs and a plurality of second inputs, the plurality of first inputs are connected to the plurality of sub-outputs of the counting circuit one by one, and the plurality of second inputs are respectively used to connect a plurality of preset state input levels in the first direction, the plurality of preset state input levels constitute a preset digital signal.
[0012] In the technical scheme of the embodiments of the present application, the comparison circuit configures a preset digital signal by using a plurality of second inputs, compares the counting signal of the plurality of sub-outputs respectively, and is simple and adjustable, so that the watchdog circuit is applicable.
[0013] In some embodiments, the voltage configuration circuit is further connected to the plurality of second inputs of the comparison circuit, and the voltage configuration circuit is used to configure the level state of each input level.
[0014] In the technical scheme of the embodiments of the present application, the level state of the input level of the plurality of second inputs of the comparison circuit is configured by setting a voltage configuration circuit, so that the size of the preset digital signal is configured, that is, the number of time-outs or the time-out duration of the reset of the monitored device can be freely configured and controlled, which is convenient and simple.
[0015] In some embodiments, the counting circuit includes n counting components arranged in a first direction and n-2 first logic gates, where n is a natural number greater than or equal to 3.
[0016] The first input end of the first counting component is connected to the first level, the first input end of the second counting component is connected to the output end of the first counting component, and the first input end of each counting component is connected to the first input end and the output end of the previous counting component through a first logic gate from the third counting component.
[0017] The second input end of each counting component is commonly connected to the output end of the watchdog chip.
[0018] The output end of each counting component further constitutes a plurality of sub-outputs of the counting circuit.
[0019] The technical scheme of the embodiment of the application provides a counting circuit composed of discrete devices, the counting circuit can configure the number of counting components according to requirements, thereby configuring the counting period of a counting signal, and can cooperate with a pre-designed counting signal of a configurable size, and can freely configure the timeout times or timeout duration of resetting a monitored device, which is convenient and simple.
[0020] In some embodiments, the counting component comprises a T flip-flop or a JK flip-flop.
[0021] The input end, the clock end and the output end of the T flip-flop respectively constitute the first input end, the second input end and the output end of the counting component.
[0022] The two input ends of the JK flip-flop are commonly connected to constitute the first input end of the counting component, and the clock end and the output end of the JK flip-flop respectively constitute the second input end and the output end of the counting component.
[0023] In the technical scheme of the embodiment of the application, the implementation mode of the counting component is provided, which comprises a T flip-flop or a JK flip-flop, and in other embodiments, other flip-flops such as a D flip-flop or an RS flip-flop are used to implement the counting function.
[0024] In some embodiments, the first logic gate comprises an AND gate circuit, the first input end and the second input end of the AND gate circuit are respectively connected to the first input end and the output end of the previous counting component, and the output end of the AND gate circuit is connected to the first input end of the current counting component.
[0025] In the technical scheme of the embodiment of the application, the counting circuit uses a logic gate circuit, which is built by flip-flops and basic logic gates, and has a simple and reliable structure.
[0026] In some embodiments, the comparison circuit comprises n first comparison components and a second comparison component arranged in a first direction.
[0027] The first input end of each first comparison component respectively constitutes the first input end of the comparison circuit, the second input end of each first comparison component respectively constitutes the second input end of the comparison circuit, and the first comparison component is configured to output a second level in the case that the level states of the input levels received at the first input end and the second input end are the same.
[0028] Each input end of the second comparison component is connected to the output end of each first comparison component in one-to-one correspondence, and the output end of the second comparison component is connected to the reset end of the monitored device, and the second comparison component outputs a reset signal when the second level is received at each input end.
[0029] In the technical scheme of the embodiment of the application, an implementation manner of a comparison circuit is provided, in the embodiment, the output of each sub-output end of a counting circuit is compared individually by a single first comparison component, and then a second comparison component confirms whether a counting signal reaches a preset design signal according to multiple comparison results, and the comparison circuit has clear logic and good reliability.
[0030] In some embodiments, the first comparison component comprises an exclusive-OR gate circuit, two input ends of the exclusive-OR gate circuit constitute a first input end and a second input end of the first comparison component respectively, and an output end of the exclusive-OR gate circuit constitutes an output end of the first comparison component.
[0031] In the technical scheme of the embodiment of the application, an implementation manner of a simple and reliable first comparison component is provided.
[0032] In some embodiments, the second comparison component comprises n-1 OR gate circuits.
[0033] When n=3, two input ends of a first OR gate circuit are connected to an output end of a first first comparison component and an output end of a second first comparison component respectively, two input ends of a second OR gate circuit are connected to an output end of the first OR gate circuit and an output end of a third first comparison component respectively, and an output end of the second OR gate circuit serves as an output end of the comparison circuit.
[0034] When n=4, two input ends of a first OR gate circuit are connected to an output end of a first first comparison component and an output end of a second first comparison component respectively, two input ends of a second OR gate circuit are connected to an output end of a third first comparison component and an output end of a fourth first comparison component respectively, two input ends of a third OR gate circuit are connected to output ends of the first and second OR gate circuits respectively, and an output end of the third OR gate circuit serves as an output end of the comparison circuit.
[0035] When n is an even number and n is greater than or equal to 6, the n-1 OR gate circuits are divided into n / 2 layers, a first layer of OR gate circuits comprises n / 2 OR gate circuits, each input end of the first layer of OR gate circuits constitutes an input end of the second comparison component, an input end of an i-th layer of OR gate circuits is connected to an output end of an (i-1)-th layer, an (i-2)-th layer or the first layer of OR gate circuits, a last layer of OR gate circuits comprises one OR gate circuit, each input end of the last layer of OR gate circuits is connected to output ends of an (n / 2-1)-th layer or an (n / 2-2)-th layer of OR gate circuits, and an output end of the last layer of OR gate circuits constitutes an output end of the second comparison component, i=2, 3, …, n / 2-1.
[0036] When n is odd and n is greater than or equal to 5, the n-1 or gate circuits are divided into (n+1) / 2 layers, the first layer of or gate circuits includes (n-2) / 2 or gate circuits, each input terminal of the first layer of or gate circuits respectively constitutes the 1st to the (n-1)th input terminal of the second comparison component, the input terminal of the or gate circuit of the jth layer is connected with the output terminal of the or gate circuit of the (j-1)th layer, the (j-2)th layer or the first layer, the or gate circuit of the last layer includes 1 or gate circuit, the first input terminal of the or gate circuit of the last layer is connected with the output terminal of the or gate circuit of the (n+1) / 2-1 layer, the second input terminal of the or gate circuit of the last layer constitutes the nth input terminal of the second comparison component, and the output terminal of the or gate circuit of the last layer constitutes the output terminal of the second comparison component, j=2, 3, …, (n+1) / 2-1.
[0037] In the technical scheme of the embodiment of the application, some simple and reliable implementation manners of the second comparison component are provided, and the number of or gate circuits can be configured according to the number of the first comparison components to match the corresponding pre-designed time signals.
[0038] In some embodiments, the second comparison component includes one or gate circuit, each input terminal of the or gate circuit is connected with the output terminal of each first comparison component, and the output of the or gate circuit constitutes the output terminal of the second comparison component.
[0039] In the technical scheme of the embodiment of the application, a simple and reliable implementation manner of the second comparison component is provided, and the number of input terminals of the or gate circuit can be configured according to the number of the first comparison components to match the corresponding pre-designed time signals.
[0040] In some embodiments, the digital-to-analog conversion circuit is further connected with the plurality of sub-output terminals of the counting circuit, and is configured to convert the counting signal of the output level arranged in the first direction into an analog counting signal.
[0041] In the technical scheme of the embodiment of the application, another embodiment of the watchdog circuit is provided, the counting signal of the digital signal is converted into the counting signal of the analog signal, and the setting of the comparison circuit and the configuration of the pre-designed digital signal are facilitated.
[0042] In some embodiments, the comparison circuit includes a comparison device, a first input terminal of the comparison device is connected with the output terminal of the digital-to-analog conversion circuit, a second input terminal of the comparison device is connected with a voltage signal representing the pre-designed digital signal, and an output terminal of the comparison device is connected with a reset terminal of the monitored device.
[0043] In the technical scheme of the embodiment of the application, based on the counting signal of the analog signal, a simpler and more reliable comparison circuit is set, the devices are less, the size of the pre-designed digital signal is easier to configure, and the software or interface resources occupied are less.
[0044] In some embodiments, the voltage configuration circuit is further connected to the second input terminal of the comparison circuit, and the voltage configuration circuit is configured to configure the voltage value of the voltage signal.
[0045] In the technical solution of the embodiments of the present application, the comparison circuit based on a single comparison device only needs to provide one voltage signal to configure the pre-designed count signal, which is simple, reliable and more accurate.
[0046] In some embodiments, the voltage configuration circuit comprises a power-on start state and a normal working state, the voltage configuration circuit is further configured to configure the pre-designed count signal at a first voltage in the power-on start state, and the voltage configuration circuit is further configured to configure the pre-designed count signal at a second voltage in the normal working state.
[0047] The first voltage corresponds to a timeout number greater than a timeout number corresponding to the second voltage.
[0048] In the technical solution of the embodiments of the present application, the timeout period can be configured, for example, the watchdog chip can be enabled at power-on, the timeout time is set to the start time of the monitored device, and the timeout time is set to be shorter after the monitored device is started, which meets the safety of monitoring at power-on and the timeliness of processing problems during software running.
[0049] In some embodiments, the voltage configuration circuit comprises a power supply circuit or a control chip, the power supply circuit is connected to the second input terminal of the comparison circuit, and the control chip is connected to the second input terminal of the comparison circuit.
[0050] In the technical solution of the embodiments of the present application, two implementation manners of the voltage configuration circuit are provided.
[0051] In some embodiments, the count circuit further comprises a clear terminal, the clear terminal is connected to the output terminal of the comparison circuit or the input terminal of the watchdog chip.
[0052] In the technical solution of the embodiments of the present application, when the clear terminal of the count circuit is connected to the output terminal of the comparison circuit, the count circuit is cleared by using a reset signal, and the count circuit can realize continuous or discontinuous timeout count recording; when the clear terminal of the count circuit is connected to the input terminal of the watchdog chip, the count circuit is cleared by using a dog feeding signal of the watchdog chip, and the count circuit can realize continuous timeout count recording.
[0053] In some embodiments, the count circuit and the comparison circuit are arranged in a field programmable gate array.
[0054] In the technical solution of the embodiments of the present application, the count circuit and the comparison circuit can be realized by using a logic circuit in a field programmable gate array (FPGA), which has high integration, small occupied area and is conducive to miniaturization.
[0055] In a second aspect, the embodiments of the present application provide an electronic device, comprising a control device and the watchdog circuit as above, an input end of a watchdog chip of the watchdog circuit is connected with an output end of the control device, and an output end of a comparison circuit of the watchdog circuit is connected with a reset end of the control device.
[0056] The above description is only a summary of the technical solutions of the present application. In order to enable one of ordinary skill in the art to better understand the technical means of the present application and implement the same according to the contents of the specification, and in order to enable the above and other purposes, characteristics and advantages of the present application to be more apparent and understandable, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS
[0057] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not meant to limit the present application. Furthermore, the same reference numerals are used throughout the several views that follow. In the drawings:
[0058] Figure 1 Structure schematic diagram of the watchdog circuit provided for some embodiments of the present application;
[0059] Figure 2 Structure schematic diagram of the watchdog circuit provided for some embodiments of the present application;
[0060] Figure 3 Structure schematic diagram of the watchdog circuit provided for some embodiments of the present application;
[0061] Figure 4 Circuit schematic diagram of the watchdog circuit provided for some embodiments of the present application;
[0062] Figure 5 Circuit schematic diagram of the comparison circuit in the watchdog circuit provided for some embodiments of the present application;
[0063] Figure 6 Circuit schematic diagram of the comparison circuit in the watchdog circuit provided for some embodiments of the present application;
[0064] Figure 7 Circuit schematic diagram of the comparison circuit in the watchdog circuit provided for some embodiments of the present application;
[0065] Figure 8 Circuit schematic diagram of the watchdog circuit provided for some embodiments of the present application;
[0066] Figure 9 Structure schematic diagram of the watchdog circuit provided for some embodiments of the present application;
[0067] Figure 10The structure diagram of the watchdog circuit provided for some embodiments of the present application is shown. DETAILED DESCRIPTION
[0068] The embodiments of the technical solutions of the present application will be described in detail below with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present application, and therefore only serve as examples, and cannot limit the protection scope of the present application.
[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs; the terms used herein are only for the purpose of describing specific embodiments of the present application, and are not intended to limit the present application; the terms "include" and "have" and any variations thereof in the specification and claims of the present application and the above description of drawings are intended to cover non-exclusive inclusion.
[0070] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise explicitly and specifically limited.
[0071] In this paper, the reference to "embodiments" means that the specific features, structures or properties described in conjunction with the embodiments can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily mean the same embodiment, nor is it an independent or alternative embodiment to other embodiments. The skilled person in the art explicitly and implicitly understands that the embodiments described herein can be combined with other embodiments.
[0072] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents a "or" relationship between the front and rear associated objects.
[0073] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two), and similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).
[0074] In some cases, during the time from the device being powered on to the system starting, the watchdog chip cannot be enabled, the running state of the device cannot be monitored, and abnormal states such as deadlock cannot be effectively handled in time, thereby reducing the stability and safety of the system. In some other cases, the watchdog chip starts faster than the monitored device, the watchdog chip is enabled as soon as it is powered on, and the monitored device is still in the initialization process and cannot normally and timely provide the watchdog chip with a watchdog feeding signal. The watchdog chip that has timed out will provide a reset signal to the monitored device in the initialization process, so that the monitored device or even the entire device cannot start normally.
[0075] To this end, in view of the problem that the watchdog chip cannot be enabled or the enabled timeout period is less than the device startup time during device startup, the application concept is to set a watchdog circuit that can configure the timeout period (i.e., the interval length of the output reset signal) of the watchdog circuit, so that the device can be monitored during startup and can start smoothly.
[0076] Please refer to Figure 1 Some embodiments of the application provide a watchdog circuit, which comprises a watchdog chip 110, a counting circuit 120, and a comparison circuit 130.
[0077] The input end WDI of the watchdog chip 110 is connected with the output end Out of the monitored device 200; the input end of the counting circuit 120 is connected with the output end WDO of the watchdog chip 110, and the counting circuit 120 is configured to record the number of timeouts of the output end WDO of the watchdog chip 110 after power-on startup and the watchdog chip 110 is started, and output a corresponding counting signal according to the number of timeouts; the comparison circuit 130 is connected with the output end of the counting circuit 120, a preset counting signal Vref, and the reset end Rst of the monitored device 200, and the comparison circuit 130 is configured to output a reset signal in the case that the counting signal is greater than or equal to the preset counting signal Vref, and the reset signal is used to enable the monitored device 200 to reset.
[0078] The input end WDI of the watchdog chip 110 is a watchdog feeding end or a watchdog input end (watchdog timer input, WDI), and the output end WDO of the watchdog chip 110 is a watchdog output end (watchdog timer Output, WDO). The monitored device 200 is, for example, any control chip of an electronic device, such as a microcontroller unit (Microcontroller Unit, MCU), or a single chip microcomputer, or a single chip microcomputer (Single Chip Microcomputer), or a central processing unit (Central Process Unit; CPU), etc.
[0079] It can be understood that the pre-design count signal Vref, i.e., the corresponding timeout period, can be configured by a user, for example, the timeout period can be set to be slightly greater than the starting / initialization time length of the monitored device 200. The timeout period can be set to be a preset number of times of feeding the watchdog or a continuous preset number of times of feeding the watchdog.
[0080] In the technical solution of the embodiment of the application, the watchdog circuit is configured with the counting circuit 120 and the comparison circuit 130 to constitute the entire circuit. After the power-on starting and the watchdog chip 110 starting, the counting circuit 120 monitors the timeout times of the output end WDO of the watchdog chip 110, and outputs a corresponding count signal according to the timeout times. When the count signal is not lower than the pre-design count signal Vref, the comparison circuit 130 outputs a reset signal to enable the monitored device 200 to reset, so that the running state of the monitored device 200 can be monitored during the time from the power-on of the watchdog chip 110, the monitored device 200 and the like to the system starting completion, even if the watchdog chip 110 cannot directly enable, the running state of the monitored device 200 can be monitored, and the abnormal state such as deadlock can be processed in time and effectively, thereby improving the stability and safety of the system. In addition, the pre-design count signal Vref, i.e., the timeout period, can be set to be slightly longer than the starting or initialization time of the monitored device 200, so that the monitored device 200 has sufficient time to complete the starting, so as not to receive the reset signal in advance to reset. At the same time, after the watchdog chip 110 starts, the running state of the monitored device 200 can still be monitored. Moreover, since the pre-design count signal Vref is a preset value, the timeout period of the hardware watchdog can be adjusted.
[0081] Please refer to Figure 2 In some embodiments, the output of the counting circuit 120 includes a plurality of sub-output ends Q1-Qn, and the counting circuit 120 is configured to change the level state of the output level of one of the plurality of sub-output ends Q1-Qn each time the timeout of the output end WDO of the watchdog chip 110 is recorded, and the plurality of sub-output ends Q1-Qn are arranged in a first direction to form the count signal by the output levels.
[0082] For example, the initial level state of the plurality of sub-output ends Q1-Qn of the counting circuit 120 after power-on is all low, i.e., the output value is the digital signal 0000, and the set value of the pre-design time signal is 1000. The counting circuit 120 counts "+1" based on the count signal output at the last time each time the output end WDO of the watchdog chip 110 is recorded. The first direction can be the signal input-to-output direction of the circuit, or the front-to-rear direction of the circuit.
[0083] In the technical solution of the embodiment of the application, the counting circuit 120 records each time the output end WDO of the watchdog chip 110 times out by using the plurality of sub-output ends Q1-Qn, and records the timeout times by using the digital signal, and the timeout recording result is intuitive.
[0084] Please see Figure 2 In some embodiments, the comparison circuit 130 includes a plurality of first input terminals and a plurality of second input terminals. The plurality of first input terminals are respectively connected to a plurality of sub-output terminals Q1 to Qn of the counting circuit 120. The plurality of second input terminals are respectively used to connect to a plurality of preset state input levels IO1 to IOn arranged in a first direction. The plurality of preset state input levels IO1 to IOn constitute a preset counting signal Vref.
[0085] The preset input levels IO1 to IOn can be configured using the power supply circuit, for example, the positive terminal of the power supply output can be configured to a high level and the negative terminal of the power supply output can be configured to a low level; or, the preset states of the input levels IO1 to IOn can be configured using the IO ports of the control chip.
[0086] In the technical solution of this application embodiment, the comparison circuit 130 uses multiple second input terminals configured with preset counting signals Vref, which are compared with the counting signals of multiple sub-output terminals Q1 to Qn respectively. The setup is simple and adjustable, which expands the applicability of the watchdog circuit.
[0087] Please see Figure 3 In some embodiments, the watchdog circuit further includes a voltage configuration circuit 140; the voltage configuration circuit 140 is connected to a plurality of second input terminals of the comparator circuit 130, and the voltage configuration circuit 140 is used to configure the level state of each input level IO1 to IOn.
[0088] The voltage configuration circuit 140 can be implemented using a power supply circuit, such as a power supply chip. If the second input terminal needs to be connected to a low-level signal, it is connected to the negative terminal or ground of the power supply chip. If the second input terminal needs to be connected to a high-level signal, it is connected to the positive terminal of the preset voltage output of the power supply chip, such as 3.3V or 5V output. Alternatively, the voltage configuration circuit 140 can use an integrated control circuit, with each second input terminal connected to an I / O port of the integrated control circuit. The I / O port of the integrated control circuit can be used to directly configure the corresponding second input terminal to a high-level or low-level state.
[0089] In the technical solution of this application embodiment, a voltage configuration circuit 140 is set to configure the input level IO1 to IOn of the multiple second input terminals of the comparison circuit 130, thereby configuring the magnitude of the preset counting signal Vref. In other words, the number of timeouts or the timeout duration for controlling the reset of the monitored device 200 can be freely configured, which is convenient and simple.
[0090] Please see Figure 4In some embodiments, the counting circuit 120 includes n counting components A1-An arranged in a first direction and n-2 first logic gates B1-Bn-2, where n is a natural number greater than or equal to 3. Figure 4 The circuit structure is shown when n=4, where An is A4, Bn-2 is B2, Cn is C4, and Qn is Q4.
[0091] The first input terminal of the first counting component A1 is connected to the first level, the first input terminal of the second counting component A2 is connected to the output terminal of the first counting component A1, and the first input terminals of the counting components A1-An from the third counting component A3 are connected to the first input terminal and the output terminal of the previous counting component A1-An through a first logic gate B1-Bn-2.
[0092] The second input terminals of the counting components A1-An are commonly connected to the output terminal WDO of the watchdog chip 110.
[0093] The output terminals of the counting components A1-An also constitute multiple sub-output terminals Q1-Qn of the counting circuit 120.
[0094] For example, the first level is a high level, which can be provided by the voltage configuration circuit 140 or an IO port of the control chip.
[0095] The counting components A1-An can be used to record a digital counting signal of 3 bits or more, and the number of counting components A1-An can be set by the user according to the design of the counting signal Vref, i.e., the demand for the timeout period. The counting components A1-An are triggered to count by the output terminal WDO of the watchdog chip 110. When the output terminal WDO of the watchdog chip 110 outputs a timeout reset signal, the first counting component A1-An starts recording, i.e., inverts the output (at the same time, the output is output from the sub-output terminals Q1-Qn to the comparison circuit 130) to the second counting component A1-An, the second counting component A1-An receives a timeout reset signal, i.e., inverts the output (at the same time, the output is output from the sub-output terminals to the comparison circuit 130) to the third counting component A1-An, and so on.
[0096] In the technical scheme of the embodiments of the present application, the counting circuit 120 composed of discrete components can configure the number of counting components A1-An according to the demand, thereby configuring the counting period of the counting signal, and can freely configure the timeout number or timeout period of the reset of the monitored device 200 in cooperation with the designable size of the counting signal Vref, which is convenient and simple.
[0097] Please continue to refer to Figure 5 In some embodiments, the counting components A1-An include T flip-flops or JK flip-flops, whereFigure 5 The input end, the clock end and the output end of the T flip-flop constitute the first input end, the second input end and the output end of the counter component A1-An respectively; the two input ends of the JK flip-flop are connected in common to constitute the first input end of the counter component A1-An, and the clock end and the output end of the JK flip-flop constitute the second input end and the output end of the counter component A1-An respectively.
[0098] The input end, the clock end and the output end of the T flip-flop are respectively the T end, the CLK end (or the CP end) and the Q end, the two input ends of the JK flip-flop are respectively the J end and the K end, and the clock end and the output end of the JK flip-flop are respectively the CLK end and the Q end. The J end and the K end are left hanging.
[0099] In the technical scheme of the embodiment, the implementation mode of the counter component A1-An is provided, including the T flip-flop or the JK flip-flop, and in other embodiments, other flip-flops such as the D flip-flop and the RS flip-flop are used to realize the counting function.
[0100] Please continue to refer to Figure 4 In some embodiments, the first logic gate B1-Bn-2 includes an AND gate circuit, the first input end and the second input end of the AND gate circuit are connected to the first input end and the output end of the previous counter component respectively, and the output end of the AND gate circuit is connected to the first input end of the current counter component.
[0101] In the technical scheme of the embodiment, the counting circuit 120 is built by using the logic gate circuit including the flip-flop and the basic logic gate, and the structure is simple and reliable.
[0102] Please continue to refer to Figure 4 In some embodiments, the comparison circuit 130 includes n first comparison components C1-Cn and a second comparison component 131 arranged along a first direction.
[0103] The first input end of each first comparison component C1-Cn constitutes the first input end of the comparison circuit 130, the second input end of each first comparison component C1-Cn constitutes the second input end of the comparison circuit 130, and the first comparison component C1-Cn is configured to output the second level in the case that the input level IO1-IOn of the pre-designed count signal Vref received at the first input end and the second input end is the same.
[0104] Each input end of the second comparison component 131 is connected to the output end of each first comparison component C1-Cn in one-to-one correspondence, the output end of the second comparison component 131 is connected to the reset end Rst of the monitored device 200, and the second comparison component 131 outputs the reset signal when the second level is received at each input end.
[0105] The first comparison components C1-Cn and the second comparison component 131 are, for example, logical gate circuits. The n first comparison components C1-Cn arranged in the first direction are configured to have the second input ends of the comparison circuit 130 arranged in the first direction connected one by one with the plurality of sub-output ends Q1-Qn of the counting circuit 120 arranged in the first direction.
[0106] For example, the second level is a low level, indicating that the counting signal (i.e., the level state of Q1-Qn) is identical to the corresponding digit of the preset counting signal Vref. In particular, all the outputs of the first comparison components C1-Cn are the second level, indicating that the value of the counting signal is identical to the value of the preset counting signal Vref.
[0107] In the technical solution of the embodiment, the implementation of the comparison circuit 130 is provided. In the embodiment, the output of each sub-output end of the counting circuit 120 is compared individually by the single first comparison component C1-Cn, and then the second comparison component 131 confirms whether the counting signal reaches the preset counting signal Vref according to the plurality of comparison results. The comparison circuit 130 has clear logic and good reliability.
[0108] Please continue to refer to Figure 4 In some embodiments, each first comparison component C1-Cn includes an exclusive-OR gate circuit, the two input ends of the exclusive-OR gate circuit are configured as the first input end and the second input end of the first comparison component C1-Cn, and the output end of the exclusive-OR gate circuit is configured as the output end of the first comparison component C1-Cn.
[0109] In the technical solution of the embodiment, a simple and reliable implementation of the first comparison component C1-Cn is provided.
[0110] Please refer to Figure 4 to Figure 6 In some embodiments, the second comparison component 131 includes n-1 OR gate circuits D1-Dn-1.
[0111] Please refer to Figure 5 , Figure 5 The circuit schematic diagram of the comparison circuit 130 in the watchdog circuit when n=3 is shown. When n=3, the two input ends of the first OR gate circuit D1 are connected with the output end of the first first comparison component C1 and the output end of the second first comparison component C2 respectively, the two input ends of the second OR gate circuit D2 are connected with the output end of the first OR gate circuit D1 and the output end of the third first comparison component C3 respectively, and the output end of the second OR gate circuit D2 is configured as the output end of the comparison circuit 130.
[0112] The two input terminals of the first OR gate D1 and the one input terminal of the second OR gate D2 constitute the three second input terminals of the second comparison component 131 respectively, and the output terminal of the second OR gate D2 is connected to the reset terminal Rst of the monitored device 200.
[0113] Please refer to Figure 4 , Figure 4 The circuit schematic diagram of the watchdog circuit when n=4 is shown. When n=4, the two input terminals of the first OR gate D1 are connected to the output terminals of the first and second first comparison components C1 and C2 respectively, the two input terminals of the second OR gate D2 are connected to the output terminals of the third and fourth first comparison components C3 and C4 respectively, the two input terminals of the third OR gate D3 are connected to the output terminals of the first and second OR gates D1 and D2 respectively, and the output terminal of the third OR gate D3 serves as the output terminal of the comparison circuit 130.
[0114] The two input terminals of the first OR gate D1 and the two input terminals of the second OR gate D2 constitute the four second input terminals of the second comparison component 131 respectively, and the output terminal of the third OR gate D3 is connected to the reset terminal Rst of the monitored device 200.
[0115] Please refer to Figure 6 , Figure 6 The circuit schematic diagram of the comparison circuit 130 in the watchdog circuit when n=5 is shown. When n is an odd number and n≥5, the n-1 OR gates D1~Dn-1 are divided into (n+1) / 2 layers, the first layer OR gates D1~Dn-1 include (n-2) / 2 OR gates D1~D(n-2) / 2, the input terminals of the first layer OR gates D1~D(n-2) / 2 constitute the 1st to (n-1)th input terminals of the second comparison component 131 respectively, the input terminals of the OR gate in the jth layer are connected to the output terminals of the OR gates in the (j-1)th, (j-2)th or first layer, the last layer OR gate includes one OR gate D1~Dn-1, the first input terminal of the last layer OR gate is connected to the output terminal of the (n+1) / 2-1 layer OR gate, the second input terminal of the last layer OR gate constitutes the nth input terminal of the second comparison component 131, the output terminal of the last layer OR gate constitutes the output terminal of the second comparison component 131, and j=2, 3, …, (n+1) / 2-1.
[0116] Please refer to Figure 7 , Figure 7The circuit schematic of the comparison circuit 130 in the watchdog circuit when n = 6 is shown. When n is even and n ≥ 6, the n-1 OR gate circuits D1-Dn-1 are divided into n / 2 layers, the first layer of OR gate circuits D1-Dn-1 includes n / 2 OR gate circuits D1-Dn / 2, each input of the first layer of OR gate circuits D1-Dn / 2 forms an input of the second comparison component 131, the input of the OR gate circuit in the i-th layer is connected to the output of the OR gate circuit in the (i-1)-th layer, the (i-2)-th layer or the first layer of OR gate circuits D1-Dn / 2, the last layer of OR gate circuits includes one OR gate circuit Dn-1, each input of the last layer of OR gate circuits is connected to the output of the OR gate circuit in the (n / 2-1)-th layer or the (n / 2-2)-th layer, and the output of the last layer of OR gate circuits forms an output of the second comparison component 131, i = 2, 3, …, n / 2-1.
[0117] In the above embodiments, the OR gate circuits D1-Dn-1 are two-input, single-output OR gate devices or OR gate circuits. As can be seen from the above embodiments of the second comparison component 131, the second comparison component 131 connects each output of the first comparison components C1-Cn to the output of the comparison circuit 130 in the form of an inverted triangle by a plurality of OR gate circuits D1-Dn-1. In the technical solution of the embodiments of the present application, a plurality of simple and reliable embodiments of the second comparison component 131 are provided.
[0118] For example, when n = 4, please refer to Figure 4 When the clock end CLK of each counting component A1-A4 of the counting circuit 120 detects the first falling edge output by the output end WDO of the watchdog chip 110 after power-on, the output end level of the first counting component A1 flips: Q1 changes from 0 to 1, where Q1-Qn also represents the output signal of the counting component A1-A4, and since the input end level of the second to fourth counting components A2-A4 is 0, the output end level does not flip and remains at 0. Therefore, the counting signal Q4-Q1 output by the counting circuit 120 changes from 0000 to 0001. When the clock end CLK of each counting component A1-A4 detects the second falling edge, the output end level of the first and second counting components A1-A2 flips: Q1 changes from 1 to 0 and Q2 changes from 0 to 1, and since the AND gate circuits B1, B2 cause the input end of the third and fourth counting components A3, A4 to be 0, the output end does not flip and remains at 0. Therefore, the counting signal Q4-Q1 output by the counting circuit 120 is 0010. When the clock end CLK of each counting component A1-A4 detects the third falling edge, the output of the first counting component A1 flips: Q1 changes from 0 to 1, and the counting signal Q4-Q1 output by the counting circuit 120 is 0011. In this way, the number of timeouts of the watchdog chip 110 is recorded.
[0119] With the increase of the falling edge, when the count signal outputted by the count circuit 120 is equal to the preset count signal Vref received by the comparison circuit 130, i.e. the input level IO4-IO1:1000, the first comparison components C1-C4 output all 0, or the OR gate circuits D1-D3 output all 0, i.e. the reset signal, so that the monitored device 200 is reset. It can be understood that when n is another number, the working principle of the watchdog circuit in this embodiment is similar, which will not be repeated here.
[0120] Please refer to Figure 8 , Figure 8 The circuit structure of n=4 is shown, wherein An is A4, Bn-2 is B2, Cn is C4, and Qn is Q4. In some embodiments, the second comparison component 131 includes an OR gate circuit D0; each input end of the OR gate circuit D0 is connected with the output end of each first comparison component C1-Cn, and the output end of the OR gate circuit D0 constitutes the output end of the second comparison component 131.
[0121] In this embodiment, the OR gate circuit D0 is a single OR gate device or an OR gate circuit with multiple inputs and single output, and each input end of the OR gate circuit D0 serves as an input end of the second comparison component 131.
[0122] In the technical solution of this embodiment, a simple and reliable implementation of the second comparison component 131 is provided, and the number of input ends of the OR gate circuit D0 can be configured according to the number of the first comparison components C1-Cn to match the corresponding preset count signal Vref.
[0123] Please refer to Figure 9 In some embodiments, the watchdog circuit further includes a digital-to-analog conversion circuit 150 connected with the multiple sub-output ends Q1-Qn of the count circuit 120, and the digital-to-analog conversion circuit 150 is configured to convert the count signal with the output level arranged in the first direction into an analog count signal.
[0124] The digital-to-analog conversion circuit 150 is, for example, a digital-to-analog converter (DAC). In the technical solution of this embodiment, another embodiment of the watchdog circuit is provided, which converts the digital count signal into an analog count signal, and the comparison circuit 130 only needs to receive one count signal outputted by the digital-to-analog conversion circuit 150 and one preset count signal Vref, which facilitates the setting of the comparison circuit 130 and the configuration of the preset count signal Vref.
[0125] Please continue to refer to Figure 9In some embodiments, the comparison circuit 130 comprises a comparison device, a first input terminal of the comparison device is connected to an output terminal of the digital-to-analog conversion circuit 150, a second input terminal of the comparison device is connected to a voltage signal representing the pre-designed digital signal Vref, and an output terminal of the comparison device is connected to a reset terminal Rst of the monitored device 200.
[0126] The comparison device is, for example, a conventional comparator for comparing analog signals, and the voltage signal inputted to the second input terminal of the comparison device is used as a reference signal, and the user can set the value of the voltage signal as needed to set the size of the pre-designed digital signal Vref, thereby setting the timeout period of the watchdog circuit of the embodiments.
[0127] In the technical solution of the embodiments, a simpler and more reliable comparison circuit 130 is set based on the counting signal of the analog signal, the device is less, and it is easier to set the size of the pre-designed digital signal Vref, and the software or interface resources occupied are less.
[0128] Please continue to refer to Figure 9 In some embodiments, another voltage configuration circuit 140 is further provided; the voltage configuration circuit 140 is connected to the second input terminal of the comparison circuit 130, and the voltage configuration circuit 140 is used to configure the voltage value of the voltage signal to set the size of the pre-designed digital signal Vref, thereby setting the timeout period of the watchdog circuit of the embodiments.
[0129] In the technical solution of the embodiments, the comparison circuit 130 based on a single comparison device, and the voltage configuration circuit 140 only needs to provide one voltage signal to configure the pre-designed digital signal Vref, which is simple and reliable, and more accurate.
[0130] Please refer to Figure 3 and Figure 8 In some embodiments, the voltage configuration circuit 140 comprises a power-on start state and a normal working state, the voltage configuration circuit 140 is further used to configure the pre-designed digital signal Vref at a first voltage in the power-on start state, and the voltage configuration circuit 140 is further used to configure the pre-designed digital signal Vref at a second voltage in the normal working state; wherein the timeout number corresponding to the first voltage is greater than the timeout number corresponding to the second voltage.
[0131] In the embodiments shown, the level state of each input level IO1-IO1 is used to represent the first voltage and the second voltage, Figure 3 In the embodiments shown, the pre-designed digital signal Vref of the voltage value is used to represent the first voltage and the second voltage. Figure 8
[0132] It is understandable that the power-on startup state and normal operation state of the voltage configuration circuit 140 are matched to the power-on startup process and normal operation process of the monitored device 200, respectively, enabling configurable timeout periods. Generally, when the power-on startup of the monitored device 200 is relatively long, the value of the preset counting signal Vref can be set larger than that during normal operation. For example, even if the watchdog chip 110 is activated upon power-on, the timeout period can be set to match the startup duration of the monitored device 200. For instance, the timeout period corresponding to a continuous timeout period can be slightly longer than the startup duration of the monitored device 200. After the monitored device 200 starts up, the timeout period can be shortened, satisfying both the security of monitoring upon power-on and the timeliness of handling problems that occur during software operation.
[0133] In some embodiments, the voltage configuration circuit 140 includes a power supply circuit or a control chip, the power supply circuit being connected to the second input terminal of the comparator circuit 130 (see [link]). Figure 4 , Figure 8 The control chip (not shown) is connected to the second input terminal of the comparator circuit 130.
[0134] In the technical solutions of this application embodiment, two implementation methods of the voltage configuration circuit 140 are provided.
[0135] Please see Figure 9 In some embodiments, the counting circuit 120 further includes a clear terminal rst, which is connected to ( Figure 9 (The connection is indicated by a dashed line) The output terminal of the comparator circuit 130 or the input terminal WDI of the watchdog chip 110.
[0136] The clear terminal rst of the counting circuit 120 is, for example, the power supply port or reset port of each flip-flop, or a port that can set the output of each flip-flop to 0.
[0137] When the reset terminal rst of the counting circuit 120 is connected to the output terminal of the comparator circuit 130, when the counting signal reaches the preset counting signal Vref, the counting circuit 120 is reset using the reset signal. The counting circuit 120 can then restart continuous or discontinuous timeout counting and recording, so that the monitored device 200 is reset after a preset number of continuous or discontinuous timeout feedings.
[0138] When the reset terminal rst of the counting circuit 120 is connected to the input terminal WDI of the watchdog chip 110, the counting circuit 120 is reset by feeding the watchdog chip 110, allowing the counting circuit 120 to restart continuous timeout counting. Thus, the monitored device 200 resets after a preset number of consecutive timeout feedings, and the counting circuit 120 outputs the first feeding signal to reset the counting signal after a successful reset.
[0139] In some embodiments, the counting circuit 120 and the comparison circuit 130 are arranged in a field programmable gate array. In the technical solution of the embodiments of the present application, the counting circuit 120 and the comparison circuit 130 can be implemented by using the logic circuit in the field programmable gate array (i.e., FPGA), which has high integration degree, small occupied area, and is conducive to miniaturization.
[0140] In a second aspect, the embodiments of the present application provide an electronic device, which comprises a control device and the watchdog circuit as above, the input end WDI of the watchdog chip 110 of the watchdog circuit is connected with the output end of the control device, and the output end of the comparison circuit 130 of the watchdog circuit is connected with the reset end Rst of the control device.
[0141] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should be covered in the scope of the claims and the specification of the present application. Especially, as long as there is no structural conflict, each technical feature mentioned in each embodiment can be combined in any way. The present application is not limited to the specific embodiments disclosed in the text, but includes all technical solutions falling within the scope of the claims.
Claims
1. A watchdog circuit, characterized by The application relates to a watchdog chip, a counting circuit and a comparison circuit. The watchdog chip is connected with the output of the monitored device. The counting circuit is connected with the output of the watchdog chip, and is configured to record the timeout times of the output of the watchdog chip after power-on and the watchdog chip is started, and output a corresponding counting signal according to the timeout times. The comparison circuit is connected with the output of the counting circuit, a preset counting signal and the reset end of the monitored device, and is configured to output a reset signal when the counting signal is greater than or equal to the preset counting signal, so as to enable the reset of the monitored device.
2. The watchdog circuit of claim 1, wherein, The output of the counting circuit comprises a plurality of sub-output ends, and the counting circuit is configured to change the level state of the output level of one of the plurality of sub-output ends each time the timeout of the output of the watchdog chip is recorded.
3. The watchdog circuit of claim 2, wherein, The comparison circuit comprises a plurality of first input ends and a plurality of second input ends, the plurality of first input ends are connected with the plurality of sub-output ends of the counting circuit one by one, and the plurality of second input ends are used for connecting a plurality of preset state input levels arranged in a first direction, wherein the plurality of preset state input levels constitute the preset counting signal.
4. The watchdog circuit of claim 3, wherein, The application further comprises a voltage configuration circuit. The voltage configuration circuit is connected with the plurality of second input ends of the comparison circuit, and is used for configuring the level state of each input level.
5. The watchdog circuit according to any one of claims 2 to 4, characterized in that The counting circuit comprises n counting components arranged in the first direction and n-2 first logic gates, wherein n is a natural number greater than or equal to 3. The first input end of the first counting component is connected with a first level, the first input end of the second counting component is connected with the output end of the first counting component, and the first input end of each counting component from the third counting component is connected with the first input end and the output end of the previous counting component through one first logic gate. The second input end of each counting component is commonly connected with the output end of the watchdog chip. The output end of each counting component further constitutes the plurality of sub-output ends of the counting circuit.
6. The watchdog circuit of claim 5, wherein, The counting component comprises a T flip-flop or a JK flip-flop. The input end, the clock end and the output end of the T flip-flop constitute the first input end, the second input end and the output end of the counting component respectively. The two input ends of the JK flip-flop are commonly connected to constitute the first input end of the counting component, and the clock end and the output end of the JK flip-flop constitute the second input end and the output end of the counting component respectively.
7. The watchdog circuit according to claim 5 or 6, characterized in that The first logic gate comprises an AND gate circuit, the first input end and the second input end of the AND gate circuit are connected with the first input end and the output end of the previous counting component, and the output end of the AND gate circuit is connected with the first input end of the current counting component.
8. The watchdog circuit according to any one of claims 2 to 7, characterized in that The comparison circuit comprises n first comparison components arranged in the first direction and a second comparison component. The first input end of each of the first comparison components constitutes a first input end of the comparison circuit, the second input end of each of the first comparison components constitutes a second input end of the comparison circuit, and the first comparison components are configured to output a second level when the level states of the input levels received at the first input end and the second input end are the same. Each input end of the second comparison component is connected to the output end of each of the first comparison components in one-to-one correspondence, the output end of the second comparison component is connected to a reset end of the monitored device, and the second comparison component outputs the reset signal when the second level is received at each input end.
9. The watchdog circuit of claim 8, wherein, The first comparison component includes an exclusive-OR gate circuit, two input ends of the exclusive-OR gate circuit constitute the first input end and the second input end of the first comparison component, and the output end of the exclusive-OR gate circuit constitutes the output end of the comparison component.
10. The watchdog circuit of claim 8, wherein, The second comparison component includes n-1 OR gate circuits. When n=3, two input ends of a first OR gate circuit are connected to the output end of a first first comparison component and the output end of a second first comparison component, two input ends of a second OR gate circuit are connected to the output end of the first OR gate circuit and the output end of a third first comparison component, and the output end of the second OR gate circuit serves as the output end of the comparison circuit. When n=4, two input ends of a first OR gate circuit are connected to the output end of a first first comparison component and the output end of a second first comparison component, two input ends of a second OR gate circuit are connected to the output end of a third first comparison component and the output end of a fourth first comparison component, two input ends of a third OR gate circuit are connected to the output ends of the first and second OR gate circuits, and the output end of the third OR gate circuit serves as the output end of the comparison circuit. When n is an odd number and n≥5, the n-1 OR gate circuits are divided into (n+1) / 2 layers, the first layer of OR gate circuits includes (n-2) / 2 OR gate circuits, each input end of the first layer of OR gate circuits constitutes the 1st to (n-1)th input ends of the second comparison component, the input end of the jth layer of OR gate circuits is connected to the output end of the (j-1)th, (j-2)th or first layer of OR gate circuits, the last layer of OR gate circuits includes one OR gate circuit, the first input end of the last layer of OR gate circuits is connected to the output end of the (n+1) / 2-1 layer of OR gate circuits, the second input end of the last layer of OR gate circuits constitutes the nth input end of the second comparison component, the output end of the last layer of OR gate circuits constitutes the output end of the second comparison component, and j=2, 3, …, (n+1) / 2-1. When n is even and n≥6, the n-1 or gate circuits are divided into n / 2 layers, the first layer of or gate circuits comprises n / 2 or gate circuits, each input terminal of the first layer of or gate circuits respectively constitutes each input terminal of the second comparison component, the input terminal of the i layer of or gate circuits is connected with the output terminal of the i-1 layer, i-2 layer or the first layer of or gate circuits, the last layer of or gate circuits comprises 1 or gate circuit, each input terminal of the last layer of or gate circuits is connected with the output terminal of the n / 2-1 layer or n / 2-2 layer of or gate circuits, the output terminal of the last layer of or gate circuits constitutes the output terminal of the second comparison component, i=2, 3, …, n / 2-1.
11. The watchdog circuit of claim 8, wherein, The second comparison component comprises an or gate circuit. Each input terminal of the or gate circuit is connected with the output terminal of each first comparison component, and the output of the or gate circuit constitutes the output terminal of the second comparison component.
12. The watchdog circuit of claim 2, wherein, The number-analog conversion circuit is further connected with the plurality of sub-output terminals of the counting circuit, and is configured to convert the counting signal with the output level arranged in the first direction into an analog counting signal.
13. The watchdog circuit of claim 12, wherein, The comparison circuit comprises a comparison device, a first input terminal of the comparison device is connected with an output terminal of the number-analog conversion circuit, a second input terminal of the comparison device is connected with a voltage signal representing the pre-designed digital signal, and an output terminal of the comparison device is connected with a reset terminal of the monitored device.
14. The watchdog circuit of claim 13, wherein, The voltage configuration circuit is further connected with the second input terminal of the comparison circuit, and is configured to configure the voltage value of the voltage signal. The voltage configuration circuit comprises a power-on starting state and a normal working state, the voltage configuration circuit is further configured to configure the pre-designed digital signal at a first voltage in the power-on starting state, and the voltage configuration circuit is further configured to configure the pre-designed digital signal at a second voltage in the normal working state.
15. The watchdog circuit of claim 4 or 14, wherein, The first voltage corresponds to a timeout number greater than the timeout number corresponding to the second voltage. The voltage configuration circuit comprises a power supply circuit or a control chip, the power supply circuit is connected with the second input terminal of the comparison circuit, and the control chip is connected with the second input terminal of the comparison circuit.
16. The watchdog circuit of claim 15, wherein, The counting circuit further comprises a clear terminal, the clear terminal is connected with the output terminal of the comparison circuit or the input terminal of the watchdog chip.
17. The watchdog circuit of claim 1, wherein, The counting circuit and the comparison circuit are arranged in a field programmable gate array.
18. The watchdog circuit of claims 1, 2, 3, 13, or 14, wherein, The watchdog circuit comprises a control device and the watchdog circuit according to any one of claims 1 to 18, an input terminal of a watchdog chip of the watchdog circuit is connected with an output terminal of the control device, and an output terminal of a comparison circuit of the watchdog circuit is connected with a reset terminal of the control device.
19. An electronic device, comprising: