Polycrystalline silicon trench SiC diode with P-type masking layer

Abstract

The utility model discloses a polycrystalline silicon groove SiC diode with a P-type masking layer, and relates to the technical field of semiconductors. In the SiC SBD diode, a Poly electrode and an N-drift layer are insulated by using an oxide layer to form a planar capacitor, and the two sides of the Poly electrode repel surrounding electrons during reverse blocking, so that a depletion region of the upper N-drift layer is expanded, the electric field intensity at a Schottky interface is reduced, the Schottky effect is weakened, and electric leakage is reduced. And meanwhile, the P-type masking layer extends into the N-drift layer by utilizing an etched groove and is connected with the positive electrode at an equal potential, and when the device is reversely blocked, an electric field peak value moves downwards from the surface and is far away from a Schottky interface, so that electric leakage is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a polycrystalline silicon trench SiC diode with a P-type masking layer. Background Technology

[0002] SiC can achieve high-voltage diodes with a high voltage rating of over 600V using the SBD (Schottky Barrier Diode) structure, a high-frequency device structure. Replacing the current mainstream fast PN junction diodes (FRDs) with SiC-SBDs can significantly reduce recovery losses, which is beneficial for improving power supply efficiency. Furthermore, it enables the miniaturization of passive components such as inductors through high-frequency driving and can reduce noise. Therefore, it is widely used in power conditioners in air conditioners, power supplies, photovoltaic power generation systems, power factor correction circuits (PFC circuits), and rectifier bridge circuits in electric vehicle fast chargers.

[0003] The HTRB (High Temperature Reverse Bias) test is a reliability test that SiC SBD diodes must undergo. In this test, SiC SBDs with high native leakage current often fail first due to thermal accumulation. This is because at 175°C and 80% VR bias voltage, the leakage current of SiC SBDs can reach tens or hundreds of μA. During the test, the chip will generate heat due to leakage current. If the heat cannot be dissipated quickly, the junction temperature of the chip will exceed 175°C, which will greatly increase the failure rate of SiC SBDs. Therefore, reducing the native leakage current of SiC SBDs is particularly important. Utility Model Content

[0004] To address the above problems, this invention proposes a polycrystalline silicon trench SiC diode with a P-type masking layer that reduces the electric field strength and leakage current at the substrate interface.

[0005] The technical solution of this utility model is:

[0006] A polysilicon trench SiC diode with a P-type masking layer includes a back metal layer, an N-type masking layer, and an N-type masking layer arranged sequentially from bottom to top. + Substrate layer, N-type buffer layer, N - Drift layer, Schottky metal, and front metal;

[0007] The N - The drift layer is equipped with:

[0008] The poly layer has several components, each originating from the N... - The top surface of the drift layer extends downwards;

[0009] Several oxide layers are provided, respectively located between the Poly layer and the N layer. -Between drift layers; the top surface of the oxide layer is flush with the top surface of the poly layer, and the bottom surface of the oxide layer is flush with the bottom surface of the poly layer;

[0010] A P-type masking layer is disposed on the bottom surface and corners of the oxide layer and the poly layer.

[0011] Specifically, the Schottky metal is reacted with N... - The drift layer, oxide layer, and poly layer are connected.

[0012] Specifically, the N - The thickness of the drift layer is 5-15 μm.

[0013] Specifically, the depth of the Poly layer is 0.8-1.2 μm.

[0014] Specifically, the bottom of the Poly layer is in contact with the P-type masking layer, the sides are in contact with the oxide layer, and the top is in contact with the N-type masking layer. - The surface of the drift layer is flush.

[0015] The beneficial effects of this utility model are:

[0016] Compared to traditional SiC JBS diodes, this invention utilizes an oxide layer to bond the Poly electrode to the N-type diode. - The drift layer acts as an insulator, forming a planar capacitor. During reverse blocking, the poly electrodes repel surrounding electrons, causing the upper N-layer to... - Lower doping concentration in the drift layer allows for better depletion region expansion, reduces the electric field strength at the Schottky interface, weakens the Schottky effect, and decreases leakage current. Simultaneously, trenches are used to extend the P-type masking layer from the surface to the N-type layer. - Inside the drift layer and connected to the positive electrode at the same potential, when the device is reverse blocked, N - The electric field distribution within the drift layer is altered, with the electric field peak shifting downwards from the surface, away from the Schottky interface, thereby reducing leakage current. Therefore, lower reverse leakage current and higher breakdown voltage can be achieved in epitaxial layers with the same doping.

[0017] During the use of diodes, there are often forward current surges. At this time, the Poly electrode can also serve as a current discharge path. The forward current can not only flow out from the Schottky junction, but also flow into the P-type masking layer through the Poly electrode and then out from the P-type masking layer. Moreover, the current carrying capacity of the PN junction diode is greater than that of the Schottky diode, which greatly improves the forward surge capability of the device. Attached Figure Description

[0018] Figure 1 This is a structural schematic diagram of step S100 of this utility model;

[0019] Figure 2 This is a structural schematic diagram of step S200 of this utility model;

[0020] Figure 3 This is a structural schematic diagram of step S300 of this utility model;

[0021] Figure 4 This is a structural schematic diagram of step S400 of this utility model;

[0022] Figure 5 This is a structural schematic diagram of step S500 of this utility model;

[0023] Figure 6 This is a structural schematic diagram of step S600 of this utility model;

[0024] Figure 7 This is a structural schematic diagram of step S700 of this utility model;

[0025] Figure 8 This is a structural schematic diagram of step S800 of this utility model;

[0026] Figure 9 This is a structural schematic diagram of step S900 of this utility model;

[0027] In the figure, 1 is N + Substrate layer, 2 is an N-type buffer layer, 3 is an N-type buffer layer. - Drift layer, 4 is trench area, 5 is P-type masking layer, 6 is oxide layer, 7 is Poly layer, 8 is Schottky metal, 9 is front metal, and 10 is back metal. Detailed Implementation

[0028] The present invention will now be described in detail with reference to specific practical examples. Examples of the embodiments are shown in the accompanying drawings. The illustrative embodiments and descriptions of the present invention are for explaining the present invention only and are not intended to limit the present invention.

[0029] A method for fabricating a polycrystalline silicon trench SiC diode with a P-type masking layer includes the following steps:

[0030] S100, refer to Figure 1 As shown, in N + An N-type buffer layer 2 is grown on substrate 1;

[0031] N in step S100 + Substrate layer 1 is doped with N ions, with a thickness of 360-400 μm and a doping concentration of 1e. 19 cm -2 ±10%;

[0032] The N-type buffer layer 2 is also doped with N ions, with a thickness of 0.8-1.2 μm and a doping concentration of 1e. 18 cm -2 ±10%.

[0033] S200, refer to Figure 2 As shown, an N-type buffer layer is epitaxially grown on the N-type buffer layer 2. - Drift layer 3;

[0034] In step S200, N - Drift layer 3 is doped with N ions at a concentration of 8e⁻¹. 15 -1e 16 cm -2 The thickness is 5-15um.

[0035] S300, refer to Figure 3 As shown, in N - Several downward-extending trench regions 4 are formed on the surface of the drift layer 3 by dry etching;

[0036] In step S300, the depth of trench region 4 is 0.8-1.2 μm, and the spacing is 2.5-3 μm.

[0037] S400, refer to Figure 4 As shown, a P-type masking layer 5 is formed at the bottom of the trench region 4 by ion implantation, and then activated by high-temperature ions after implantation.

[0038] In step S400, the P-type masking layer 5 is doped with Al ions at a doping concentration of 1e. 18 -1e 19 cm -2 The doping depth is 0.5-1um, and the P-type masking layer 5 completely covers the two right angles at the bottom of the trench region 4.

[0039] S500, refer to Figure 5 As shown, an oxide layer 6 is formed on the sidewall of the trench area 4 by dry oxygen thermal oxidation and dry etching;

[0040] In step S500, the oxide layer 6 is connected to the sidewall of the trench region 4. The growth temperature of the oxide layer 6 is 1250-1350℃, and the growth thickness is 40-60nm. It needs to be annealed in a NO atmosphere at a temperature of 1250℃ for 1 hour to improve the density of the gate oxide layer 6 and reduce defects.

[0041] S600, refer to Figure 6 As shown, polysilicon is deposited in trench region 4 to form a Poly layer 7, and Poly electrodes are led out.

[0042] In step S600, the bottom of the Poly layer 7 is in contact with the P-type masking layer 5, the two sides are in contact with the oxide layer 6, and the top is in contact with the N-type masking layer 5. - The surface of drift layer 3 is flush.

[0043] S700, see reference Figure 7 As shown, in N -Schottky metal 8 is formed on the top surface of drift layer 3, oxide layer 6 and poly layer 7 by sputtering Ti or other metals;

[0044] S800, see reference Figure 8 As shown, a front metal 9 is formed on the top surface of the Schottky metal 8 by sputtering AlCu or other metals, and a positive electrode is drawn out.

[0045] S900, refer to Figure 9 As shown, in N + The back side of substrate 1 is thinned to reduce N. + The substrate layer is 1 thickness, and then Ni metal is sputtered and Ti / Ni / Ag metal is evaporated to form the back metal 10, which leads out the negative electrode.

[0046] In step S900, the back metal 10 needs to undergo laser annealing after Ni metal sputtering, with a laser energy of 2-4 mJ / cm. 2 Then, multiple layers of metals such as Ti / Ni / Ag, or other metals, are evaporated, with a total thickness of 1.4-2 μm.

[0047] A polysilicon trench SiC diode with a P-type masking layer includes a back metal layer 10 and an N-type masking layer arranged sequentially from bottom to top. + Substrate 1, N-type buffer layer 2, N - Drift layer 3, Schottky metal 8, and front metal 9;

[0048] The N - The drift layer 3 is equipped with:

[0049] Poly layer 7, having several layers spaced apart from the N... - The top surface of drift layer 3 extends downwards;

[0050] The Poly layer 7 extends downward to a depth of 0.5~1um, and the spacing between adjacent Poly layers 7 is 2.5-3um, in order to ensure the shielding effect on the Schottky junctions on both sides during reverse blocking and reduce leakage current.

[0051] Oxide layer 6 is provided with several layers, respectively located on the Poly layer 7 and N. - Between drift layers 3; the top surface of the oxide layer 6 is flush with the top surface of the poly layer 7, and the bottom surface of the oxide layer 6 is flush with the bottom surface of the poly layer 7;

[0052] P-type masking layer 5 is disposed on the bottom surface and corners of the oxide layer 6 and the poly layer 7.

[0053] The Schottky metal 8 is respectively with N - The drift layer 3, oxide layer 6 and poly layer 7 are connected.

[0054] The front metal 9 covers the Schottky metal 8.

[0055] This invention improves the reverse leakage current of SiC SBD diodes. Compared with traditional SiC JBS diodes, this invention utilizes oxide layer 6 to bond the Poly layer (electrode) 7 to N. - Drift layer 3 is insulating, forming a planar capacitor. During reverse blocking, the two sides of the Poly electrode repel surrounding electrons, causing the upper N-layer to... - The reduced doping concentration of drift layer 3 allows for better expansion of the depletion region and a decrease in the electric field strength at the Schottky interface, thus weakening the Schottky effect and reducing leakage current. Simultaneously, trenches are used to extend the P-type masking layer 5 from the surface to the N-type interface. - Inside drift layer 3 and connected to the positive electrode at the same potential, when the device is reverse blocked, N - The electric field distribution within drift layer 3 is altered, with the electric field peak shifting downwards from the surface, away from the Schottky interface, thereby reducing leakage current. Therefore, lower reverse leakage current and higher breakdown voltage can be achieved in epitaxial layers with the same doping.

[0056] This invention also improves the forward surge capability of SiC SBD diodes. During the use of SiC SBD diodes, there are often forward current surges. At this time, the Poly electrode can also serve as a current discharge path. The forward current can not only flow out from the Schottky junction, but also flow into the P-type masking layer 5 through the Poly electrode, and then flow out from the P-type masking layer 5. The PN junction diode turns on, greatly improving the forward surge capability of the device.

Claims

1. A polycrystalline silicon trench SiC diode with a P-type masking layer, characterized in that, Including the back metal (10), N arranged sequentially from bottom to top + Substrate (1), N-type buffer layer (2), N - Drift layer (3), Schottky metal (8) and front metal (9); The N - The drift layer (3) is provided with: Poly layer (7) is provided with several layers, respectively from the N... - The top surface of the drift layer (3) extends downwards; The oxide layer (6) has several layers, which are respectively located on the Poly layer (7) and the N layer. - Between the drift layers (3); the top surface of the oxide layer (6) is flush with the top surface of the poly layer (7), and the bottom surface of the oxide layer (6) is flush with the bottom surface of the poly layer (7); A P-type masking layer (5) is disposed on the bottom surface and corners of the oxide layer (6) and the poly layer (7).

2. The polycrystalline silicon trench SiC diode with a P-type masking layer according to claim 1, characterized in that, The Schottky metal (8) is reacted with N - The drift layer (3), oxide layer (6) and poly layer (7) are connected.

3. The polycrystalline silicon trench SiC diode with a P-type masking layer according to claim 1, characterized in that, The N - The thickness of the drift layer (3) is 5-15 μm.

4. The polycrystalline silicon trench SiC diode with a P-type masking layer according to claim 1, characterized in that, The depth of the Poly layer (7) is 0.8-1.2 μm.

5. The polycrystalline silicon trench SiC diode with a P-type masking layer according to claim 1, characterized in that, The bottom of the Poly layer (7) is in contact with the P-type masking layer (5), the sides are in contact with the oxide layer (6), and the top is in contact with the N-type masking layer (5). - The surface of the drift layer (3) is flush.

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