Micro light emitting diode chip and micro light emitting diode device
By introducing a planarization layer and a bonding material layer into the micro LED chip, the reliability problem of micro LED devices is solved, and the packaging stability and reliability are improved.
Patent Information
- Application Number
- CN202422923091.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-12-23
- Estimated Expiration
- 2034-11-28
AI Technical Summary
Existing miniature light-emitting diode devices suffer from poor reliability.
A planarization layer is introduced into the micro light-emitting diode chip to fill the inter-pixel trenches between adjacent pixel regions, and is bonded to the driver chip through a first bonding material layer. An underfill adhesive layer is used to fill the gaps between the chips.
This reduces the gap between adjacent pixel areas in the micro LED chip, lowers the probability of underfill voids, and improves the stability of the packaging process and the reliability of the device.
Smart Images
Figure CN223714527U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor light emitting, in particular to a micro light emitting diode chip and a micro light emitting diode device. BACKGROUND
[0002] Micro-LED (Micro-Light Emitting Diode) display technology is a display technology that realizes the addressing control and individual driving of each pixel point by miniaturizing and arraying the traditional LED (Light Emitting Diode) structure and adopting CMOS (Complementary Metal Oxide Semiconductor) or TFT (Thin Film Transistor) to make a driving circuit.
[0003] However, the existing micro light emitting diode device has the problem of poor reliability. SUMMARY
[0004] The present application provides a micro light emitting diode chip and a micro light emitting diode device to solve the problem of poor reliability of the existing micro light emitting diode device.
[0005] In order to solve the above problems, the present application provides a micro light emitting diode chip, which comprises: a light emitting stack, the light emitting stack comprising a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked, and having a pixel array region, the pixel array region comprising a plurality of spaced pixel regions, a spacing region between the plurality of pixel regions being provided with an inter-pixel trench, the inter-pixel trench penetrating through the first semiconductor layer, and the inter-pixel trench spacing the second semiconductor layer in the plurality of pixel regions and spacing the light emitting layer in the plurality of pixel regions; a first electrode, the first electrode being provided on a side of the second semiconductor layer in the pixel region away from the light emitting layer; a first bonding material layer, the first bonding material layer being provided on a side of the first electrode away from the second semiconductor layer and electrically connected with the first electrode; and a planar layer, the planar layer filling the inter-pixel trench, and the first bonding material layer being at least partially exposed on a side of the planar layer away from a bottom wall surface of the inter-pixel trench.
[0006] The micro light emitting diode chip further comprises: a passivation layer, the passivation layer covering the light emitting stack, the first electrode and an inner wall surface of the inter-pixel trench, and the first bonding material layer being provided on a region of the passivation layer away from the light emitting stack and the first electrode and corresponding to the first electrode; and the planar layer completely filling the inter-pixel trench with the inner wall surface covered by the passivation layer.
[0007] The flat layer covers the pixel array region and the first electrode, and a surface of the flat layer away from the pixel array region and the first electrode is a flat surface, and the first bonding material layer is arranged on a region of the flat surface corresponding to the first electrode.
[0008] The micro light emitting diode chip further comprises: a first pad arranged on the region of the flat surface away from the first electrode, and the first bonding material layer is arranged on a side of the first pad away from the first electrode; and a first electrical connection layer located between the first pad and the first electrode and penetrating the flat layer.
[0009] The micro light emitting diode chip further comprises: a second electrode arranged on a bottom wall surface of the groove, and the flat layer covers the second electrode; and a second bonding material layer arranged on a region of a side of the flat layer away from the bottom wall surface of the groove corresponding to the second electrode and electrically connected with the second electrode.
[0010] The flat layer fills the groove with the second electrode arranged on the bottom wall surface, and a filling height of the flat layer in the groove is equal to a depth of the groove.
[0011] The height of the second bonding material layer relative to the plane on which the bottom wall surface of the groove is located is equal to the height of the first bonding material layer relative to the plane on which the bottom wall surface of the groove is located.
[0012] The micro light emitting diode chip further comprises: a second pad arranged on the region of the side of the flat layer away from the bottom wall surface of the groove corresponding to the second electrode, and the second bonding material layer is arranged on a side of the second pad away from the second electrode; and a second electrical connection layer located between the second pad and the second electrode and penetrating the flat layer.
[0013] To solve the above problems, the embodiment of the present application further provides a micro light emitting diode device, which comprises the micro light emitting diode chip of any one of the above and a driving chip and a bottom filling adhesive layer, wherein the micro light emitting diode chip is bonded with the driving chip through the first bonding material layer, and the bottom filling adhesive layer is located between the micro light emitting diode chip and the driving chip and fills a gap between the micro light emitting diode chip and the driving chip.
[0014] The light-emitting stack also has a pixel peripheral region located at the periphery of the pixel array region, and the pixel peripheral region is provided with a groove penetrating to the first semiconductor layer; the micro light-emitting diode chip further comprises a second electrode and a second bonding material layer, wherein the second electrode is arranged on the bottom wall surface of the groove, and the planar layer covers the second electrode, the second bonding material layer is arranged on the side of the planar layer away from the bottom wall surface of the groove and corresponds to the region of the second electrode, and is electrically connected with the second electrode; and the micro light-emitting diode chip is bonded with the driving chip through the first bonding material layer and the second bonding material layer.
[0015] The micro light-emitting diode chip and the micro light-emitting diode device provided by the application introduce a planar layer in the micro light-emitting diode chip, the planar layer fills the pixel gap groove between adjacent pixel regions, and the first bonding material layer at least partially protrudes and is exposed on the side of the planar layer away from the bottom wall surface of the pixel gap groove, thereby reducing the gap between adjacent pixel regions in the micro light-emitting diode chip, and effectively improving the generation of the underfill void in the subsequent underfill process, reducing the probability of the generation of the underfill void, improving the stability of the subsequent packaging process, protecting the solder joint, and improving the reliability of the micro light-emitting diode device. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.
[0017] Figure 1 is a cross-sectional structure schematic diagram of the micro light-emitting diode chip provided by the embodiment of the application;
[0018] Figure 2 is another cross-sectional structure schematic diagram of the micro light-emitting diode chip provided by the embodiment of the application;
[0019] Figure 3 is a cross-sectional structure schematic diagram of the micro light-emitting diode device provided by the embodiment of the application;
[0020] Figure 4 is another cross-sectional structure schematic diagram of the micro light-emitting diode device provided by the embodiment of the application.
DETAILED DESCRIPTION
[0021] The embodiments of the present application will be further described below with reference to the drawings and embodiments. It is to be particularly noted that the following embodiments merely illustrate the embodiments of the present application, but do not limit the scope of the embodiments of the present application. Similarly, the following embodiments are only some of the embodiments of the present application, but not all the embodiments. All other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the embodiments of the present application.
[0022] When describing the structure of a component, when a layer or a region is referred to as being "on" or "above" another layer or another region, it can mean that it is directly above the other layer or the other region, or other layers or regions are included therebetween. And if the component is flipped, the layer or the region will be "under" or "below" the other layer or the other region. In addition, the features, structures or characteristics described below can be combined in any suitable manner in one or more embodiments.
[0023] In addition, the direction terms mentioned in the embodiments of the present application, such as [up], [down], [front], [back], [left], [right], [inward], [outward], [side] and the like, are only the directions of the attached drawings. Therefore, the direction terms used are used to illustrate and understand the embodiments of the present application, and are not used to limit the embodiments of the present application. In each figure, similar units are represented by the same reference numerals. For the sake of clarity, each part in the drawings is not drawn to scale. In addition, some related parts can not be shown in the drawings.
[0024] The embodiments of the present application will be further described below with reference to the drawings and embodiments. It is to be particularly noted that the following embodiments merely illustrate the embodiments of the present application, but do not limit the scope of the embodiments of the present application. Similarly, the following embodiments are only some of the embodiments of the present application, but not all the embodiments. All other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the embodiments of the present application.
[0025] Please refer to Figure 1 , Figure 1 is a schematic diagram of a cross-sectional structure of a micro light emitting diode chip provided by the embodiments of the present application. As shown in Figure 1As shown, the micro light emitting diode chip 10 comprises a light emitting stack 101, a first electrode 102, a first bonding material layer 103 and a planar layer 104. The light emitting stack 101 has a pixel array region C1 comprising a plurality of pixel regions C11 spaced apart from each other and arranged in an array, and a spacing region C12 between the pixel regions C11 is provided with an inter-pixel trench 105. Specifically, the light emitting stack 101 comprises a first semiconductor layer 1011, a light emitting layer 1012 and a second semiconductor layer 1013 which are sequentially stacked, and the inter-pixel trench 105 penetrates through the first semiconductor layer 1011 and separates the second semiconductor layer 1013 in the pixel regions C11 and separates the light emitting layer 1012 in the pixel regions C11. The first electrode 102 is arranged on the side of the second semiconductor layer 1013 in the pixel regions C11 away from the light emitting layer 1012. The first bonding material layer 103 is arranged on the side of the first electrode 102 away from the second semiconductor layer 1013 and is electrically connected to the first electrode 102. The planar layer 104 fills the inter-pixel trench 105 to reduce the gap between the adjacent pixel regions C11 in the micro light emitting diode chip 10. Moreover, the first bonding material layer 103 at least partially protrudes out of the side of the planar layer 104 away from the bottom wall surface of the inter-pixel trench 105, i.e., the height of the planar layer 104 relative to the plane where the bottom wall surface of the inter-pixel trench 105 is located is less than the height of the first bonding material layer 103 relative to the plane where the bottom wall surface of the inter-pixel trench 105 is located, so as to ensure that the micro light emitting diode chip 10 can be bonded to other chips (such as a driving chip) through the first bonding material layer 103.
[0026] Therefore, in the present embodiment, by introducing the planar layer 104 in the micro light emitting diode chip 10, the planar layer 104 fills the gap in the spacing region between the adjacent pixel regions C11 (i.e., the inter-pixel trench 105), and the first bonding material layer 103 at least partially protrudes out of the side of the planar layer 104 away from the bottom wall surface of the inter-pixel trench 105, which not only ensures that the micro light emitting diode chip 10 can be bonded to other chips (such as a driving chip) through the first bonding material layer 103, but also reduces the gap between the adjacent pixel regions C11 in the micro light emitting diode chip 10, so that the generation of underfill voids in the subsequent underfill process can be effectively improved, and the probability of underfill voids is reduced, which not only improves the stability of the subsequent packaging process, but also protects the solder joints and improves the reliability of the micro light emitting diode device.
[0027] Moreover, it should be noted that, in the present embodiment, the planar layer 104 filling the inter-pixel trench 105 can include two cases, i.e., the planar layer 104 partially filling the inter-pixel trench 105, and the planar layer 104 completely filling the inter-pixel trench 105.
[0028] Specifically, the inner wall surface of the aforementioned inter-pixel trench 105 and the planar layer 104 can be free of other film layers, and the planar layer 104 can completely fill or partially fill the inter-pixel trench 105. Alternatively, the inner wall surface of the aforementioned inter-pixel trench 105 and the planar layer 104 can be provided with other film layers (such as the passivation layer 111 shown in FIG. 1B), and the planar layer 104 can completely fill or partially fill the inter-pixel trench 105 whose inner wall surface is covered with the other film layers. Figure 1
[0029] Specifically, the filling height of the planar layer 104 in the inter-pixel trench 105 can be greater than or equal to the height of the upper surface of the first semiconductor layer 1011 exposed on the side wall surface of the inter-pixel trench 105, and can be greater than or equal to the height of the upper surface of the light-emitting layer 1012 exposed on the side wall surface of the inter-pixel trench 105, to ensure that the planar layer 104 can effectively reduce the gap between adjacent pixel regions C11 in the micro light-emitting diode chip 10.
[0030] In some examples, the material of the aforementioned first electrode 102 can include at least one of titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), and aluminum (Al), etc. In some examples, the material of the aforementioned first bonding material layer 103 can include one or more of gold (Au), tin (Sn), indium (In), and copper (Cu), etc. In some examples, the aforementioned first bonding material layer 103 can be in a partial spherical shape. Specifically, the aforementioned first bonding material layer 103 can be formed by adopting a reflow soldering process.
[0031] In the present embodiment, the aforementioned planar layer 104 can be prepared from an insulating material. Specifically, the material of the aforementioned planar layer 104 can be an organic insulating material, which can specifically be polyimide. Specifically, the aforementioned planar layer 104 can be formed by a coating process. In this way, a planar surface of the planar layer 104 can be obtained without a chemical mechanical polishing (CMP) process.
[0032] In some alternative embodiments, the material of the aforementioned planar layer 104 can also be an inorganic insulating material, which can specifically be at least one of silicon oxide, silicon nitride, and aluminum oxide, etc. Specifically, the aforementioned planar layer 104 can be formed by a deposition process.
[0033] In this embodiment, in the aforementioned light-emitting stack 101, the light-emitting layer 1012 can be a quantum well layer, for example, an indium gallium nitride (IGaN) quantum well layer, or an IGaN / GaN multi-quantum well layer. The first semiconductor layer 1011 and the second semiconductor layer 1013 have different polarities. Specifically, the first semiconductor layer 1011 can be either an N-type semiconductor layer or a P-type semiconductor layer, and the second semiconductor layer 1013 can be either an N-type semiconductor layer or a P-type semiconductor layer. Specifically, the N-type semiconductor layer can be an N-type gallium nitride layer or an N-type gallium arsenide layer, and the P-type semiconductor layer can be a P-type gallium nitride layer or a P-type aluminum gallium nitride layer. Correspondingly, the aforementioned first electrode 102 can be an N-type electrode electrically connected to the N-type semiconductor layer, or it can be a P-type electrode electrically connected to the P-type semiconductor layer.
[0034] Specifically, such as Figure 1 As shown, the aforementioned micro-LED chip 10 may further include a current diffusion layer 106. The current diffusion layer 106 is disposed on the side of the second semiconductor layer 1013 in the pixel region C11 opposite to the light-emitting layer 1012, and the aforementioned first electrode 102 may be disposed on the side of the current diffusion layer 106 opposite to the second semiconductor layer 1013. Furthermore, the current diffusion layer 106 can distribute the current very uniformly throughout the entire second semiconductor layer 1013 (e.g., a P-type gallium nitride layer), thereby effectively improving the luminous efficiency of the aforementioned micro-LED chip 10.
[0035] In some examples, the current diffusion layer 106 can be formed by depositing multiple layers of metal (e.g., titanium (Ti), aluminum (Al), gold (Au), platinum (Pt) or nickel (Ni)) or semiconductor oxide (e.g., indium tin oxide (ITO) or zinc oxide (ZnO)) onto the surface of the second semiconductor layer 1013 in the pixel region C11 away from the light-emitting layer 1012 to create current conduction.
[0036] In some embodiments, the micro LED chip 10 may further include a reflective layer (not shown in the figure), which is disposed between the first electrode 102 and the current diffusion layer 106. Specifically, during the use of the micro LED chip 10, the light emitted by the light-emitting layer 1012 in the pixel region C11 that propagates to the reflective layer can be reflected by the reflective layer, and the reflected light will propagate outward toward the side of the light-emitting stack 101 away from the reflective layer (i.e., the light-emitting side), thereby enabling the micro LED chip 10 to emit light on the side of the light-emitting stack 101 away from the reflective layer and improving the luminous efficiency of the micro LED chip 10.
[0037] In some examples, the material of the reflective layer can include any material having high reflectivity (e.g., greater than 50%) to visible light, such as titanium (Ti), aluminum (Al), silver (Ag), platinum (Pt), nickel (Ni), and the like. In other examples, the reflective layer can also be formed by stacking multiple layers of materials having different refractive indices.
[0038] In some embodiments, as shown in FIG. 1A, the micro light emitting diode chip 10 can further include a first substrate 107 for supporting the film layer structure thereon. Specifically, the micro light emitting diode chip 10 can further include a buffer layer 108, which can be disposed on one side of the first substrate 107, and the light emitting stack 101 can be disposed on the side of the buffer layer 108 facing away from the first substrate 107. Figure 1
[0039] Specifically, the first semiconductor layer 1011, the light emitting layer 1012, and the second semiconductor layer 1013 can be sequentially stacked on the side of the buffer layer 108 facing away from the first substrate 107, and the buffer layer 108 can relieve the stress between the first semiconductor layer 1011 and the first substrate 107 due to lattice mismatch and thermal expansion coefficient mismatch.
[0040] In some examples, the first substrate 107 can be a sapphire substrate, a silicon substrate, or a silicon carbide substrate, etc. The material of the buffer layer 108 can include buffer materials such as silicon nitride, silicon oxide, gallium nitride, or aluminum nitride, etc. For example, the buffer layer 108 can specifically be an unintentionally doped gallium nitride (U-GaN) layer.
[0041] In the above embodiments, as shown in FIG. 1A, the inter-pixel trench 105 can sequentially penetrate the second semiconductor layer 1013 and the light emitting layer 1012 from top to bottom, and extend into the first semiconductor layer 1011, so as to achieve the gap spacing the second semiconductor layer 1013 in each pixel region C11 from the second semiconductor layer 1013 in other pixel regions C11 located in the periphery thereof, achieve the gap spacing the light emitting layer 1012 in each pixel region C11 from the light emitting layer 1012 in other pixel regions C11 located in the periphery thereof, and achieve the inter-pixel trench 105 spacing the top end of the first semiconductor layer 1011 in each pixel region C11 from the top end of the first semiconductor layer 1011 in other pixel regions C11 located in the periphery thereof. In this way, independent control of the light emitting of the light emitting layer 10 in each pixel region C11 can be achieved. Figure 1
[0042] In some embodiments, as shown in FIG. 1A, the micro light emitting diode chip 10 can further include a first substrate 107 for supporting the film layer structure thereon. Specifically, the micro light emitting diode chip 10 can further include a buffer layer 108, which can be disposed on one side of the first substrate 107, and the light emitting stack 101 can be disposed on the side of the buffer layer 108 facing away from the first substrate 107. Figure 1 As shown, the micro light emitting diode chip 10 can further include a passivation layer 111 covering the light emitting stack 101 and the first electrode 102, so as to effectively prevent the water and oxygen in the external environment from corroding the light emitting stack 101, the current diffusion layer 106, the reflective layer and the first electrode 102, thereby improving the reliability of the product.
[0043] Correspondingly, the first bonding material layer 103 can be arranged on the region corresponding to the first electrode 102 on the side of the passivation layer 111 away from the light emitting stack 101 and the first electrode 102, so as to realize the electrical connection between the first bonding material layer 103 and the first electrode 103.
[0044] In addition, in the above-mentioned embodiments in which the micro light emitting diode chip 10 further includes the current diffusion layer 106 and / or the reflective layer, the passivation layer 111 can also cover the current diffusion layer 106 and / or the reflective layer, so as to effectively prevent the water and oxygen in the external environment from corroding the current diffusion layer 106 and / or the reflective layer, thereby improving the reliability of the product.
[0045] In some examples, the material of the passivation layer 111 can include at least one of an insulating material such as silicon oxide, silicon nitride and aluminum oxide.
[0046] In some specific embodiments, as shown, Figure 1 As shown, the inner wall surface of the inter-pixel trench 105 can be covered with the passivation layer 111, so as to effectively prevent the water and oxygen in the external environment from corroding the inner wall surface of the inter-pixel trench 105, thereby improving the reliability of the product.
[0047] Specifically, the side wall surface of the inter-pixel trench 105 can be covered with the passivation layer 111; or, as shown, Figure 1 As shown, the side wall surface and the bottom wall surface of the inter-pixel trench 105 can be covered with the passivation layer 111.
[0048] In addition, the planar layer 104 can completely fill the inter-pixel trench 105 whose inner wall surface is covered with the passivation layer 111. In other words, part of the space in the inter-pixel trench 105 is filled with the passivation layer 111, and the remaining space in the inter-pixel trench 105 except for the part of the space is filled with the planar layer 104.
[0049] In some embodiments, as shown, Figure 1As shown, the planar layer 104 can cover the pixel array region C1 and the first electrode 102, and the surface of the planar layer 104 away from the pixel array region C1 and the first electrode 102 can be a planar surface F1. Accordingly, the first bonding material layer 103 can be arranged on the region of the planar surface F1 corresponding to the first electrode 102. In this way, the planar layer 104 is arranged to completely fill the gap between the first electrode 102 on each pixel region C11 and the first electrode 102 on the other pixel region C11 located at the periphery thereof, so that the probability of voids occurring during the subsequent underfilling process can be reduced more effectively, and the reliability of the micro light emitting diode device is further improved.
[0050] In the above embodiment in which the micro light emitting diode chip 10 further includes the passivation layer 111, the planar layer 104 can be arranged on the side of the passivation layer 111 away from the light emitting stack 101 and the first electrode 102.
[0051] In some specific embodiments, as shown, Figure 1 The micro light emitting diode chip 10 can further include a first electrical connection layer 109 located between the first bonding material layer 103 and the first electrode 102 and penetrating at least part of the film layers (such as the planar layer 104 and / or the passivation layer 111) located between the first bonding material layer 103 and the first electrode 102. Moreover, the opposite ends of the first electrical connection layer 109 in the longitudinal direction Z can be electrically connected to the first bonding material layer 103 and the first electrode 102, respectively, so as to realize electrical connection between the first bonding material layer 103 and the first electrode 102.
[0052] In some specific embodiments, as shown, Figure 1 The micro light emitting diode chip 10 can further include a first pad 110 arranged on the region of the planar surface F1 of the planar layer 104 corresponding to the first electrode 102. Specifically, the first bonding material layer 103 can be arranged on the side of the first pad 110 away from the first electrode 102, and the first electrical connection layer 109 can be located between the first pad 110 and the first electrode 102 and penetrate all the film layers (such as the planar layer 104 and / or the passivation layer 111) located between the first pad 110 and the first electrode 102.
[0053] Accordingly, the opposite ends of the first electrical connection layer 109 in the longitudinal direction Z can be electrically connected to the first pad 110 and the first electrode 102, respectively, so as to realize electrical connection between the first pad 110 and the first electrode 102.
[0054] It should be noted that, in the embodiment, the first electrically connecting layer 109, the first pad 110 and the first bonding material layer 103 are sequentially stacked on the side of the first electrode 102 away from the second semiconductor layer 1023, so that the electrically connecting performance between the first electrically connecting layer 109 and the first bonding material layer 103 can be improved by the first pad 110, and the first bonding material layer 103 can be formed on the surface of the first pad 110 away from the first electrode 102 by reflowing the solder, that is, the process difficulty of forming the first bonding material layer 103 is reduced.
[0055] In some examples, the material of the first electrically connecting layer 109 can include conductive materials such as titanium (Ti), aluminum (Al), gold (Au), platinum (Pt) and / or nickel (Ni).
[0056] In the above embodiment, as shown in Figure 2 The light-emitting stack 101 can further have a pixel peripheral region C2 located at the periphery of the pixel array region C1. Figure 2 As shown in
[0057] In some examples, as shown in Figure 2 The recess 112 can sequentially penetrate the second semiconductor layer 1013, the light-emitting layer 1012 and part of the first semiconductor layer 1011 from top to bottom, and the bottom wall surface of the recess 112 and the bottom wall surface of the inter-pixel trench 105 can be located on the same plane or can be substantially located on the same plane.
[0058] In some examples, as shown in Figure 2 The pixel peripheral region C2 can surround the pixel array region C1, and the cross-sectional shape of the recess 112 perpendicular to the longitudinal direction Z can be annular, such as a circular ring or a square ring.
[0059] In some examples, as shown in Figure 2 The included angle between the side wall surface and the bottom wall surface of the recess 112 can be between 90 degrees and 120 degrees, such as 90 degrees, 100 degrees, 110 degrees or 120 degrees.
[0060] Specifically, as shown in Figure 2As shown, the micro light emitting diode chip 10 can further include a second electrode 113 and a second bonding material layer 114. The second electrode 113 is arranged on the bottom wall surface of the groove 112 and is electrically connected with the first semiconductor layer 1011. The second bonding material layer 114 is arranged on the side of the second electrode 113 away from the bottom wall surface of the groove 112 and is electrically connected with the second electrode 113. Moreover, the second bonding material layer 114 at least partially protrudes and is exposed on the side of the flat layer 104 away from the bottom wall surface of the inter-pixel trench 105, that is, the height of the flat layer 104 relative to the plane where the bottom wall surface of the inter-pixel trench 105 is located is less than the height of the second bonding material layer 114 relative to the plane where the bottom wall surface of the inter-pixel trench 105 is located, so as to ensure that the micro light emitting diode chip 10 can be bonded with other chips (such as a driving chip) through the second bonding material layer 114.
[0061] In some examples, the material of the second electrode 113 can include at least one of metal materials such as titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), and aluminum (Al), and in specific implementation, the material of the second electrode 113 can be the same as the material of the first electrode 102.
[0062] In some examples, the material of the second bonding material layer 114 can include one or more of metal materials such as gold (Au), tin (Sn), indium (In), and copper (Cn), and in specific implementation, the material of the second bonding material layer 114 can be the same as the material of the first bonding material layer 103.
[0063] In some embodiments, as Figure 2 As shown, the flat layer 104 can cover the second electrode 113, and the second bonding material layer 114 can be specifically arranged on the region of the flat layer 104 corresponding to the second electrode 113 on the side away from the bottom wall surface of the groove 112, so that the second bonding material layer 114 is not covered by the flat layer 104 and is not wrapped by the flat layer 104, so as to facilitate the bonding of the micro light emitting diode chip 10 with other chips (such as a driving chip) through the second bonding material layer 114.
[0064] In some specific embodiments, as Figure 2 As shown, the flat layer 104 can fill the groove 112 in which the second electrode 113 is arranged on the bottom wall surface, and the filling height of the flat layer 104 in the groove 112 can be equal to the depth of the groove 112, so as to further improve the flatness of the side of the micro light emitting diode chip 10 where the first bonding material layer 103 and the second bonding material layer 114 are arranged, thereby more effectively reducing the probability of voids occurring during the subsequent underfilling process, and further improving the reliability of the micro light emitting diode device.
[0065] Specifically, as shown in Figure 2 the flat layer 104 can cover the pixel array region C1, the first electrode 102, the pixel peripheral region C2 and the second electrode 113, and the surface of the flat layer 104 away from the pixel array region C1, the first electrode 102, the pixel peripheral region C2 and the second electrode 113 can be a flat surface F1. Accordingly, the first bonding material layer 103 can be arranged on the region of the flat surface F1 corresponding to the first electrode 102, and the second bonding material layer 114 can be arranged on the region of the flat surface F1 corresponding to the second electrode 113. In this way, the flatness of the side of the micro LED chip 10 provided with the first bonding material layer 103 and the second bonding material layer 114 can be further improved, so that when underfilling in the subsequent bonding process, the probability of underfilling voids can be more effectively reduced, and the reliability of the micro LED device produced can be further improved.
[0066] Specifically, as shown in Figure 2 in the above embodiment in which the micro LED chip 10 further includes the passivation layer 111, the passivation layer 111 can also cover the second electrode 113 and the inner wall surface of the groove 112, so as to effectively block the erosion of the second electrode 113 and the inner wall surface of the groove 112 by external water and oxygen, thereby improving the product reliability.
[0067] Furthermore, the groove 112 in which the second electrode 113 is arranged on the bottom wall surface and which is filled with the flat layer 104 can include the groove 112 in which the second electrode 113 is arranged on the bottom wall surface and the inner wall surface of which is covered with the passivation layer 111. In other words, part of the space in the groove 112 is filled with the passivation layer 111 and the second electrode 113, and the remaining space in the groove 112 except for the part of the space is filled with the flat layer 104.
[0068] In some specific embodiments, as shown in Figure 2 the micro LED chip 10 can further include a second electrical connection layer 115, which is located between the second bonding material layer 114 and the second electrode 113 and penetrates at least part of the film layer (such as the flat layer 104 and / or the passivation layer 111) between the second bonding material layer 114 and the second electrode 113. Furthermore, the opposite ends of the second electrical connection layer 115 in the longitudinal direction Z can be electrically connected with the second bonding material layer 114 and the second electrode 113 respectively, so as to realize the electrical connection between the second bonding material layer 114 and the second electrode 113.
[0069] In some specific embodiments, as shown in Figure 2As shown, the micro light emitting diode chip 10 can further include a second pad 116 disposed on a region of the flat layer 104 on a side of the flat layer 104 facing away from the bottom wall surface of the groove 112 and corresponding to the second electrode 113. Specifically, the second bonding material layer 114 can be disposed on a side of the second pad 116 facing away from the second electrode 113, and the second electrical connection layer 115 can be located between the second pad 116 and the second electrode 113 and penetrate through all the film layers (such as the flat layer 104 and / or the passivation layer 111) between the second pad 116 and the second electrode 113.
[0070] Correspondingly, opposite ends of the second electrical connection layer 115 in the longitudinal direction Z can be electrically connected with the second pad 116 and the second electrode 113, respectively, so as to realize electrical connection between the second pad 116 and the second electrode 113.
[0071] In addition, it should be noted that, in the embodiment, by sequentially stacking the second electrical connection layer 115, the second pad 116, and the second bonding material layer 114 on a side of the second electrode 113 facing away from the bottom wall surface of the groove 112, not only can the electrical connection performance between the second electrical connection layer 115 and the second bonding material layer 114 be improved through the second pad 116, but also the second bonding material layer 114 can be formed on a surface of the second pad 116 facing away from the second electrode 113 by using a reflow ball formation method of evaporated solder, that is, the process difficulty of forming the second bonding material layer 114 is reduced.
[0072] In some examples, the material of the second electrical connection layer 115 can include conductive materials such as titanium (Ti), aluminum (Al), gold (Au), platinum (Pt), and / or nickel (Ni). In particular implementations, the material of the second electrical connection layer 115 can be the same as the material of the first electrical connection layer 109. In some examples, the material of the second pad 116 can include conductive materials such as titanium (Ti), aluminum (Al), gold (Au), platinum (Pt), and / or nickel (Ni). In particular implementations, the material of the second pad 116 can be the same as the material of the first pad 110.
[0073] In some particular embodiments, as Figure 3As shown, the height of the second bonding material layer 114 relative to the plane containing the bottom wall of the groove 112 can be equal to or substantially equal to the height of the first bonding material layer 103 relative to the plane containing the bottom wall of the groove 112. In other words, the surface of the second bonding material layer 114 facing away from the bottom wall of the groove 112 and the surface of the first bonding material layer 103 facing away from the first semiconductor layer 1011 can be located in the same plane, or substantially in the same plane. This helps to reduce the process difficulty of bonding the micro LED chip 10 to other chips (e.g., driver chips) through the first bonding material layer 103 and the second bonding material layer 114.
[0074] As can be seen from the above, the micro LED chip provided in this application embodiment introduces a planarization layer into the micro LED chip. The planarization layer fills the inter-pixel trenches between adjacent pixel regions, and the first bonding material layer at least partially protrudes and is exposed on the side of the planarization layer away from the bottom wall of the inter-pixel trench. This reduces the gap between adjacent pixel regions in the micro LED chip, and thus effectively improves the generation of underfill voids during the underfilling process of the subsequent bonding process, reducing the probability of underfill voids. This can not only improve the stability of the subsequent packaging process, but also protect the solder joints and improve the reliability of the micro LED device.
[0075] Please see Figure 3 , Figure 3 This is a schematic cross-sectional view of the miniature light-emitting diode device provided in an embodiment of this application. Figures 1 to 3 As shown, the miniature light-emitting diode device 1 includes the miniature light-emitting diode chip 10 of any of the above embodiments (e.g., Figures 1 to 3 (As shown) and the driver chip 20 and the bottom filler 30. The micro light-emitting diode chip 10 is bonded to the driver chip 20 through the first bonding material layer 103, so that the driver chip 20 can drive the micro light-emitting diode chip 10 to emit light, thereby realizing the display function of the micro light-emitting diode device 1.
[0076] The bottom filler 30 is located between the micro LED chip 10 and the driver chip 20, and fills the gap between the micro LED chip 10 and the driver chip 20 to enhance the bonding strength between the micro LED chip 10 and the driver chip 20, thereby improving the reliability of the product.
[0077] In some examples, the aforementioned underfill adhesive 30 can be obtained by filling the gap between the micro-LED chip 10 and the driver chip 20 with an adhesive (e.g., epoxy resin adhesive) through an underfill process after bonding the micro-LED chip 10 and the driver chip 20, and then curing the adhesive filled between the micro-LED chip 10 and the driver chip 20.
[0078] Specifically, as shown in Figure 2 the micro light emitting diode chip 10 includes a light emitting stack 101, a first electrode 102, a first bonding material layer 103, and a planar layer 104. The light emitting stack 101 includes a first semiconductor layer 1011, a light emitting layer 1012, and a second semiconductor layer 1013 which are sequentially stacked, and has a pixel array region C1. The pixel array region C1 includes a plurality of pixel regions C11 which are spaced apart from each other, and a spacing region between the plurality of pixel regions C11 is provided with an inter-pixel trench 105. The inter-pixel trench 105 penetrates the first semiconductor layer 1011, and the inter-pixel trench 105 separates the second semiconductor layer 1013 in the plurality of pixel regions C11 and separates the light emitting layer 1012 in the plurality of pixel regions C11. The first electrode 102 is disposed on a side of the second semiconductor layer 1013 in the pixel region C11 facing away from the light emitting layer 1012. The first bonding material layer 103 is disposed on a side of the first electrode 102 facing away from the second semiconductor layer 1013 and is electrically connected to the first electrode 102. The planar layer 104 fills the inter-pixel trench 105 to reduce the gap between adjacent pixel regions C11 in the micro light emitting diode chip 10. Moreover, the first bonding material layer 103 at least partially protrudes and is exposed on a side of the planar layer 104 facing away from the bottom wall surface 105 of the inter-pixel trench, that is, the height of the planar layer 104 with respect to the plane on which the bottom wall surface of the inter-pixel trench 105 is located is less than the height of the first bonding material layer 103 with respect to the plane on which the bottom wall surface of the inter-pixel trench 105 is located, to ensure that the micro light emitting diode chip 10 can be bonded to the driving chip 20 through the first bonding material layer 103.
[0079] In some embodiments, as shown in Figure 4 and Figure 3 the light emitting stack 101 can also have a pixel peripheral region C2 located at the periphery of the pixel array region C1, and the pixel peripheral region C2 can be provided with a recess 112 penetrating the first semiconductor layer 1011. Specifically, the micro light emitting diode chip 10 can further include a second electrode 113 and a second bonding material layer 114, wherein the second electrode 113 is disposed on the bottom wall surface of the recess 112, and the planar layer 104 covers the second electrode 113, and the second bonding material layer 114 is disposed on a region of the planar layer 104 facing away from the bottom wall surface of the recess 112 corresponding to the second electrode 113 and is electrically connected to the second electrode 113. Moreover, the micro light emitting diode chip 10 can be bonded to the driving chip 20 through the first bonding material layer 103 and the second bonding material layer 114.
[0080] In some embodiments, as shown in Figure 3As shown, the driving chip 20 can include a driving circuit layer 201 and a first driving electrode 202, wherein the first driving electrode 202 is arranged on one side of the driving circuit layer 201. Specifically, the driving circuit layer 201 can include a second substrate (not shown in the figure) and a driving circuit (not shown in the figure), wherein the driving circuit is arranged on one side of the second substrate, and the first driving electrode 202 is arranged on the side of the driving circuit away from the second substrate and is electrically connected with the driving circuit.
[0081] Also, as shown in the above micro light-emitting diode device 1, the first driving electrode 202 of the driving chip 20 can be bonded with the first bonding material layer 103 of the micro light-emitting diode chip 100 correspondingly, so as to realize the bonding connection between the driving chip 20 and the micro light-emitting diode chip 100. Figure 4
[0082] In some embodiments, as shown in the above, the driving chip 20 can further include a second driving electrode 203, and the second driving electrode 203 is arranged on the same side of the driving circuit layer 201 as the first driving electrode 202. Figure 4
[0083] Also, as shown in the above, the second driving electrode 203 of the driving chip 20 can be bonded with the second bonding material layer 114 of the micro light-emitting diode chip 100 correspondingly, so as to realize the bonding connection between the driving chip 20 and the corresponding micro light-emitting diode chip 100.
[0084] In some examples, the first driving electrode 202 can be a pixel electrode (or an anode) of the driving chip 300A, and the second driving electrode 203 can be a common electrode (or a cathode) of the driving chip 20.
[0085] In some examples, the material of the first driving electrode 202 can include conductive materials such as titanium (Ti), aluminum (Al), gold (Au), platinum (Pt), and / or nickel (Ni). The material of the second driving electrode 203 can include conductive materials such as titanium (Ti), aluminum (Al), gold (Au), platinum (Pt), and / or nickel (Ni).
[0086] In some examples, the above micro light-emitting diode device 1 can not only be applied to the projection part of electronic devices such as optical projection and vehicle head-up display (HUD), but also can be applied to the display part of electronic devices, for example, the electronic devices can include any device with a display screen such as a smart phone, a smart watch, a notebook computer, a tablet computer, a driving recorder, a navigator, a head-mounted device, etc., and can also be applied to the lighting part of electronic devices, for example, the electronic devices can include any device with a lighting component such as a vehicle, a street lamp, etc.
[0087] It should be noted that the micro light emitting diode device provided by the embodiment of the present application can realize the beneficial effects of any one of the micro light emitting diode chips provided by the embodiment of the present application due to the micro light emitting diode chip provided by the embodiment of the present application. Details are described in the foregoing embodiments and will not be described here.
[0088] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A micro light emitting diode chip, characterized by, The micro LED chip comprises: a light-emitting stack, the light-emitting stack comprising a first semiconductor layer, a light-emitting layer and a second semiconductor layer arranged in sequence, and having a pixel array region, the pixel array region comprising a plurality of spaced pixel regions, a spacing region between the plurality of pixel regions being provided with an inter-pixel trench, the inter-pixel trench penetrating through the first semiconductor layer, and the inter-pixel trench spacing the second semiconductor layer in the plurality of pixel regions and spacing the light-emitting layer in the plurality of pixel regions; a first electrode provided on a side of the second semiconductor layer in the pixel region away from the light-emitting layer; a first bonding material layer provided on a side of the first electrode away from the second semiconductor layer and electrically connected with the first electrode; a planar layer filling the inter-pixel trench, and the first bonding material layer at least partially protruding from a side of the planar layer away from a bottom wall surface of the inter-pixel trench.
2. The micro light emitting diode chip of claim 1, wherein, The micro LED chip further comprises: a passivation layer covering the light-emitting stack, the first electrode and an inner wall surface of the inter-pixel trench, and the first bonding material layer being provided on a side of the passivation layer away from the light-emitting stack and the first electrode and corresponding to the first electrode; and the planar layer completely filling the inter-pixel trench with the inner wall surface covered by the passivation layer.
3. The micro light emitting diode chip of claim 1, wherein, The planar layer covers the pixel array region and the first electrode, and a surface of the planar layer away from the pixel array region and the first electrode is a planar surface, and the first bonding material layer is provided on a region of the planar surface corresponding to the first electrode.
4. The micro light emitting diode chip of claim 3, wherein, The micro LED chip further comprises: a first pad provided on the region of the planar surface corresponding to the first electrode, and the first bonding material layer being provided on a side of the first pad away from the first electrode; a first electrical connection layer between the first pad and the first electrode and penetrating through the planar layer.
5. The micro light emitting diode chip of claim 1, wherein, The light-emitting stack further has a pixel peripheral region located at a periphery of the pixel array region, and the pixel peripheral region is provided with a groove penetrating through the first semiconductor layer; and the micro LED chip further comprises: a second electrode provided on a bottom wall surface of the groove, and the planar layer covering the second electrode; a second bonding material layer provided on a side of the planar layer away from the bottom wall surface of the groove and corresponding to the second electrode and electrically connected with the second electrode.
6. The micro light emitting diode chip of claim 5, wherein, The planar layer fills the groove provided with the second electrode on the bottom wall surface, and a filling height of the planar layer in the groove is equal to a depth of the groove.
7. The micro light emitting diode chip of claim 5, wherein, A height of the second bonding material layer relative to a plane in which the bottom wall surface of the groove is located is equal to a height of the first bonding material layer relative to the plane in which the bottom wall surface of the groove is located.
8. The micro light emitting diode chip of claim 5, wherein, The micro LED chip further comprises: A second pad is arranged on a region corresponding to the second electrode on a side of the planar layer facing away from the bottom wall surface of the recess, and the second bonding material layer is arranged on a side of the second pad facing away from the second electrode; A second electrical connection layer is arranged between the second pad and the second electrode and penetrates the planar layer.
9. A micro light emitting diode device, characterized by, The micro light emitting diode chip of any one of claims 1 to 8, a driving chip and a bottom filling adhesive layer, wherein the micro light emitting diode chip is bonded to the driving chip through the first bonding material layer, and the bottom filling adhesive layer is arranged between the micro light emitting diode chip and the driving chip and fills a gap between the micro light emitting diode chip and the driving chip.
10. The micro light emitting diode device of claim 9, wherein, The light emitting stack also has a pixel peripheral region located at a periphery of the pixel array region, and the pixel peripheral region is provided with a recess penetrating to the first semiconductor layer; the micro light emitting diode chip further comprises a second electrode and a second bonding material layer, wherein the second electrode is arranged on a bottom wall surface of the recess, and the planar layer covers the second electrode, the second bonding material layer is arranged on a region corresponding to the second electrode on a side of the planar layer facing away from the bottom wall surface of the recess and is electrically connected with the second electrode; and the micro light emitting diode chip is bonded to the driving chip through the first bonding material layer and the second bonding material layer.