Power supply clamping circuit and chip
By utilizing the parasitic capacitance of the discharge transistor to detect ESD events and control the opening of the discharge path, the problem of large area occupied by the power supply clamping circuit is solved, achieving a smaller chip size and stronger ESD protection capability.
Patent Information
- Application Number
- CN202520032296.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-07
- Publication Date
- 2025-12-26
- Estimated Expiration
- 2035-01-07
AI Technical Summary
Existing power clamping circuits require large capacitor values to ensure appropriate response time, resulting in a large circuit area and making it impossible to effectively reduce chip size.
ESD events are detected by using the parasitic capacitance of the discharge transistor, and the opening of the discharge path is controlled by the first feedback network and the second feedback network. This avoids the use of large capacitors in RC circuits and achieves complete discharge of electrostatic charge by utilizing the cross-feedback network structure.
It reduces the circuit footprint and chip size, while improving ESD protection and reliability.
Smart Images
Figure CN223729634U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of electronic circuits, and in particular to a power clamp circuit and a chip. BACKGROUND
[0002] The characteristics of electrostatic discharge (ESD) are that the instantaneous voltage is too high or the instantaneous current is too large, so the chip needs to be designed for electrostatic protection to prevent static electricity from entering the chip and damaging the internal elements of the chip. At present, a power clamp circuit is often used to discharge static electricity to achieve chip electrostatic protection. Figure 1 A circuit schematic diagram of a specific example of a power clamp circuit in the related art is shown, as shown in the figure, the power clamp circuit includes an RC circuit (including a resistor R and a capacitor C), an inverter (including a PMOS tube Q1 and an NMOS tube Q2), and a discharge circuit (including a large NMOS tube Q3). The RC circuit is used to ensure that the discharge circuit is not turned on when the chip is normally powered on, and can detect an ESD event and quickly turn on the discharge circuit when an ESD event occurs between the power supply end Vdd and the ground end Vss. Specifically, when an ESD event occurs, the resistor R and the capacitor C detect the ESD event, and raise the gate potential of the large NMOS tube Q3 through the inverter to turn it on to discharge the static electricity. At the same time, the static voltage is limited to a reasonable range to ensure that the internal circuit of the chip is not damaged.
[0003] In the above power clamp circuit, the resistor R and the capacitor C form a circuit for detecting ESD events. Because the resistance value of the resistor R and the capacitance value of the capacitor C jointly determine the response time of the circuit, the capacitor C needs to have a large capacitance value to ensure that the response time is within a suitable range, so that the large NMOS tube Q3 has sufficient opening time length, and the static electricity can be completely discharged; and further avoid the large NMOS tube Q3 closing too early due to insufficient response time, and the static electricity cannot be completely discharged, and the charges that are not discharged flow to the internal circuit of the chip and damage the internal circuit. Therefore, a capacitor C with a large capacitance value needs to be used, resulting in a large area occupied by this power clamp circuit. CONTENT OF THE INVENTION
[0004] Therefore, the embodiments of the present application provide a power clamp circuit and a chip to solve at least one problem in the background art.
[0005] In a first aspect, the embodiments of the present application provide a power clamp circuit, which comprises:
[0006] A discharge transistor is coupled between the first power supply end and the second power supply end to provide an electrostatic protection path between the first power supply end and the second power supply end.
[0007] a first feedback network configured to switch an output first level to a second level in response to an electrostatic discharge event occurring under an effect of a parasitic capacitance of the discharge transistor; and
[0008] a second feedback network configured to be turned on under a control of the second level to provide a driving level to a control terminal of the discharge transistor, so that the discharge transistor is turned on to turn on the electrostatic discharge path for discharging electrostatic charge.
[0009] With reference to the first aspect, in an optional implementation of the first aspect,
[0010] the discharge transistor comprises a third NMOS transistor;
[0011] a drain of the third NMOS transistor is connected with the first power supply terminal, and a source of the third NMOS transistor is connected with the second power supply terminal;
[0012] a gate of the third NMOS transistor is connected with the first feedback network and the second feedback network respectively, to control the first feedback network to output the second level in the case of the electrostatic discharge event occurring, and to obtain the driving level output by the second feedback network.
[0013] With reference to the first aspect, in an optional implementation of the first aspect,
[0014] the first feedback network comprises a first transistor module configured to be controlled by the discharge transistor to be turned on in the case of the electrostatic discharge event occurring, so that the first feedback network outputs the second level.
[0015] With reference to the first aspect, in an optional implementation of the first aspect,
[0016] the first feedback network comprises a first NMOS transistor and a first resistor;
[0017] a gate of the first NMOS transistor is connected with the control terminal of the discharge transistor; a source of the first NMOS transistor is connected with the second power supply terminal; a drain of the first NMOS transistor is connected with a first terminal of the first resistor, and is configured to output the second level; and a second terminal of the first resistor is connected with the first power supply terminal.
[0018] With reference to the first aspect, in an optional implementation of the first aspect,
[0019] the second feedback network comprises a second transistor module configured to be turned on under the control of the second level to output the driving level to the control terminal of the discharge transistor, so that the control terminal of the discharge transistor is maintained at the driving level in the case of the electrostatic discharge event occurring.
[0020] With reference to the first aspect, in an optional implementation of the first aspect,
[0021] The second feedback network comprises a second PMOS transistor and a second resistor;
[0022] The gate of the second PMOS transistor is configured to obtain the second level; the source of the second PMOS transistor is connected with the first power supply end; the drain of the second PMOS transistor is connected with the first end of the second resistor and is configured to output the driving level; and the second end of the second resistor is connected with the second power supply end.
[0023] With reference to the first aspect, in an optional implementation, the power clamping circuit further comprises:
[0024] The feedback circuit is configured to respond to an electrostatic discharge event faster than the first feedback network under the action of the parasitic capacitance of the discharge transistor, so as to switch the output from the first level to the second level in time.
[0025] With reference to the first aspect, in an optional implementation,
[0026] The feedback circuit comprises a third transistor module and a fourth transistor module connected in series between the first power supply end and the second power supply end;
[0027] The third transistor module and the fourth transistor module are respectively configured to be controlled by the discharge transistor, so that in the case of an electrostatic discharge event, the third transistor module is controlled to be turned off and the fourth transistor module is controlled to be turned on, so that the feedback circuit outputs the second level in time before the first feedback network.
[0028] With reference to the first aspect, in an optional implementation,
[0029] The feedback circuit comprises a fourth PMOS transistor and a fifth NMOS transistor;
[0030] The gate of the fourth PMOS transistor and the gate of the fifth NMOS transistor are respectively connected with the control end of the discharge transistor; the source of the fourth PMOS transistor is connected with the first power supply end; the source of the fifth NMOS transistor is connected with the second power supply end; and the drain of the fourth PMOS transistor is connected with the drain of the fifth NMOS transistor and is configured to output the second level.
[0031] The second aspect provides a chip, which comprises the power clamping circuit according to the first aspect.
[0032] The beneficial effects brought by the technical scheme provided by the embodiments of the present application include: through the first feedback network, an ESD event can be detected and responded to under the action of the parasitic capacitance of the discharge transistor, so as to output a second level to feedback control the second feedback network to open. And through the second feedback network, a driving level can be provided to the control end of the discharge transistor after the second feedback network is controlled to open, so that the control end of the discharge transistor is maintained at the driving level, thereby feedback controlling the discharge transistor to ensure that the discharge transistor is opened before the static charge is completely discharged, and the static charge is discharged through the static protection path between the first power supply end and the second power supply end. Since the embodiments of the present application detect the ESD event by using the parasitic capacitance of the discharge transistor, an RC circuit is not used, so that a large capacitor does not need to be used in the circuit, the occupied area of the circuit can be greatly reduced, and the size of the chip can be reduced.
[0033] Some of the aspects and advantages of the embodiments of the present application will be given in the following description, some will become apparent from the following description, or will be understood by those skilled in the art through practice of the embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS
[0034] The drawings described herein are used to provide further understanding of the present application, and form a part of the present application, wherein the drawings are not necessarily drawn to scale, and some local features can be enlarged or reduced to more clearly show the details of the local features. The illustrative embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation on the present application. In the drawings:
[0035] Figure 1 A circuit schematic diagram of a specific example of a power clamping circuit in the related art;
[0036] Figure 2 A circuit schematic diagram of example one of the power clamping circuit in the embodiments of the present application;
[0037] Figure 3 A circuit schematic diagram of example two of the power clamping circuit in the embodiments of the present application. DETAILED DESCRIPTION
[0038] In order to make the technical scheme and beneficial effects of the present application more obvious and easy to understand, the following will be described in detail by enumerating specific embodiments. Unless otherwise defined, the technical and scientific terms used herein have the same meaning as the technical and scientific terms in the technical field to which the present application belongs.
[0039] The embodiments of the present application are not exhaustive, but only illustrate some embodiments, and are not specifically limited to the scope of the present application. In the case of no contradiction, each step in an embodiment can be implemented as an independent embodiment, and the steps can be combined arbitrarily, for example, the scheme after removing some steps in an embodiment can also be implemented as an independent embodiment, and the order of the steps in an embodiment can be exchanged arbitrarily, in addition, the optional implementation manners in an embodiment can be combined arbitrarily; in addition, the embodiments can be combined arbitrarily, for example, the steps of different embodiments or part or all of the steps of different embodiments can be combined arbitrarily, an embodiment can be combined with the optional implementation manners of other embodiments arbitrarily.
[0040] In each embodiment of the present application, the terms and / or descriptions of the embodiments are consistent and can be referred to each other if there is no special description and logical conflict, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationship.
[0041] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and not as a limitation of the present application.
[0042] In the embodiments of the present application, unless otherwise specified, the elements expressed in singular form, such as "one", "a", "the", "above", "said", "preceding", "this" and the like, can represent "one and only one", and can also represent "one or more", "at least one" and the like. For example, in the case of using articles such as "a", "an", "the" and the like in English, the noun after the article can be understood as singular expression, and can also be understood as plural expression.
[0043] In the embodiments of the present application, "a plurality of" means two or more.
[0044] In some embodiments, the terms "at least one of", "one or more", "a plurality of", "multiple" and the like can be replaced with each other.
[0045] The prefix words, such as "first", "second" and the like, in the embodiments of the present application are merely used to distinguish different description objects, and do not constitute limitation on the position, sequence, priority, value or content of the description objects. The description objects are described in the claims or embodiments in the context of the description, and should not be construed as redundant limitation because of the use of the prefix words. For example, the value of the description object is not limited by the ordinal number, and can be one or more. For example, the value of "first device" can be one or more. In addition, the objects modified by different prefix words can be the same or different. For example, the description object is "device", and "first device" and "second device" can be the same device or different devices, and the types can be the same or different.
[0046] In some embodiments, the term "connection" can mean that there is mutual transmission of electrical signals or data between the connected end and the connected end, which can be understood as "electrical connection", "communication connection" and the like. The "connection" can be a direct connection between two components, or an indirect connection established through other components, or a communication within two components, or any other possible connection form.
[0047] In some embodiments, the terms "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not lower than", "above", "exceed" and the like can be replaced with each other, and the terms "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "not more than", "lower than", "lower than or equal to", "not higher than", "below" and the like can be replaced with each other.
[0048] In some embodiments, high voltage and low voltage, or high voltage and low voltage, or high voltage and low voltage, etc. can be relative values, not limited to absolute values.
[0049] In some embodiments, the transistor can be a single transistor; or a series and / or parallel connection of multiple transistors, and has a functional pole corresponding to each functional pole of the single transistor respectively, and has the same working state as the single transistor, such as the on state and the off state. For example, the single transistor can include a MOSFET (Metal Oxide Semiconductor Field Effect Transistor, abbreviated as MOS tube), and the functional poles can include a gate G, a source S, a drain D and a substrate B. Therefore, the series and / or parallel connection of multiple transistors has a gate G, a source S, a drain D and a substrate B corresponding to the gate G, the source S, the drain D and the substrate B of the single MOS tube respectively, and has the same working state as the single MOS tube. The MOS tube can include a P-type MOS tube (abbreviated as PMOS tube) and an N-type MOS tube (abbreviated as NMOS tube).
[0050] In some embodiments, the transistor can include a control terminal, a first signal terminal and a second signal terminal, and can be configured to turn on or off a path between the first signal terminal and the second signal terminal under the control of a control signal input to the control terminal, so as to connect or block the signal transmission between the first signal terminal and the second signal terminal. In exemplary embodiments, the transistor can include at least one of the following: MOS tube; BJT (triode); IGBT (insulated gate bipolar transistor); GTO (gate turn-off thyristor); SCR (silicon controlled rectifier); MCT (MOS controlled thyristor); IGCT (integrated gate-commutated thyristor); IEGT (electron injection enhancement gate transistor); and the like.
[0051] The embodiments of the present application provide a power clamp circuit, Figure 2 An example one of the power clamp circuit in the embodiments of the present application is shown in the circuit schematic diagram. As shown in the figure, the power clamp circuit includes:
[0052] A discharge transistor 103 is coupled between the first power terminal VDD and the second power terminal VSS, and is configured to provide an electrostatic discharge path between the first power terminal VDD and the second power terminal VSS.
[0053] A first feedback network 101 is configured to switch the output first level to a second level under the action of the parasitic capacitance of the discharge transistor in response to an electrostatic discharge (ESD) event.
[0054] A second feedback network 102 is configured to be turned on under the control of the second level, so as to provide a driving level to the control terminal of the discharge transistor 103, so that the discharge transistor 103 is turned on to turn on the electrostatic discharge path to discharge the electrostatic charge.
[0055] In the embodiments of the present application, compared with the transistor of normal size, the discharge transistor 103 can be a transistor with larger size, for example, can be a MOS tube with longer channel length and / or larger channel width (referred to as large MOS tube). Then, the large MOS tube can provide higher current processing capacity and better heat dissipation performance. The parasitic capacitance of the discharge transistor 103 can cause the gate voltage to rise, for example, the Miller effect caused by the gate-drain capacitance (Cgd) can cause the change of the gate voltage to be amplified, so that the first feedback network 101 can output the second level in response to the ESD event to turn on the electrostatic discharge path to discharge the electrostatic charge. However, the factor of controlling the first feedback network 101 to output the second level in response to the ESD event is not limited to the gate-drain capacitance (Cgd), but can also be due to the action of other parasitic capacitances of the discharge transistor 103.
[0056] When an ESD event occurs, the discharge transistor 103 is turned on to enable the ESD protection path between the first power supply terminal VDD and the second power supply terminal VSS to discharge the static charge. At the same time, the static voltage is limited within a reasonable range to ensure that the internal circuit of the chip is not burned out. And when the chip is normally powered on, the discharge transistor 103 is not turned on, and the ESD protection path is in an open state, and the internal circuit of the chip works normally.
[0057] The first power supply terminal VDD can be a power supply terminal providing a positive power supply voltage, and the second power supply terminal VSS can be a ground terminal, but is not limited thereto.
[0058] The first feedback network 101 can have a first working state outputting a first level, and a second working state outputting a second level. In some examples, the first level can be a high level, and correspondingly, the second level can be a low level, but is not limited thereto. In other examples, the first level can also be a low level, and correspondingly, the second level can be a high level, which can be configured according to the controlled level requirement of the second feedback network 102. Then, the specific structure of the first feedback network 101 can be set according to the actual requirement, and the circuit structure capable of switching from the first working state to the second working state due to the voltage mutation caused by the parasitic capacitance of the discharge transistor when an ESD event occurs can be applicable. In an exemplary embodiment, the controlled switching output level of the first feedback network 101 can be realized by switching of a switching device (such as a transistor), or can also be realized by programmable control of a processor, selection of a chip select chip, etc.
[0059] The second feedback network 102 can be turned off under the control of the first level, and can be turned on under the control of the second level. The driving level output by the second feedback network 102 when turned on can be a high level, but is not limited thereto, and can be configured according to the level requirement of the turned-on discharge transistor 103. Then, the specific structure of the second feedback network 102 can be set according to the actual requirement. In an exemplary embodiment, the second feedback network 102 can be realized by a switching device to be controlled to be turned on or turned off, or can also be realized by programmable control of a processor, etc.
[0060] Therefore, the first feedback network can detect the ESD event and respond under the action of the parasitic capacitance of the discharge transistor, so as to output the second level to feedback control the second feedback network to be turned on. The second feedback network can provide the driving level to the control end of the discharge transistor after being controlled to be turned on, so that the control end of the discharge transistor is maintained at the driving level, thereby feedback controlling the discharge transistor to ensure that the discharge transistor is turned on before the static charge is completely discharged, and the static charge is discharged through the static protection path between the first power supply end and the second power supply end. Since the ESD event is detected by using the parasitic capacitance of the discharge transistor in the embodiment of the present application, the RC circuit is not used, so that a large capacitor does not need to be used in the circuit, the occupied area of the circuit can be greatly reduced, and the chip size can be reduced.
[0061] In an optional embodiment, the discharge transistor 103 includes a third NMOS transistor M3.
[0062] The drain of the third NMOS transistor M3 is connected with the first power supply end VDD, and the source of the third NMOS transistor M3 is connected with the second power supply end VSS.
[0063] The gate of the third NMOS transistor M3 is connected with the first feedback network 101 and the second feedback network 102, respectively, to control the first feedback network 101 to output the second level when the ESD event occurs, and to obtain the driving level output by the second feedback network 102.
[0064] In the embodiment of the present application, the discharge transistor 103 can be the third NMOS transistor M3, but is not limited thereto. When the ESD event occurs between the first power supply end VDD and the second power supply end VSS, the parasitic capacitance of the third NMOS transistor M3 can make the gate voltage of the third NMOS transistor M3 rise, so that the first feedback network 101 can detect and respond to the ESD event, thereby outputting the second level to ensure that the third NMOS transistor M3 is turned on to completely discharge the ESD current.
[0065] It can be understood that, in addition to the discharge transistor 103 (such as the third NMOS transistor M3) in series, other components such as resistors can also be connected in series in the static protection path between the first power supply end VDD and the second power supply end VSS.
[0066] In an optional embodiment, the first feedback network 101 includes a first transistor module 11 configured to be controlled by the discharge transistor 103 to be controlled to be turned on when the ESD event occurs, so that the first feedback network 101 outputs the second level.
[0067] In the embodiment, the first transistor module 11 can be in an off state when no ESD event occurs, so that the first feedback network 101 outputs a first level.
[0068] In the exemplary embodiment, the first transistor module 11 can include one or more transistors, and can include NMOS tubes and / or PMOS tubes. For details, refer to the above description of the transistor, which will not be repeated here. It can be understood that the first transistor module 11 can include other components in addition to the transistor, such as resistors.
[0069] In an optional embodiment, the first feedback network 101 includes a first NMOS tube M1 and a first resistor Rn.
[0070] The gate of the first NMOS tube M1 is connected to the control end of the discharge transistor 103; the source of the first NMOS tube M1 is connected to the second power supply end VSS; the drain of the first NMOS tube M1 is connected to the first end of the first resistor Rn, and is configured to output the second level; and the second end of the first resistor Rn is connected to the first power supply end VDD.
[0071] In the embodiment, the gate of the first NMOS tube M1 can be connected to the gate of a third NMOS tube M3. When the chip is normally powered on, the first level can be output through the first end of the first resistor Rn, i.e., the first feedback network 101 outputs the first level.
[0072] The first resistor Rn can be a single resistor, or a series and / or parallel connection of multiple resistors, and can also be a passive resistor network or an active resistor network including resistors, capacitors, inductors, etc. By voltage division of the first resistor Rn, it is ensured that the output level of the first feedback network 101 is within a preset range, thereby improving the safety and stability of the circuit.
[0073] In an optional embodiment, the second feedback network 102 includes a second transistor module 21 configured to be turned on under the control of the second level to output the drive level to the control end of the discharge transistor 103, so that the control end of the discharge transistor 103 is maintained at the drive level in the case of an electrostatic discharge event.
[0074] In the embodiment, the second transistor module 21 can be turned off under the control of the first level output by the first feedback network 101, so that the discharge transistor 103 is turned off.
[0075] In this way, in the case of an electrostatic discharge event, the drive level is fed back to the control end of the discharge transistor 103 through the second transistor module 21, which maintains and ensures the opening of the discharge transistor 103, so that the electrostatic charge can be completely discharged.
[0076] In the example embodiment, the second transistor module 21 can include one or more transistors, and can include NMOS transistors and / or PMOS transistors. For details, refer to the above description of the transistors, which will not be repeated here. It can be understood that the second transistor module 21 can include other components in addition to the transistors, such as resistors, etc.
[0077] In an optional embodiment, the second feedback network 102 includes a second PMOS transistor M2 and a second resistor Rp.
[0078] The gate of the second PMOS transistor M2 is configured to obtain the second level. The source of the second PMOS transistor M2 is connected to the first power supply end VDD. The drain of the second PMOS transistor M2 is connected to the first end of the second resistor Rp, and is configured to output the driving level. The second end of the second resistor Rp is connected to the second power supply end VSS.
[0079] In the embodiment, the drain of the second PMOS transistor M2 can be connected to the gate of the third NMOS transistor M3.
[0080] The second resistor Rp can be a single resistor, or a series and / or parallel connection of multiple resistors, or a passive resistor network including resistors, capacitors, inductors, etc., or an active resistor network, etc. Through the second resistor Rp, the level at the control end of the discharge transistor 103 can be stabilized when the chip is normally powered on, and the discharge transistor 103 is ensured to be in an off state, thereby improving the stability of the circuit.
[0081] Reference Figure 2 When an ESD event occurs between the first power supply end VDD and the second power supply end VSS, the parasitic capacitance of the discharge transistor 103, such as the third NMOS transistor M3 of large size, causes the potential at point A to rise, causing the first NMOS transistor M1 to turn on. The turned-on first NMOS transistor M1 causes the potential at point B to become low, causing the second PMOS transistor M2 to turn on and start charging point A to maintain the high potential of point A, ensuring the opening of the third NMOS transistor M3 and the complete discharge of the ESD current. Therefore, by using the parasitic capacitance of the discharge transistor and the feedback network of the first resistor Rn / first NMOS transistor M1 and the second PMOS transistor M2 / second resistor Rp, a cross feedback structure is formed, which can open the discharge channel and achieve complete discharge of static charges.
[0082] Figure 3 FIG. 2 shows a circuit schematic diagram of an example of the power clamping circuit in the embodiment. As shown in the figure, the power clamping circuit further includes:
[0083] The feedback circuit 104 is configured to respond to an ESD event faster than the first feedback network 101 under the action of the parasitic capacitance of the discharge transistor 103, so as to switch the output from the first level to the second level in time prior to the first feedback network 101.
[0084] Therefore, by adding the feedback circuit to the first feedback network and the second feedback network used in the power clamp circuit, the feedback circuit can respond to the ESD event faster than the first feedback network and the second feedback network, and can respond to the change caused by the ESD event quickly, so that the discharge capability of the power clamp circuit is more robust under the same ESD level.
[0085] It should be understood that the feedback circuit 104 can be similar to the first feedback network 101, and can have a first working state outputting a first level and a second working state outputting a second level. In some examples, the first level can be a high level, and the second level can be a low level accordingly, but is not limited thereto. In other examples, the first level can also be a low level, and the second level can be a high level accordingly, which can be configured according to the controlled level requirement of the second feedback network 102. Then, the specific structure of the feedback circuit 104 can be set according to actual requirements, for example, can be realized by a switching circuit composed of a switching device (such as a transistor) with fast response performance, or can be realized by other gate circuits, programmable control of a processor, etc.
[0086] In an optional embodiment, the feedback circuit 104 includes a third transistor module 41 and a fourth transistor module 42 connected in series between the first power supply end VDD and the second power supply end VSS.
[0087] The third transistor module 41 and the fourth transistor module 42 are respectively configured to be controlled by the discharge transistor 103, so that in the case of an ESD event, the third transistor module 41 is controlled to be turned off, and the fourth transistor module 42 is controlled to be turned on, so that the feedback circuit 104 outputs the second level in time prior to the first feedback network 101.
[0088] In the embodiment of the application, when no ESD event occurs, the third transistor module 41 can be in an on state, and the fourth transistor module 42 can be in an off state, so that the feedback circuit 104 outputs the first level.
[0089] In this way, the response speed of switching from the first level to output the second level is improved through the third transistor module 41 and the fourth transistor module 42, and the speed of responding to the ESD event is improved.
[0090] In the exemplary embodiments, the third transistor module 41 and the fourth transistor module 42 can each include a single or multiple transistors, and can include NMOS tubes and / or PMOS tubes. For details, refer to the above description of the transistors, which will not be repeated here. It can be understood that, in addition to the transistors, the third transistor module 41 and the fourth transistor module 42 can also include other components such as resistors.
[0091] In an optional embodiment, the feedback circuit 104 includes a fourth PMOS tube M4 and a fifth NMOS tube M5.
[0092] The gate of the fourth PMOS tube M4 and the gate of the fifth NMOS tube M5 are respectively connected with the control end of the discharge transistor 103; the source of the fourth PMOS tube M4 is connected with the first power supply end VDD; the source of the fifth NMOS tube M5 is connected with the second power supply end VSS; the drain of the fourth PMOS tube M4 is connected with the drain of the fifth NMOS tube M5, and is configured to output the second level.
[0093] In the embodiments of the present application, the gate of the fourth PMOS tube M4 and the gate of the fifth NMOS tube M5 can be respectively connected with the gate of the third NMOS tube M3. When the chip is normally powered on, the first level can be output through the drain of the fourth PMOS tube M4, i.e., the feedback circuit 104 outputs the first level.
[0094] Reference Figure 3 When the ESD occurs between the first power supply end VDD and the second power supply end VSS, due to the discharge transistor 103, such as the third NMOS tube M3 of a large size, the parasitic capacitance of the third NMOS tube M3 causes the potential of point A to rise. After the potential of point A rises, the signal of point A is fed back to the gate end of the fourth PMOS tube M4 and the fifth NMOS tube M5. The fourth PMOS tube M4 is closed (turned off), and the fifth NMOS tube M5 is preferentially turned on and starts to pull down point B. Subsequently, the first NMOS tube M1 is also turned on after the fifth NMOS tube M5 is turned on. The first NMOS tube M1 and the fifth NMOS tube M5 together make the potential of point B become a low potential, so that the second PMOS tube M2 is turned on to charge point A and maintain the high potential of point A, ensuring that the third NMOS tube M3 is turned on to completely discharge the ESD current. Therefore, by using the parasitic capacitance of the discharge transistor and the cross feedback structure of the first resistor Rn / the first NMOS tube M1 / the second PMOS tube M2 / the second resistor Rp, and by using the feedback loop of the fourth PMOS tube M4 and the fifth NMOS tube M5, the change of the ESD can be quickly responded, and the ESD discharge capability is improved.
[0095] Thus, through the feedback circuit 104 composed of the fourth PMOS tube M4 and the fifth NMOS tube M5, the overall ESD discharge capacity can be made more robust at the same ESD level, and the robustness and reliability are further improved. Moreover, the power clamping circuit can make the ESD protection capacity more robust under the condition of basically the same area.
[0096] The embodiments of the present application also provide a chip, which comprises the power clamping circuit as described in the above embodiments. Thus, the safety and reliability of the chip are improved.
[0097] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes can also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, any combination of the technical features of the above embodiments can also be made to form additional embodiments of the present application which can not have been explicitly described. Therefore, the above embodiments only express several implementation manners of the present application and do not limit the protection scope of the patent of the present application.
Claims
1. A power supply clamp circuit, characterized by, The power supply clamping circuit comprises: a discharge transistor coupled between the first power supply terminal and the second power supply terminal to provide an electrostatic discharge path between the first power supply terminal and the second power supply terminal; a first feedback network configured to switch the output from a first level to a second level in response to an electrostatic discharge event occurring under the action of a parasitic capacitance of the discharge transistor; and a second feedback network configured to be turned on under the control of the second level to provide a drive level to a control terminal of the discharge transistor, so that the discharge transistor is turned on to conduct the electrostatic discharge path for discharging electrostatic charge.
2. The power supply clamping circuit of claim 1, wherein the discharge transistor comprises a third NMOS transistor; a drain of the third NMOS transistor is connected to the first power supply terminal, and a source of the third NMOS transistor is connected to the second power supply terminal; a gate of the third NMOS transistor is connected to the first feedback network and the second feedback network, respectively, to control the first feedback network to output the second level in the case of an electrostatic discharge event, and to obtain the drive level output by the second feedback network.
3. The power supply clamping circuit of claim 1, wherein the first feedback network comprises a first transistor module configured to be controlled by the discharge transistor to be turned on in the case of an electrostatic discharge event, so that the first feedback network outputs the second level.
4. The power supply clamping circuit of claim 1, wherein the first feedback network comprises a first NMOS transistor and a first resistor; a gate of the first NMOS transistor is connected to the control terminal of the discharge transistor; a source of the first NMOS transistor is connected to the second power supply terminal; a drain of the first NMOS transistor is connected to a first end of the first resistor and is configured to output the second level; and a second end of the first resistor is connected to the first power supply terminal.
5. The power supply clamping circuit of claim 1, wherein the second feedback network comprises a second transistor module configured to be turned on under the control of the second level to output the drive level to the control terminal of the discharge transistor, so that the control terminal of the discharge transistor is maintained at the drive level in the case of an electrostatic discharge event.
6. The power supply clamping circuit of claim 1, wherein the second feedback network comprises a second PMOS transistor and a second resistor; a gate of the second PMOS transistor is configured to obtain the second level; a source of the second PMOS transistor is connected to the first power supply terminal; a drain of the second PMOS transistor is connected to a first end of the second resistor and is configured to output the drive level; and a second end of the second resistor is connected to the second power supply terminal. The power supply clamping circuit further comprises:
7. The power clamp circuit of any of claims 1-6, wherein, a feedback circuit configured to respond to an electrostatic discharge event faster than the first feedback network under the action of the parasitic capacitance of the discharge transistor, to switch the output from the first level to the second level in time before the first feedback network.
8. The power supply clamping circuit of claim 7, wherein The feedback circuit comprises a third transistor module and a fourth transistor module connected in series between the first power terminal and the second power terminal; The third transistor module and the fourth transistor module are respectively configured to be controlled by the discharge transistor, so that in the case of an electrostatic discharge event, the third transistor module is controlled to be turned off, and the fourth transistor module is controlled to be turned on, so that the feedback circuit outputs the second level in time before the first feedback network.
9. The power clamp circuit of claim 7, wherein, The feedback circuit comprises a fourth PMOS tube and a fifth NMOS tube; The gate of the fourth PMOS tube and the gate of the fifth NMOS tube are respectively connected with the control terminal of the discharge transistor; the source of the fourth PMOS tube is connected with the first power terminal; The source of the fifth NMOS tube is connected with the second power terminal; the drain of the fourth PMOS tube is connected with the drain of the fifth NMOS tube, and is configured to output the second level.
10. A chip, characterized by The chip comprises the power clamp circuit according to any one of claims 1-9.