Display device and optical device

Abstract

The utility model relates to a display device and an optical device capable of improving brightness balance while improving transmissivity of a short wavelength area. The display device comprises a substrate (SSUB); a first electrode (AND) on the substrate; a light emitting layer on the first electrode; a second electrode (CAT) on the light emitting layer; and a wire grid polarizer (WGP) on the second electrode, the wire grid polarizer including a plurality of grid patterns (GP), a pitch between the grid patterns disposed corresponding to a blue light emitting region of a blue pixel providing blue light being smaller than a pitch between the grid patterns disposed corresponding to a light emitting region of a pixel providing light different from the blue light.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of display devices, in particular to a kind of display device and optical device that can improve luminance balance while improving the transmittance of short wavelength region. BACKGROUND

[0002] A head mounted display (HMD) is an image display device that forms a focal point at a close distance in front of a user's eyes in the form of glasses or a helmet worn on the user's head. The head mounted display can implement virtual reality (VR) or augmented reality (AR).

[0003] The head mounted display enlarges and displays the image displayed by a small display device using a plurality of lenses. Due to this, the display device suitable for the head mounted display needs to provide a high-resolution image, such as an image having a resolution of 3000 PPI (Pixels Per Inch) or more. For this, as a display device suitable for the head mounted display, OLEDoS (Organic Light Emitting Diode on Silicon) is used, which is a small organic light emitting display device having high resolution. The OLEDoS is a device that displays an image by configuring an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a CMOS (Complementary Metal Oxide Semiconductor) is configured.

[0004] Korean Patent Laid-Open Publication No. 10-2018-0023102 (Published on March 7, 2018) SUMMARY

[0005] The utility model aims at providing a kind of display device and optical device that can improve luminance balance while improving the transmittance of short wavelength region.

[0006] The technical problem of the utility model is not limited to the above-mentioned technical problem, and another technical problem not mentioned can be clearly understood by those skilled in the art from the following description.

[0007] A display device according to an embodiment of the present application for achieving the above object includes: a substrate S SUB; a first electrode AND on the substrate; a light emitting layer on the first electrode; a second electrode CAT on the light emitting layer; and a wire grid polarizer WGP on the second electrode, the wire grid polarizer including a plurality of grid patterns, a pitch between grid patterns configured corresponding to a blue light emitting region of a blue pixel providing blue light being smaller than a pitch between grid patterns configured corresponding to a light emitting region of a pixel providing a different light from the blue light.

[0008] The pixel providing the different light includes: a green pixel providing green light; and a red pixel providing red light.

[0009] The pitch between grid patterns configured corresponding to a green light emitting region of the green pixel and the pitch between grid patterns configured corresponding to a red light emitting region of the red pixel are the same.

[0010] The display device further includes a phase retardation layer QWP between the second electrode and the wire grid polarizer.

[0011] The display device further includes a color filter layer CFL between the second electrode and the wire grid polarizer.

[0012] The color filter layer includes: a red color filter CF1 transmitting red light; a green color filter CF2 transmitting green light; and a blue color filter CF3 transmitting blue light.

[0013] The pitch between grid patterns configured corresponding to the blue color filter is smaller than the pitch between grid patterns configured corresponding to the green color filter.

[0014] The pitch between grid patterns configured corresponding to the blue color filter is smaller than the pitch between grid patterns configured corresponding to the red color filter.

[0015] The pitch between grid patterns configured corresponding to the blue light emitting region is 50 nm to 90 nm.

[0016] The pitch between grid patterns configured corresponding to the light emitting region of the pixel providing the different light is 100 nm to 150 nm.

[0017] At least one of the grid patterns of the wire grid polarizer has a thickness of 100 nm to 300 nm.

[0018] The wire grid polarizer is composed of a substance including at least one of aluminum (Al), silver (Ag), and gold (Au).

[0019] The display device further includes a lens layer LSL between the second electrode and the wire grid polarizer.

[0020] The display device further includes a lens layer on the wire grid polarizer.

[0021] In addition, an optical device according to an embodiment of the present application for achieving the above object includes: a display device; and a light path conversion member on the display device, the display device including: a substrate; a first electrode on the substrate; a light emitting layer on the first electrode; a second electrode on the light emitting layer; and a wire grid polarizer on the second electrode, the wire grid polarizer including a plurality of grid patterns, a pitch between grid patterns configured corresponding to a blue light emitting region of a blue pixel providing blue light being smaller than a pitch between grid patterns configured corresponding to a light emitting region of a pixel providing light different from the blue light.

[0022] Details of other embodiments are included in the detailed description and the accompanying drawings.

[0023] According to the display device and the optical device according to an embodiment of the present application, it is possible to improve the luminance balance while improving the transmittance in the short wavelength region.

[0024] In addition, the display device and the optical device according to an embodiment can ensure an align-free structure maintained according to the same pitch of red and blue pixels in a high resolution pixel configuration structure, and can improve the alignment margin. Therefore, it is possible to improve the processability.

[0025] On the other hand, the effects obtainable in the present application are not limited to those mentioned above, and other effects that are not mentioned will become apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is an exploded perspective view illustrating a display device according to an embodiment.

[0027] Figure 2 is a layout view illustrating Figure 1 an example of a display panel.

[0028] Figure 3 is an equivalent circuit diagram of a first pixel according to an embodiment.

[0029] Figure 4 is a layout view illustrating an example of a display panel according to an embodiment.

[0030] Figure 5 is a layout view illustrating Figure 4Layout diagram of an embodiment of a display area of the display device.

[0031] Figure 6 is a cross-sectional view showing an example of a display panel taken along Figure 5 X-X' of the display device 1.

[0032] Figure 7 is a cross-sectional view showing an example of a display panel taken along Figure 5 X-X' of the display device 1.

[0033] Figure 8 is a cross-sectional view showing an example of a display panel taken along Figure 5 X-X' of the display device 1.

[0034] Figure 9 is a cross-sectional view showing an example of a display panel taken along Figure 5 X-X' of the display device 1.

[0035] Figure 10 is a diagram for explaining an effect of the display device according to an embodiment.

[0036] Figure 11 is a perspective view showing a head-mounted display device according to an embodiment.

[0037] Figure 12 is an exploded perspective view showing an example of a head-mounted display device of the display device 1. Figure 11

[0038] Figure 13 is a perspective view showing a head-mounted display device according to an embodiment.

[0039] (Explanation of Reference Numerals)

[0040] EA1-EA3: First to third light-emitting areas

[0041] PX1-PX3: First to third pixels

[0042] WGP: Wire grid polarizer

[0043] GP: Grid pattern

[0044] P1-P3: First to third pitches

[0045] TRC: Trench

[0046] DR1-DR3: First to third directions DETAILED DESCRIPTION

[0047] ​The advantages and features of the present application and the method of realizing them will become apparent from the following detailed embodiments described hereinafter with reference to the attached drawings. However, the present application is not limited to the following disclosed embodiments, which will be realized in various forms different from each other, and the present embodiments are only to make the disclosure of the present application complete, and to provide a complete description of the scope of the present application to those having ordinary knowledge in the technical field to which the present application belongs, and the present application is only defined by the scope of the claims.

[0048] Reference to elements or layers "on" other elements or layers means directly on the other element or intervening layers or elements therebetween throughout the specification. Like reference numbers refer to like elements throughout the specification. Shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for explaining the embodiments are exemplary, and thus the present application is not limited to the illustrated matters.

[0049] Although first, second, and the like are used for describing various constituent elements, it is needless to say that the constituent elements are not limited by these terms. The terms are only used to distinguish one constituent element from other constituent elements. Thus, it is needless to say that the first constituent element mentioned below can also be the second constituent element within the technical idea of the present application.

[0050] It is possible that various features of each of the embodiments of the present application are partially or entirely combined with or combined with each other, and various linkages and driving are possible in the technical field, and each embodiment can be implemented independently with respect to each other or can be implemented together in an associated relationship.

[0051] The specific embodiments will be described below with reference to the accompanying drawings.

[0052] Figure 1 is an exploded perspective view showing a display device according to an embodiment. Figure 2 is a layout view showing Figure 1 a display panel. Figure 3 is an equivalent circuit diagram of a first pixel according to an embodiment.

[0053] Figure 1 is an exploded perspective view showing a display device according to an embodiment. Figure 2 is a block diagram showing a display device according to an embodiment.

[0054] Referring to Figure 1 and Figure 2The display device 10 according to an embodiment is a device that displays a video or a still image. The display device 10 according to an embodiment can be applied to a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic book, an e-book, a PMP (Portable Multimedia Player), a navigation, a UMPC (Ultra Mobile PC), etc. For example, the display device 10 according to an embodiment can be applied to a display of a television, a notebook computer, a monitor, a billboard, or an IOT (Internet Of Things). In addition, the display device 10 according to an embodiment can be applied to a smart watch, a watch phone, a head mounted display (HMD) for implementing virtual reality and augmented reality.

[0055] The display device 10 according to an embodiment includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0056] The display panel 100 can be configured in a planar form similar to a quadrangle. For example, the display panel 100 can have a planar form similar to a quadrangle having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. A corner portion in which the short side in the first direction DR1 and the long side in the second direction DR2 of the display panel 100 intersect can be rounded to have a predetermined curvature or formed as a right angle. The planar form of the display panel 100 is not limited to a quadrangle, and can be formed similar to other polygons, a circle, or an ellipse. The planar form of the display device 10 can follow the planar form of the display panel 100, but embodiments of the present specification are not limited thereto.

[0057] The display panel 100 is configured to display an image. Figure 2 The display panel 100 includes a display area DAA in which an image is displayed and a non-display area NDA in which an image is not displayed.

[0058] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0059] The plurality of pixels PX can be arranged in a matrix form in the first direction DR1 and the second direction DR2. The plurality of scan lines SL and the plurality of light emitting control lines EL can extend in the first direction DR1 and be arranged in the second direction DR2. The plurality of data lines DL can extend in the second direction DR2 and be arranged in the first direction DR1.

[0060] The plurality of scan lines SL includes a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of light emitting control lines EL includes a plurality of first light emitting control lines EL1 and a plurality of second light emitting control lines EL2.

[0061] The plurality of unit pixels PX includes a plurality of pixels PX1, PX2, PX3. The plurality of pixels PX1, PX2, PX3 can be arranged in a matrix form in the first direction DR1 and the second direction DR2. Figure 3 The plurality of pixel transistors can be formed by a semiconductor process and arranged on a semiconductor substrate (SSUB). For example, the plurality of pixel transistors of the data driving part 700 can be formed by a CMOS. Figure 7 The plurality of pixel transistors can be formed by a semiconductor process and arranged on a semiconductor substrate (SSUB). For example, the plurality of pixel transistors of the data driving part 700 can be formed by a CMOS.

[0062] Each of the plurality of pixels PX1, PX2, PX3 can be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines EBL, any one of the plurality of first light emitting control lines EL1, any one of the plurality of second light emitting control lines EL2, and any one of the plurality of data lines DL. Each of the plurality of pixels PX1, PX2, PX3 can receive supply of a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and cause the light emitting element to emit light according to the data voltage.

[0063] The non-display area NDA includes the scan driving part 610, the light emitting driving part 620, and the data driving part 700.

[0064] The scan driving part 610 includes a plurality of scan transistors, and the light emitting driving part 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors can be formed by a semiconductor process and arranged on a semiconductor substrate (SSUB). For example, the plurality of scan transistors and the plurality of light emitting transistors can be formed by a CMOS. Figure 7 The scan driving part 610 includes a plurality of scan transistors, and the light emitting driving part 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors can be formed by a semiconductor process and arranged on a semiconductor substrate (SSUB). For example, the plurality of scan transistors and the plurality of light emitting transistors can be formed by a CMOS. Figure 2The present embodiment is not limited to this. For example, the scan driving portion 610 and the emission driving portion 620 can be arranged on both the left and right sides of the display region DAA.

[0065] The scan driving portion 610 can include a write scan signal output portion 611, a control scan signal output portion 612, and a bias scan signal output portion 613. Each of the write scan signal output portion 611, the control scan signal output portion 612, and the bias scan signal output portion 613 can receive an input of a scan timing control signal SCS from the timing control circuit 400. The write scan signal output portion 611 can generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 400 and sequentially output the write scan signal to the write scan line GWL. The control scan signal output portion 612 can generate a control scan signal according to the scan timing control signal SCS and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output portion 613 can generate a bias scan signal according to the scan timing control signal SCS and sequentially output the bias scan signal to the bias scan line EBL.

[0066] The emission driving portion 620 includes a first emission control driving portion 621 and a second emission control driving portion 622. Each of the first emission control driving portion 621 and the second emission control driving portion 622 can receive an input of an emission timing control signal ECS from the timing control circuit 400. The first emission control driving portion 621 can generate a first emission control signal according to the emission timing control signal ECS and sequentially output the first emission control signal to the first emission control line EL1. The second emission control driving portion 622 can generate a second emission control signal according to the emission timing control signal ECS and sequentially output the second emission control signal to the second emission control line EL2.

[0067] The data driving portion 700 can include a plurality of data transistors formed by a semiconductor process and formed on a semiconductor substrate (SSUB). For example, the plurality of data transistors can be formed by CMOS. Figure 7

[0068] The data driving portion 700 can receive an input of digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driving portion 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the pixels PX1, PX2, PX3 can be selected by the write scan signal of the scan driving portion 610, and the data voltage can be supplied to the selected pixels PX1, PX2, PX3.

[0069] ​The heat dissipation layer 200 can overlap with the display panel 100 on a third direction DR3 in the thickness direction. The heat dissipation layer 200 can be disposed on one side of the display panel 100, such as the back side. The heat dissipation layer 200 serves to dissipate heat generated in the display panel 100. The heat dissipation layer 200 can include metals with high thermal conductivity, such as graphite, silver (Ag), copper (Cu), or aluminum (Al).

[0070] The circuit board 300 can be electrically connected to the first pad portion of the display panel 100 using conductive adhesive components such as anisotropic conductive film. Figure 4 Multiple first pads of PDA1 Figure 4 (PD1). Circuit board 300 can be a flexible printed circuit board or a flexible film made of a flexible material. Figure 1 The illustration shows the circuit board 300 unfolded, but the circuit board 300 can be bent. In this case, one end of the circuit board 300 can be disposed on the back of the display panel 100 and / or the back of the heat dissipation layer 200. One end of the circuit board 300 can be connected to the first pad portion of the display panel 100 using conductive adhesive components. Figure 4 Multiple first pads of PDA1 Figure 4 The opposite end of the other end of the PD1) circuit board 300.

[0071] The timing control circuit 400 can receive digital video data and timing signals from an external source. Based on the timing signals, the timing control circuit 400 generates a scan timing control signal SCS, a light emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver unit 610 and the light emission timing control signal ECS to the light emission driver unit 620. The timing control circuit 400 can also output digital video data and the data timing control signal DCS to the data driver unit 700.

[0072] The power supply circuit 500 can generate multiple panel driving voltages based on an external power supply voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT and supply them to the display panel 100. A description of the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT is provided below. Figure 3 This will be discussed later.

[0073] The timing control circuit 400 and the power supply circuit 500 can be formed as integrated circuits (ICs) and attached to one side of the circuit board 300. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. In addition, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0074] In addition, each of the timing control circuit 400 and the power supply circuit 500 can be disposed in the non-display area NDA of the display panel 100, similar to the scan driving part 610, the emission driving part 620, and the data driving part 700. In this case, the timing control circuit 400 can include a plurality of timing transistors, and each of the power supply circuits 500 can include a plurality of power supply transistors. The plurality of timing transistors and the plurality of power supply transistors can be formed by a semiconductor process and formed on a semiconductor substrate (SSUB). For example, the plurality of timing transistors and the plurality of power supply transistors can be formed by CMOS. Each of the timing control circuit 400 and the power supply circuit 500 can be disposed between the data driving part 700 and the first pad part (PDA1). Figure 7 Figure 4

[0075] Figure 3 is an equivalent circuit diagram of a first pixel according to an embodiment.

[0076] Referring to Figure 3 , the first pixel PX1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. In addition, the first pixel PX1 can be connected to the first driving voltage line VSL to which the first driving voltage VSS corresponding to a low potential voltage is applied, the second driving voltage line VDL to which the second driving voltage VDD corresponding to a high potential voltage is applied, and the third driving voltage line VIL to which the third driving voltage VINT corresponding to an initialization voltage is applied. That is, the first driving voltage line VSL can be a low potential voltage line, the second driving voltage line VDL can be a high potential voltage line, and the third driving voltage line VIL can be an initialization voltage line. At this time, the first driving voltage VSS can be a voltage lower than the third driving voltage VINT. The second driving voltage VDD can be a voltage higher than the third driving voltage VINT.

[0077] ​​The first pixel PX1 includes a plurality of transistors T1 to T6, a light emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0078] The light emitting element LE emits light according to a drive current Ids flowing in a channel of the first transistor T1. An amount of light emitted by the light emitting element LE can be proportional to the drive current Ids. The light emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. It can be that a first electrode of the light emitting element LE is connected to a drain electrode of the fourth transistor T4, and a second electrode of the light emitting element LE is connected to the first drive voltage line VSL. It can be that the first electrode of the light emitting element LE is an anode electrode, and the second electrode of the light emitting element LE is a cathode electrode. The light emitting element LE can be an organic light emitting diode including the first electrode, the second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode, but embodiments of the present specification are not limited thereto. For example, the light emitting element LE can be an inorganic light emitting element including the first electrode, the second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode, in which case the light emitting element LE can be a micro light emitting diode.

[0079] The first transistor T1 can be a drive transistor that controls a source-drain current Ids (hereinafter referred to as a "drive current") flowing between a source electrode and a drain electrode according to a voltage applied to a gate electrode. The first transistor T1 includes the gate electrode connected to the first node N1, the source electrode connected to the drain electrode of the sixth transistor T6, and the drain electrode connected to the second node N2.

[0080] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 connects one electrode of the first capacitor CP1 to the data line DL by being turned on by a write scan signal of the write scan line GWL. Due to this, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 includes the gate electrode connected to the write scan line GWL, the source electrode connected to the data line DL, and the drain electrode connected to one electrode of the first capacitor CP1.

[0081] The third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 connects the first node N1 to the second node N2 by being turned on by a write control signal of the scan line GCL. Due to this, the gate electrode and the source electrode of the first transistor T1 are connected, and thus the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0082] The fourth transistor T4 can be turned on between the second node N2 and the third node N3. The fourth transistor T4 connects the second node N2 to the third node N3 by being turned on by a first light emitting control signal of the first light emitting control line EL1. Due to this, the driving current of the first transistor T1 can be supplied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first light emitting control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0083] The fifth transistor T5 can be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 connects the third node N3 to the third driving voltage line VIL by being turned on by a bias scan signal of the bias scan line EBL. Due to this, the first electrode of the light emitting element LE can be applied with the third driving voltage VINT of the third driving voltage line VIL. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0084] The sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 connects the source electrode of the first transistor T1 to the second driving voltage line VDL by being turned on by a second light emitting control signal of the second light emitting control line EL2. Due to this, the source electrode of the first transistor T1 can be applied with the second driving voltage VDD of the second driving voltage line VDL. The sixth transistor T6 includes a gate electrode connected to the second light emitting control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0085] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0086] A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second drive voltage line VDL.

[0087] The first node N1 is a contact point of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is a contact point of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a contact point of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0088] Each of the first to sixth transistors T1 to T6 can be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). For example, each of the first to sixth transistors T1 to T6 can be a P-type MOSFET, but embodiments of the present specification are not limited thereto. Each of the first to sixth transistors T1 to T6 can be an N-type MOSFET. In addition, it can be that each of a part of the transistors among the first to sixth transistors T1 to T6 is a P-type MOSFET, and each of the remaining transistors is an N-type MOSFET.

[0089] In Figure 3 , it is exemplified that the first pixel PX1 includes six transistors T1 to T6 and two capacitors CP1 and CP2, but it should be noted that the equivalent circuit diagram of the first pixel PX1 is not limited to Figure 3 that illustrated. For example, the number of transistors and the number of capacitors of the first pixel PX1 are not limited to Figure 3 that illustrated.

[0090] In addition, the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 can be substantially the same as the equivalent circuit diagram of the first pixel PX1 described in conjunction with Figure 3 . Due to this, the description about the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 is omitted in the present specification.

[0091] Figure 4 is a layout diagram showing an example of a display panel according to an embodiment.

[0092] Referring to Figure 4The display area DAA of the display panel 100 according to an embodiment includes a plurality of pixels PX arranged in a matrix form. The non-display area NDA of the display panel 100 according to an embodiment includes a scan driving part 610, a light emitting driving part 620, a data driving part 700, a first pad part PDA1, and a second pad part PDA2.

[0093] The scan driving part 610 can be disposed at a first side of the display area DAA, and the light emitting driving part 620 can be disposed at a second side of the display area DAA. For example, the scan driving part 610 can be disposed at one side of a first direction DR1 of the display area DAA, and the light emitting driving part 620 can be disposed at the other side of the first direction DR1 of the display area DAA. That is, the scan driving part 610 can be disposed at a left side of the display area DAA, and the light emitting driving part 620 can be disposed at a right side of the display area DAA. However, embodiments of the present specification are not limited thereto, and the scan driving part 610 and the light emitting driving part 620 can be disposed at both the first side and the second side of the display area DAA.

[0094] The first pad part PDA1 can include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 through conductive adhesive members. The first pad part PDA1 can be disposed at a third side of the display area DAA. For example, the first pad part PDA1 can be disposed at one side of a second direction DR2 of the display area DAA. That is, the first pad part PDA1 can be disposed at a lower side of the display area DAA.

[0095] The first pad part PDA1 can be disposed outside the data driving part 700 in the second direction DR2. That is, the first pad part PDA1 can be disposed closer to an edge of the display panel 100 than the data driving part 700.

[0096] The second pad part PDA2 can include a plurality of second pads PD2 corresponding to inspection pads for inspecting whether the display panel 100 operates normally. The plurality of second pads PD2 can be connected to a jig or a probe or connected to an inspection circuit board in an inspection process. The inspection circuit board can be a printed circuit board of a hard material or a flexible printed circuit board having a soft material.

[0097] The first distribution circuit 710 distributes a data voltage applied through the first pad portion PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 can distribute a data voltage applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or more) data lines DL, and as a result, the number of the plurality of first pads PD1 can be reduced. The first distribution circuit 710 can be disposed at a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed at one side of the second direction DR2 of the display area DAA. That is, the first distribution circuit 710 can be disposed at a lower side of the display area DAA.

[0098] The second distribution circuit 720 distributes a signal applied through the second pad portion PDA2 to the scan driving portion 610, the light emitting driving portion 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be a structure for checking the operation of each of the pixels PX of the display area DAA. The second distribution circuit 720 can be disposed at a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed at the other side of the second direction DR2 of the display area DAA. That is, the second distribution circuit 720 can be disposed at an upper side of the display area DAA.

[0099] Figure 5 is a layout view illustrating an embodiment of a display area of Figure 4

[0100] Referring to Figure 5 , each of the plurality of unit pixels UPX includes a first light emitting area EA1 that is a light emitting area of the first pixel PX1, a second light emitting area EA2 that is a light emitting area of the second pixel PX2, and a third light emitting area EA3 that is a light emitting area of the third pixel PX3. In other words, the unit pixel UPX can include a unit light emitting area UEA including the aforementioned first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3.

[0101] Referring to Figure 5 , each of the plurality of pixels PX includes a first light emitting area EA1 that is a light emitting area of the first pixel PX1, a second light emitting area EA2 that is a light emitting area of the second pixel PX2, and a third light emitting area EA3 that is a light emitting area of the third pixel PX3.

[0102] Each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 can have a planar form of a polygon, a circle, an ellipse, or an irregular shape, but the form of each light emitting area EA1, EA2, EA3 is not limited thereto.

[0103] ​The maximum length of the first direction DR1 of the first light emitting region EA1 can be smaller than the maximum length of the first direction DR1 of the second light emitting region EA2 and the maximum length of the first direction DR1 of the third light emitting region EA3. The maximum length of the first direction DR1 of the second light emitting region EA2 and the maximum length of the first direction DR1 of the third light emitting region EA3 can be substantially the same.

[0104] The maximum length of the second direction DR2 of the first light emitting region EA1 can be longer than the maximum length of the second direction DR2 of the second light emitting region EA2 and the maximum length of the second direction DR2 of the third light emitting region EA3. The maximum length of the second direction DR2 of the second light emitting region EA2 can be longer than the maximum length of the second direction DR2 of the third light emitting region EA3. The maximum length of the second direction DR2 of the first light emitting region EA1 can be greater than the maximum length of the second direction DR2 of the second light emitting region EA2.

[0105] The first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 can have a planar form of a polygon, a circle, an ellipse, or an indefinite shape. Figure 5 The first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 can have a planar form of a hexagon formed of six straight lines, but embodiments of the present specification are not limited thereto. The first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 can have a planar form of other polygons other than a hexagon, a circle, an ellipse, or an indefinite shape.

[0106] The first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 can have a planar form of a hexagon formed of six straight lines, but embodiments of the present specification are not limited thereto. The first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 can have a planar form of other polygons other than a hexagon, a circle, an ellipse, or an indefinite shape. Figure 5 In each of the plurality of pixels PX, the first light emitting region EA1 and the second light emitting region EA2 can be adjacent in the first direction DR1. In addition, the first light emitting region EA1 and the third light emitting region EA3 can be adjacent in the first direction DR1. In addition, the second light emitting region EA2 and the third light emitting region EA3 can be adjacent in the second direction DR2. The area of the first light emitting region EA1, the area of the second light emitting region EA2, and the area of the third light emitting region EA3 can be different.

[0107] The first light emitting region EA1 can emit light of a first color, the second light emitting region EA2 can emit light of a second color, and the third light emitting region EA3 can emit light of a third color. Here, the light of the first color can be light of a blue band, the second light can be light of a green band, and the third light can be light of a red band. For example, the blue band can refer to light having a main peak wavelength included in a band of approximately 380 nm to 480 nm, the green band can refer to light having a main peak wavelength included in a band of approximately 480 nm to 560 nm, and the red band can refer to light having a main peak wavelength included in a band of approximately 600 nm to 750 nm.

[0108] The first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 can have a planar form of a hexagon formed of six straight lines, but embodiments of the present specification are not limited thereto. The first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 can have a planar form of other polygons other than a hexagon, a circle, an ellipse, or an indefinite shape. Figure 5Each of the plurality of pixels PX is illustrated as including three light emitting regions EA1, EA2, and EA3, but embodiments of the present specification are not limited thereto. That is, each of the plurality of pixels PX can also include four light emitting regions.

[0109] In addition, the configuration of the light emitting regions of the plurality of pixels PX is not limited to Figure 5 as illustrated. For example, the light emitting regions of the plurality of pixels PX can be configured in a stripe structure in which the light emitting regions are arranged in the first direction DR1, a diamond structure in which the light emitting regions have a diamond arrangement, or a hexagonal structure in which the light emitting regions have a hexagonal arrangement in a planar form of a hexagon. Figure 6

[0110] Figure 6 is a cross-sectional view showing an example of the display panel 100 taken along the X-X' of Figure 5

[0111] Referring to Figure 6 , the display panel 100 can include a semiconductor back plate SBP, an emission element back plate EBP, a display element layer EML, a sealing layer TFE, and an optical layer OPL.

[0112] The semiconductor back plate SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. The plurality of pixel transistors PTR can be the first to sixth transistors T1 to T6 described in conjunction with Figure 3

[0113] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. A plurality of well regions WA can be configured on the upper surface of the semiconductor substrate SSUB. The plurality of well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the first type of impurity described above. For example, in the case where the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. Alternatively, in the case where the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0114] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode, and a channel region CH configured between the source region SA and the drain region DA.

[0115] ​​​​A lower insulating film BINS can be provided between the gate electrode GE and the well region WA. A side insulating film SINS can be provided on a side of the gate electrode GE. The side insulating film SINS can be provided on the lower insulating film BINS.

[0116] Each of the source region SA and the drain region DA can be a region doped with a first type impurity. The gate electrode GE of the pixel transistor PTR can overlap the well region WA in the third direction DR3. The channel region CH can overlap the gate electrode GE in the third direction DR3. The source region SA can be provided on one side of the gate electrode GE, and the drain region DA can be provided on the other side of the gate electrode GE.

[0117] Each of the plurality of well regions WA further includes a first low concentration impurity region LDD1 provided between the channel region CH and the source region SA, and a second low concentration impurity region LDD2 provided between the channel region CH and the drain region DA. The first low concentration impurity region LDD1 can be a region having a lower impurity concentration than the source region SA through the lower insulating film BINS. The second low concentration impurity region LDD2 can be a region having a lower impurity concentration than the drain region DA through the lower insulating film BINS. The distance between the source region SA and the drain region DA can be increased by the first low concentration impurity region LDD1 and the second low concentration impurity region LDD2. Thus, the length of the channel region CH of each of the pixel transistors PTR can be increased, and therefore, punch-through through a short channel and a hot carrier effect can be prevented.

[0118] The first semiconductor insulating film SINS1 can be provided on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be formed of a silicon carbon nitride (SiCN) or a silicon oxide (SiOx) type inorganic film, but embodiments of the present specification are not limited thereto.

[0119] The second semiconductor insulating film SINS2 can be provided on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be formed of a silicon oxide (SiOx) type inorganic film, but embodiments of the present specification are not limited thereto.

[0120] A plurality of contact terminals CTE can be provided on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE can be connected to any one of the gate electrode GE, the source region SA, and the drain region DA of each of the pixel transistors PTR through a hole that penetrates the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The plurality of contact terminals CTE can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them.

[0121] A third semiconductor insulating film SINS3 can be provided on the side surface of each of the plurality of contact terminals CTE. The upper surface of each of the plurality of contact terminals CTE can not be covered by the third semiconductor insulating film SINS3 and be exposed. The third semiconductor insulating film SINS3 can be formed of a silicon oxide (SiOx)-based inorganic film, but embodiments of the present specification are not limited thereto.

[0122] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as a polyimide. In this case, a thin film transistor can be provided on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that is not bent, and the polymer resin substrate can be a flexible substrate that can be bent or folded.

[0123] The light emitting element back plate EBP includes a plurality of conductive layers ML1 to ML8, a plurality of vias VA1 to VA9, and a plurality of insulating films INS1 to INS9. In addition, the light emitting element back plate EBP includes a plurality of insulating films INS1 to INS11 provided between the first to eighth conductive layers ML1 to ML8.

[0124] The first to eighth conductive layers ML1 to ML8 connect the plurality of contact terminals CTE exposed at the semiconductor back plate SBP to function to realize Figure 3 the circuit of the first pixel PX1 illustrated. For example, the first to sixth transistors T1 to T6, the connection of the first to sixth transistors T1 to T6, and the first and second capacitors C1 and C2 are realized by the first to eighth conductive layers ML1 to ML8, in the semiconductor back plate SBP in which only the first to sixth transistors T1 to T6 are formed. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4 and the source region corresponding to the source electrode of the fifth transistor T5 and the first electrode of the light emitting element LE is also realized by the first to eighth conductive layers ML1 to ML8.

[0125] A first insulating film INS1 can be disposed on the semiconductor back plate SBP. Each of the first vias VA1 can be connected to the contact terminal CTE exposed at the semiconductor back plate SBP through the first insulating film INS1. Each of the first conductive layers ML1 can be disposed on the first insulating film INS1 connected to the first via VA1.

[0126] A second insulating film INS2 can be disposed on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 can be connected to the exposed first conductive layer ML1 through the second insulating film INS2. Each of the second conductive layers ML2 can be disposed on the second insulating film INS2 connected to the second via VA2.

[0127] A third insulating film INS3 can be disposed on the second insulating film INS2 and the second conductive layer ML2. Each of the third vias VA3 can be connected to the exposed second conductive layer ML2 through the third insulating film INS3. Each of the third conductive layers ML3 can be disposed on the third insulating film INS3 connected to the third via VA3.

[0128] A fourth insulating film INS4 can be disposed on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth vias VA4 can be connected to the exposed third conductive layer ML3 through the fourth insulating film INS4. Each of the fourth conductive layers ML4 can be disposed on the fourth insulating film INS4 connected to the fourth via VA4.

[0129] A fifth insulating film INS5 can be disposed on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 can be connected to the exposed fourth conductive layer ML4 through the fifth insulating film INS5. Each of the fifth conductive layers ML5 can be disposed on the fifth insulating film INS5 connected to the fifth via VA5.

[0130] A sixth insulating film INS6 can be disposed on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 can be connected to the exposed fifth conductive layer ML5 through the sixth insulating film INS6. Each of the sixth conductive layers ML6 can be disposed on the sixth insulating film INS6 connected to the sixth via VA6.

[0131] A seventh insulating film INS7 can be disposed on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 can be connected to the exposed sixth conductive layer ML6 through the seventh insulating film INS7. Each of the seventh conductive layers ML7 can be disposed on the seventh insulating film INS7 connected to the seventh via VA7.

[0132] An eighth insulating film INS8 can be provided on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 can be connected to the exposed seventh conductive layer ML7 through the eighth insulating film INS8. Each of the eighth conductive layers ML8 can be provided on the eighth insulating film INS8, connected to the eighth via VA8.

[0133] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 can be composed of substantially the same substance. The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them. The first to eighth vias VA1 to VA8 can be composed of substantially the same substance. The first to eighth insulating films INS1 to ILD8 can be formed of a silicon oxide (SiOx)-based inorganic film, but embodiments of the present specification are not limited thereto.

[0134] Each of the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be greater than each of the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. Each of the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be approximately 10 nm, and the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be approximately 50 nm. Each of the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be approximately 50 nm. Each of the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6 can be approximately 10 nm.

[0135] Each of the thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be greater than each of the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. Each of the thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be greater than each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8. Each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8 can be greater than each of the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be substantially the same. For example, each of the thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be approximately 100 nm to 300 nm. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be approximately 200 nm. Each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8 can be approximately 100 nm to 300 nm.

[0136] The ninth insulating film INS9 can be disposed on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be formed of a silicon oxide (SiOx)-based inorganic film, but embodiments of the present specification are not limited thereto.

[0137] Each of the ninth vias VA9 can be connected to the exposed eighth conductive layer ML8 through the ninth insulating film INS9. The ninth via VA9 can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them. The thickness of the ninth via VA9 can be approximately 100 nm to 300 nm.

[0138] The display element layer EML can be disposed on the light emitting element back plate EBP. The display element layer EML can include a reflective electrode layer RL, tenth and eleventh insulating films INS10, INS11, tenth vias VA10, light emitting elements LE each including a first electrode AND, a light emitting stack ES, and a second electrode CAT, a pixel definition film PDL, and a plurality of trenches TRC.

[0139] The reflective electrode layer RL can be disposed on the ninth insulating film INS9. The reflective electrode layer RL can include at least one reflective electrode RL1, RL2, RL3, RL4. For example, the reflective electrode layer RL can be as described in FIG. 2A. Figure 6 The reflective electrode layer RL can include first to fourth reflective electrodes RL1, RL2, RL3, RL4.

[0140] Each of the first reflective electrodes RL1 can be disposed on the ninth insulating film INS9 and connected to the ninth via hole VA9. The first reflective electrode RL1 can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them. For example, the first reflective electrode RL1 can contain titanium nitride (TiN).

[0141] Each of the second reflective electrodes RL2 can be disposed on the first reflective electrode RL1. The second reflective electrode RL2 can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them. For example, the second reflective electrode RL2 can contain aluminum (Al).

[0142] Each of the third reflective electrodes RL3 can be disposed on the second reflective electrode RL2. The third reflective electrode RL3 can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them. For example, the third reflective electrode RL3 can contain titanium nitride (TiN).

[0143] Each of the fourth reflective electrodes RL4 can be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them. For example, the fourth reflective electrode RL4 can contain titanium (Ti).

[0144] The second reflective electrode RL2 is an electrode that substantially reflects light from the light emitting element LE, and thus the thickness of the second reflective electrode RL2 can be greater than the thickness of the first reflective electrode RL1, the thickness of the third reflective electrode RL3, and the thickness of the fourth reflective electrode RL4. For example, it can be that the thickness of the first reflective electrode RL1, the thickness of the third reflective electrode RL3, and the thickness of the fourth reflective electrode RL4 are substantially equal to each other, and the thickness of the second reflective electrode RL2 is greater than the thickness of the first reflective electrode RL1, the thickness of the third reflective electrode RL3, and the thickness of the fourth reflective electrode RL4. The thickness of the second reflective electrode RL2 is substantially equal to the thickness of the third reflective electrode RL3 and the thickness of the fourth reflective electrode RL4.

[0145] The tenth insulating film INS10 can be provided on the ninth insulating film INS9. The tenth insulating film INS10 can be provided between the reflective electrode layers RL adjacent to each other in the horizontal direction. The tenth insulating film INS10 can be provided on the reflective electrode layer RL in the third pixel PX3. The tenth insulating film INS10 can be formed of a silicon oxide (SiOx)-based inorganic film, but embodiments of the present specification are not limited thereto.

[0146] The eleventh insulating film INS11 can be provided on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 can be formed of a silicon oxide (SiOx)-based inorganic film, but embodiments of the present specification are not limited thereto. The tenth insulating film INS10 and the eleventh insulating film INS11 can be optical auxiliary layers through which light reflected at the reflective electrode layer RL among light emitted from the light emitting element LE passes.

[0147] At least any one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can not be provided with the tenth insulating film INS10 and the eleventh insulating film INS11 under the first electrode AND of the first pixel PX1 in order to match a resonance distance of light emitted from the light emitting element LE. The first electrode AND of the first pixel PX1 can be directly provided on the reflective electrode layer RL. The eleventh insulating film INS11 can be provided under the first electrode AND of the second pixel PX2. The tenth insulating film INS10 and the eleventh insulating film INS11 can be provided under the first electrode AND of the third pixel PX3.

[0148] In summary, the distance between the first electrode AND and the reflective electrode layer RL can be different in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. That is, in order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main wavelength of light emitted in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the presence or absence of the tenth insulating film INS10 and the eleventh insulating film INS11 can be set in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, the distance between the first electrode AND and the reflective electrode layer RL is greater in the third pixel PX3 than in the second pixel PX2 and the first pixel PX1, and the distance between the first electrode AND and the reflective electrode layer RL is greater in the second pixel PX2 than in the first pixel PX1, but embodiments of the present specification are not limited thereto. Figure 6 In the example illustrated in FIG. 1, the distance between the first electrode AND and the reflective electrode layer RL is greater in the third pixel PX3 than in the second pixel PX2 and the first pixel PX1, and the distance between the first electrode AND and the reflective electrode layer RL is greater in the second pixel PX2 than in the first pixel PX1, but embodiments of the present specification are not limited thereto.

[0149] In addition, in the embodiment of the present specification, the tenth insulating film INS10 and the eleventh insulating film INS11 are exemplified, but a twelfth insulating film can be additionally provided under the first electrode AND of the first pixel PX1. In this case, the eleventh insulating film INS11 and the twelfth insulating film INS12 can be provided under the first electrode AND of the second pixel PX2, and the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film INS12 can be provided under the first electrode AND of the third pixel PX3.

[0150] Each of the tenth vias VA10 can be connected to the exposed ninth conductive layer ML9 through the tenth insulating film INS10 and / or the eleventh insulating film INS11 in the second pixel PX2 and the third pixel PX3. The tenth via VA10 can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them. The thickness of the tenth via VA10 in the second pixel PX2 can be smaller than the thickness of the tenth via VA10 in the third pixel PX3.

[0151] The first electrode AND of each of the light emitting elements LE can be provided on the tenth insulating film INS10 and connected to the tenth via VA10. The first electrode AND of each of the light emitting elements LE can be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements LE can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of them. For example, the first electrode AND of each of the light emitting elements LE can be titanium nitride (TiN).

[0152] The pixel defining film PDL can be provided on a part of the region of the first electrode AND of each of the light emitting elements LE. The pixel defining film PDL can cover the edge of the first electrode AND of each of the light emitting elements LE. The pixel defining film PDL functions to divide the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3.

[0153] The first light emitting area EA1 can be defined as an area in which the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked to emit light in the first pixel PX1. The second light emitting area EA2 can be defined as an area in which the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked to emit light in the second pixel PX2. The third light emitting area EA3 can be defined as an area in which the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked to emit light in the third pixel PX3.

[0154] The pixel defining film PDL can include first to third pixel defining films PDL1, PDL2, PDL3. It can be that the first pixel defining film PDL1 is disposed on an edge of the first electrode AND of each of the light emitting elements LE, the second pixel defining film PDL2 is disposed on the first pixel defining film PDL1, and the third pixel defining film PDL3 is disposed on the second pixel defining film PDL2. The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 can be formed of a silicon oxide (SiOx)-based inorganic film, but embodiments of the present specification are not limited thereto. Each of a thickness of the first pixel defining film PDL1, a thickness of the second pixel defining film PDL2, and a thickness of the third pixel defining film PDL3 can be substantially equal to each other.

[0155] In a case in which the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 are formed as one pixel defining film, a height of the one pixel defining film is increased, and thus the first encapsulating inorganic film TFE1 can be disconnected due to step coverage. The step coverage refers to a ratio of a degree of coating a thin film in an inclined portion with respect to a degree of coating the thin film in a flat portion. The lower the step coverage, the higher the possibility that the thin film is disconnected in the inclined portion can be.

[0156] Thus, in order to prevent the first encapsulating inorganic film TFE1 from being disconnected due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 can have a cross-sectional structure having steps in the form of a staircase. For example, it can be that a width of the first pixel defining film PDL1 is greater than a width of the second pixel defining film PDL2 and a width of the third pixel defining film PDL3, and the width of the second pixel defining film PDL2 is greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1 refers to a length in a horizontal direction of the first pixel defining film PDL1 defined by the first direction DR1 and the second direction DR2.

[0157] Each of the plurality of trench TRC can penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. Also, each of the plurality of trench TRC can penetrate the eleventh insulating film INS11. A portion of the tenth insulating film INS10 in each of the plurality of trench TRC can have a recessed form.

[0158] At least one trench TRC can be configured between the pixels PX1, PX2, PX3 adjacent to each other. Figure 6 Two trenches TRC configured between the pixels PX1, PX2, PX3 adjacent to each other are exemplified in the embodiment of the present specification, but the embodiment of the present specification is not limited thereto.

[0159] The light emitting stack ES can include a plurality of intermediate layers. In Figure 6 The light emitting stack ES having a three-tandem structure including a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3 is exemplified in the embodiment of the present specification, but the embodiment of the present specification is not limited thereto. For example, the light emitting stack ES can have a two-tandem structure including two intermediate layers.

[0160] In the three-tandem structure, the light emitting stack ES can have a tandem structure including a plurality of stack layers IL1, IL2, IL3 emitting different colors from each other. For example, the light emitting stack ES can include a first stack layer IL1 emitting a first color light, a second stack layer IL2 emitting a second color light, and a third stack layer IL3 emitting a third color light. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 can be sequentially stacked.

[0161] The first stack layer IL1 can have a structure in which a first hole transport layer, a first organic light emitting layer emitting a first color light, and a first electron transport layer are sequentially stacked. The second stack layer IL2 can have a structure in which a second hole transport layer, a second organic light emitting layer emitting a second color light, and a second electron transport layer are sequentially stacked. The third stack layer IL3 can have a structure in which a third hole transport layer, a third organic light emitting layer emitting a third color light, and a third electron transport layer are sequentially stacked. In this case, the light emitting stack can emit white light mixed with the first color light (for example, red light) from the first organic light emitting layer, the second color light (for example, green light) from the second organic light emitting layer, and the third color light (for example, blue light) from the third organic light emitting layer. Accordingly, white light can be provided from the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, respectively. Here, the white light passing through the first light emitting area EA1 can be incident on the first color filter CF1, the white light passing through the second light emitting area EA2 can be incident on the second color filter CF2, and the white light passing through the third light emitting area EA3 can be incident on the third color filter CF3.

[0162] A first charge generation layer for supplying charges to the second stack layer IL2 and supplying electrons to the first stack layer IL1 can be disposed between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer can include an N-type charge generation layer for supplying electrons to the first stack layer IL1 and a P-type charge generation layer for supplying holes to the second stack layer IL2. The N-type charge generation layer can include a dopant of a metallic substance.

[0163] A second charge generation layer for supplying charges to the third stack layer IL3 and supplying electrons to the second stack layer IL2 can be disposed between the second stack layer IL2 and the third stack layer IL3. The second charge generation layer can include an N-type charge generation layer for supplying electrons to the second stack layer IL2 and a P-type charge generation layer for supplying holes to the third stack layer IL3.

[0164] The first stack layer IL1 can be disposed on the first electrode AND and the pixel defining film PDL, on the bottom surface of the trench TRC in each of the trenches TRC. The first stack layer IL1 can be disconnected between the pixels PX1, PX2, PX3 adjacent to each other due to the trench TRC. The second stack layer IL2 can be disposed on the first stack layer IL1. The second stack layer IL2 can be disconnected between the pixels PX1, PX2, PX3 adjacent to each other due to the trench TRC. A hole ESS or empty space can be disposed between the first stack layer IL1 and the second stack layer IL2. The third stack layer IL3 can be disposed on the second stack layer IL2. The third stack layer IL3 can not be disconnected by the trench TRC, and can be disposed to cover the second stack layer IL2 in each of the trenches TRC. For example, in a triple tandem structure, each of the plurality of trenches TRC can be a structure for disconnecting the first to second stack layers IL1, IL2, the first charge generation layer, and the second charge generation layer of the display element layer EML between the pixels PX1, PX2, PX3 adjacent to each other. In addition, in a double tandem structure, each of the plurality of trenches TRC can be a structure for disconnecting the charge generation layer disposed between the lower intermediate layer and the upper intermediate layer and the lower intermediate layer.

[0165] In order to stably disconnect the first to second stack layers IL1, IL2 of the display element layer EML between the pixels PX1, PX2, PX3 adjacent to each other, the height of each of the plurality of trenches TRC can be greater than the height of the pixel defining film PDL. The height of each of the plurality of trenches TRC refers to the length of each of the plurality of trenches TRC in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. In order to disconnect the first to third stack layers IL1, IL2, IL3 of the display element layer EML between the pixels PX1, PX2, PX3 adjacent to each other, there can be other structures instead of the trenches TRC. For example, instead of the trenches TRC, barrier walls in an inverse tapered form can be disposed on the pixel defining film PDL.

[0166] The number of the stack layers IL1, IL2, IL3 that emit different light from each other is not limited to Figure 6 As illustrated, for example, the light emitting stack ES can include two intermediate layers. In this case, it can be that either of the two intermediate layers is substantially the same as the first stack layer IL1, and the other includes a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to either of the intermediate layers and supplying charges to the other intermediate layer can be disposed between the two intermediate layers.

[0167] In addition, in Figure 6 The first to third stack layers IL1, IL2, IL3 are all disposed in the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3, but embodiments of the present specification are not limited thereto. For example, the first stack layer IL1 can be disposed in the first light emitting region EA1, and not disposed in the second light emitting region EA2 and the third light emitting region EA3. In addition, the second stack layer IL2 can be disposed in the second light emitting region EA2, and not disposed in the first light emitting region EA1 and the third light emitting region EA3. In addition, the third stack layer IL3 can be disposed in the third light emitting region EA3, and not disposed in the first light emitting region EA1 and the second light emitting region EA2. In this case, the first to third color filters CF1, CF2, CF3 of the optical layer OPL can be omitted.

[0168] The second electrode CAT can be disposed on the third stack layer IL3. The second electrode CAT can be disposed on the third stack layer IL3 in each of the plurality of trenches TRC. The second electrode CAT can be formed of a transparent conductive material (TCO, Transparent Conductive Material) such as ITO, IZO, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). In a case where the second electrode CAT is formed of the semi-transmissive conductive material, light extraction efficiency can be improved in each of the first to third pixels PX1, PX2, PX3 by a micro cavity.

[0169] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE can include at least one inorganic film TFE1, TFE2 in order to prevent oxygen or moisture from penetrating the display element layer EML. For example, the encapsulation layer TFE can include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0170] The first encapsulation inorganic film TFE1 can be disposed on the second electrode CAT. The first encapsulation inorganic film TFE1 can be formed of a multi-layer film in which one or more inorganic films of silicon nitride (SiNx) and silicon oxynitride (SiON), silicon oxide (SiOx) are alternately stacked. The first encapsulation inorganic film TFE1 can be formed by a chemical evaporation deposition (CVD) process.

[0171] The second encapsulation inorganic film TFE2 can be disposed on the first encapsulation inorganic film TFE1. The second encapsulation inorganic film TFE2 can be formed of a titanium oxide (TiOx) or an aluminum oxide layer (AlOx), but embodiments of the present specification are not limited thereto. The second encapsulation inorganic film TFE2 can be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0172] The organic film APL can be a layer for improving the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic film APL can be an organic film such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0173] The optical layer OPL can include a color filter layer CFL, a lens layer LSL, a filler layer FIL, a cover layer CVL, a phase delay layer QWP, and a wire grid polarizer WGP.

[0174] The color filter layer CFL can include a plurality of color filters CF1, CF2, CF3. The plurality of color filters CF1, CF2, CF3 can include first to third color filters CF1, CF2, CF3. The first to third color filters CF1, CF2, CF3 can be disposed on the organic film APL.

[0175] The first color filter CF1 can overlap the first light emitting area EA1 (e.g., a red light emitting area) of the first pixel PX1. The first color filter CF1 can transmit light of a first color, e.g., light of a red wavelength band. The red wavelength band can be approximately 600 nm to 750 nm. Due to this, the first color filter CF1 can transmit light of the first color in light emitted from the first light emitting area EA1.

[0176] The second color filter CF2 can overlap the second light emitting area EA2 (e.g., a green light emitting area) of the second pixel PX2. The second color filter CF2 can transmit light of a second color, e.g., light of a green wavelength band. The green wavelength band can be approximately 480 nm to 560 nm. Due to this, the second color filter CF2 can transmit light of the second color in light emitted from the second light emitting area EA2.

[0177] The third color filter CF3 can overlap the third light emitting area EA3 (e.g., a blue light emitting area) of the third pixel PX3. The third color filter CF3 can transmit light of a third color, e.g., light of a blue wavelength band. The blue wavelength band can be approximately 370 nm to 460 nm. Due to this, the third color filter CF3 can transmit light of the third color in light emitted from the third light emitting area EA3.

[0178] The lens layer LSL can be disposed on the color filter layer CFL. The lens layer LSL can include a plurality of lenses LNS. Each of the plurality of lenses LNS can be disposed on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS can be a structure for increasing a ratio of light toward the front surface of the display device 10. Each of the plurality of lenses LNS can have a cross-sectional shape protruding in an upward direction.

[0179] The filler layer (FIL) can be disposed on the lens layer (LSL). For example, the filler layer (FIL) can be disposed on multiple lenses (LNS). The filler layer (FIL) can have a predetermined refractive index to ensure that light travels in the third direction (DR3) at the interface between the multiple lenses (LNS) and the filler layer (FIL). Alternatively, the filler layer (FIL) can be a planarization layer. The filler layer (FIL) can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0180] A capping CVL can be disposed on a filler FLIL. The capping CVL can be a glass substrate or a polymer resin such as resin. When the capping CVL is a glass substrate, it can be attached to the filler FLIL. In this case, the filler FLIL serves to bond the capping CVL. When the capping CVL is a glass substrate, it can function as an encapsulation substrate. When the capping CVL is a polymer resin such as resin, it can be directly coated onto the filler FLIL.

[0181] A phase retardation layer (QWP) (or phase retardation plate, or phase retardation film) can be disposed on a capping layer (CVL). The phase retardation layer QWP can be a λ / 4 plate (quarter-wave plate), but the embodiments in this specification are not limited thereto.

[0182] A wire-grid polarizer (WGP) can be disposed on a phase retardation layer (QWP). The wire-grid polarizer (WGP) and the phase retardation layer (QWP) can constitute a polarization component. For example, according to one embodiment, the polarization component may include the phase retardation layer (QWP) and the wire-grid polarizer (WGP).

[0183] A wire grid polarizer (WGP) can include multiple grid patterns (GP). For example... Figure 5 As shown, each grid pattern GP can have a rectangular shape extending along the second direction DR2. Additionally, as... Figure 5 As shown, the grid pattern GP can be arranged along the first direction DR1. The grid patterns GP can be spaced apart on the first direction DR1. The wire grid polarizer WGP can contain at least one of aluminum (Al), silver (Ag), and gold (Au). For example, each of the grid patterns GP can be made of a material containing at least one of aluminum (Al), silver (Ag), and gold (Au).

[0184] The wire grid polarizer WGP can transmit light of a certain polarization direction and reflect light of other polarization directions to be reused. Such a wire grid polarizer WGP has a high polarization separation performance compared to other polarizers, and thus is useful as a reflective polarizer. For example, the wire grid polarizer WGP is an element that generates polarization using a conductive wire grid, and can have a structure including a plurality of grid patterns GP by periodically arranging a plurality of wires composed of a conductive substance in parallel in nanometer size on a phase delay layer QWP. It can be that such a wire grid polarizer WGP including a plurality of grid patterns GP does not diffract incident light if the period of the grid pattern GP thereof is smaller than the wavelength of the incident light, and thus transmits a component (for example, TM (Transverse Magnetic) polarization (for example, P wave)) having a vibration direction orthogonal to the conductive grid pattern GP among the incident light, and on the contrary, reflects a component (for example, TE (Transverse Electric) polarization (for example, S wave)) having a vibration direction parallel to the grid pattern GP thereof. In other words, the wire grid polarizer WGP can reflect a polarization component (for example, S wave) parallel to the grid pattern GP thereof and, on the contrary, transmit a polarization component (for example, P wave) perpendicular to the grid pattern GP thereof, in a case where the arrangement period of the grid pattern GP is shorter than the wavelength of an electromagnetic wave incident on the wire grid polarizer WGP thereof. The wire grid polarizer WGP uses the grid pattern GP as a metal, and thus the efficiency of reflecting light is very high, and thus can make the reflected light be reflected again, and reuse the light to make all the light into one kind of polarized light.

[0185] According to an embodiment, the wire grid polarizer WGP can have a grid pattern GP with a relatively small pitch in the third light emitting area EA3 (or the third light emitting area EA3 overlapping with the blue color filter CF3) that transmits blue light, and can have a grid pattern GP with a relatively large pitch in the first light emitting area EA1 or the second light emitting area EA2. In other words, the grid pattern GP of the wire grid polarizer WGP can have a smaller pitch in the aforementioned third light emitting area EA3 than in the first light emitting area or the second light emitting area EA2.

[0186] According to an embodiment, the grating pattern GP of the wire grid polarizer WGP receiving the provided light of a short wavelength (e.g., blue light) can have a relatively smaller pitch (or interval). For example, when the pitch of the grating pattern GP of the first pixel PX1 providing red light is defined as a first pitch P1 (or a first interval), the pitch of the grating pattern GP of the second pixel PX2 providing green light is defined as a second pitch P2 (or a second interval), and the pitch of the grating pattern GP of the third pixel PX3 providing blue light is defined as a third pitch P3 (or a third interval), the third pitch P3 (or the third interval) can be smaller than the first pitch P1 (or the first interval) or the second pitch P2 (or the second interval). In an embodiment, the first pitch P1 (or the first interval) and the second pitch P2 (or the second interval) can be the same.

[0187] In other words, when the pitch of the grating pattern GP disposed on the first color filter CF1 transmitting red light is defined as a first pitch P1 (or a first interval), the pitch of the grating pattern GP disposed on the second color filter CF2 transmitting green light is defined as a second pitch P2 (or a second interval), and the pitch of the grating pattern GP disposed on the third color filter CF3 transmitting blue light is defined as a third pitch P3 (or a third interval), the third pitch P3 (or the third interval) can be smaller than the first pitch P1 (or the first interval) or the second pitch P2 (or the second interval). In an embodiment, the first pitch P1 (or the first interval) and the second pitch P2 (or the second interval) can be the same. Thereby, the transmittance of the short wavelength (e.g., blue light) can be improved. In other words, by improving the transmittance of the light of the short wavelength, the transmittance of the blue light can be maintained at almost the same level as the transmittance of the other colors (e.g., the transmittance of green light and the transmittance of red light). Thereby, the brightness balance between the blue light, the green light, and the red light can be improved.

[0188] According to an embodiment, the first pitch P1 can be 100 nm to 150 nm, the second pitch P2 can be 100 nm to 150 nm, and the third pitch P3 can be 50 nm to 90 nm.

[0189] According to an embodiment, at least one of the grating patterns GP of the wire grid polarizer WGP can have a thickness TK of 100 nm to 300 nm. As still another example, at least one of the grating patterns GP of the wire grid polarizer WGP can have a thickness TK of 100 nm to 200 nm. According to an embodiment, all of the grating patterns GP of the wire grid polarizer WGP can have the same thickness TK.

[0190] Figure 7 is a cross-sectional view showing an example of the display panel 100 taken along the X-X' of Figure 5

[0191] ​Figure 7 The display panel 100 of the present embodiment is different from the display panel 100 of the foregoing Figure 6 The display panel 100 of the present embodiment is different from the display panel 100 of the foregoing

[0192] As shown in FIG. 1, the display panel 100 of the present embodiment can include a lens layer LSL. Figure 7 As shown in FIG. 1, the lens layer LSL can be disposed on the wire grid polarizer WGP. In other words, the wire grid polarizer WGP can be disposed between the phase retardation layer QWP and the lens layer LSL.

[0193] In addition, as shown in FIG. 1, the filler layer FIL can be disposed directly on the color filter layer CFL. The filler layer FIL can be in contact with the color filter layer CFL. Figure 7

[0194] Figure 8 FIG. 2 is a cross-sectional view showing an example of the display panel 100 taken along the X-X' of FIG. 1. Figure 5

[0195] Figure 8 The display panel 100 of the present embodiment is different from the display panel 100 of the foregoing Figure 6 The display panel 100 of the present embodiment is different from the display panel 100 of the foregoing Figure 6 The display panel 100 of the present embodiment is a "white-OLED" display panel in which the light-emitting stacks ES of the pixels PX1, PX2, PX3 included in the unit pixel UPX all provide white light. Figure 8 The display panel 100 of the present embodiment is a "RGB-OLED" display panel in which the light-emitting stacks ES of the pixels PX1, PX2, PX3 included in the unit pixel UPX respectively provide red light, green light, and blue light.

[0196] As shown in FIG. 1, according to the display panel 100 not including the color filter layer CFL, the organic film APL and the lens layer LSL can be in contact with each other. Figure 8 According to an embodiment,

[0197] Figure 8 ​​​The light emitting stack ES can provide light of different hues from each other for each pixel. For example, the light emitting stack ES of the first pixel PX1 can include a red organic light emitting layer providing red light, the light emitting stack ES of the second pixel PX2 can include a green organic light emitting layer providing green light, and the light emitting stack ES of the third pixel PX3 can include a blue organic light emitting layer providing blue light. In other words, the light emitting stack ES can include the aforementioned red organic light emitting layer in the first light emitting area EA1 of the first pixel PX1, the aforementioned green organic light emitting layer in the second light emitting area EA2 of the second pixel PX2, and the aforementioned blue organic light emitting layer in the third light emitting area EA3 of the third pixel PX3. Thereby, it can be that the first pixel PX1 provides red light generated through the red organic light emitting layer, the second pixel PX2 provides green light generated through the green organic light emitting layer, and the third pixel PX3 provides blue light generated through the blue organic light emitting layer.

[0198] According to an embodiment, when a pitch of the grid pattern GP of the first pixel PX1 providing red light is defined as a first pitch P1 (or a first interval), a pitch of the grid pattern GP of the second pixel PX2 providing green light is defined as a second pitch P2 (or a second interval), and a pitch of the grid pattern GP of the third pixel PX3 providing blue light is defined as a third pitch P3 (or a third interval), the third pitch P3 (or the third interval) can be smaller than the first pitch P1 (or the first interval) or the second pitch P2 (or the second interval). In an embodiment, the first pitch P1 (or the first interval) and the second pitch P2 (or the second interval) can be the same.

[0199] Figure 9 is a cross-sectional view showing the display panel 100 taken along the X-X' of Figure 5

[0200] Figure 9 The display panel 100 of Figure 7 The display panel 100 of

[0201] As shown in Figure 9 According to the display panel 100 not including the color filter layer CFL, the organic film APL and the filling layer FIL can be in contact with each other.

[0202] According to an embodiment, Figure 9 ​The light emitting stack ES can provide light of different hues from each other for each pixel. For example, the light emitting stack ES of the first pixel PX1 can include a red organic light emitting layer providing red light, the light emitting stack ES of the second pixel PX2 can include a green organic light emitting layer providing green light, and the light emitting stack ES of the third pixel PX3 can include a blue organic light emitting layer providing blue light. In other words, the light emitting stack ES can include the aforementioned red organic light emitting layer in the first light emitting area EA1 of the first pixel PX1, the aforementioned green organic light emitting layer in the second light emitting area EA2 of the second pixel PX2, and the aforementioned blue organic light emitting layer in the third light emitting area EA3 of the third pixel PX3. Thereby, it can be that the first pixel PX1 provides red light generated through the red organic light emitting layer, the second pixel PX2 provides green light generated through the green organic light emitting layer, and the third pixel PX3 provides blue light generated through the blue organic light emitting layer.

[0203] According to an embodiment, when a pitch of the grid pattern GP of the first pixel PX1 providing red light is defined as a first pitch P1 (or a first interval), a pitch of the grid pattern GP of the second pixel PX2 providing green light is defined as a second pitch P2 (or a second interval), and a pitch of the grid pattern GP of the third pixel PX3 providing blue light is defined as a third pitch P3 (or a third interval), the third pitch P3 (or the third interval) can be smaller than the first pitch P1 (or the first interval) or the second pitch P2 (or the second interval). In an embodiment, the first pitch P1 (or the first interval) and the second pitch P2 (or the second interval) can be the same.

[0204] Figure 10 is a graph for explaining an effect of a display device according to an embodiment. For example, Figure 10 is a graph showing a degree of transmittance of each wavelength of light, Figure 10 The X axis of means wavelength (nm) of light, Figure 10 The Y axis of means degree of transmittance (%) of light.

[0205] Figure 10 The first curve CV1 in the blue light wavelength region BA of means a degree of transmittance of blue light of a comparative object application, Figure 10 The second curve CV2 in the blue light wavelength region BA of means a degree of transmittance of blue light of a display device according to an embodiment.

[0206] As Figure 10As shown, according to an embodiment, the transmittance of the blue light in the blue light wavelength region BA can be improved. Thereby, according to an embodiment, the brightness of the light in the blue light wavelength region BA, the brightness of the light in the green light wavelength region GA, and the brightness of the light in the red light wavelength region RA can be maintained at almost the same level. Thereby, according to an embodiment, the brightness balance among the blue light, the green light, and the red light can be improved.

[0207] Figure 11 is a perspective view showing a head-mounted display device according to an embodiment. Figure 12 is an exploded perspective view showing an example of the head-mounted display device of Figure 11

[0208] Referring to Figure 11 and Figure 12 , the head-mounted display device 1000 according to an embodiment includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0209] The first display device 10_1 provides an image to the left eye of a user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is substantially the same as the display device 10 described in connection with Figure 1 and Figure 2 , and thus a description regarding the first display device 10_1 and the second display device 10_2 is omitted.

[0210] The first optical member 1510 can be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 can be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 can include at least one convex lens.

[0211] The intermediate frame 1400 can be disposed between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 functions to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0212] ​The control circuit board 1600 can be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 through connectors. The control circuit board 1600 can convert an image source input from the outside into digital video data DATA and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connectors.

[0213] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the left eye of the user to the first display device 10_1 and digital video data DATA corresponding to a right-eye image optimized for the right eye of the user to the second display device 10_2. In addition, the control circuit board 1600 can transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0214] The display device housing 1100 functions to house the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical part 1510, the second optical part 1520, and the control circuit board 1600. The housing cover 1200 is disposed to cover an open side of the display device housing 1100. The housing cover 1200 can include a first eyepiece 1210 disposed to the left eye of the user and a second eyepiece 1220 disposed to the right eye of the user. In Figure 11 and Figure 12 In the above, the first eyepiece 1210 and the second eyepiece 1220 are separately disposed, but embodiments of the present specification are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0215] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical part 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical part 1520. Accordingly, the user can see the image of the first display device 10_1 magnified as a virtual image through the first optical part 1510 through the first eyepiece 1210 and see the image of the second display device 10_2 magnified as a virtual image through the second optical part 1520 through the second eyepiece 1220.

[0216] The headgear 1300 functions to fix the display device housing 1100 to the head of the user so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are maintained in a state of being disposed to the left eye and the right eye of the user, respectively. In the case where the display device housing 1100 is implemented to be light and small, the head-mounted display device 1000 can have a spectacle frame instead of the headgear 800 as Figure 13

[0217] ​Further, the head-mounted display device 1000 can further include a battery for supplying power, an external memory slot into which an external memory can be inserted, an external connection port for receiving supply of an image source, and a wireless communication module. The external connection port can be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module can be a 5G communication module, a 4G communication module, a WiFi module, or a Bluetooth module.

[0218] Figure 13 FIG. 1 is a perspective view illustrating a head-mounted display device according to an embodiment.

[0219] Referring to Figure 13 , the head-mounted display device 1000_1 according to an embodiment can be a display device housing 1200_1 implemented in the form of glasses that are lightweight and small. According to an embodiment, the head-mounted display device 1000_1 can include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temple legs 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and the display device housing 1200_1.

[0220] The display device housing 1200_1 can include the display device 10_3, the optical member 1060, and the optical path conversion member 1070. An image displayed on the display device 10_3 can be enlarged by the optical member 1060 and provided to the right eye of the user through the right-eye lens 1020 by optical path conversion by the optical path conversion member 1070. Due to this, the user can view an augmented reality image in which a virtual image displayed on the display device 10_3 through the right eye and a real image viewed through the right-eye lens 1020 are combined.

[0221] In Figure 13 , the display device housing 1200_1 is illustrated as being disposed at the right end of the support frame 1030, but embodiments of the present specification are not limited thereto. For example, the display device housing 1200_1 can be disposed at the left end of the support frame 1030, in which case an image of the display device 10_3 can be provided to the left eye of the user. In addition, the display device housing 1200_1 can be disposed at both the left end and the right end of the support frame 1030, in which case the user can view an image displayed on the display device 10_3 through both the left eye and the right eye.

[0222] Those skilled in the art to which the present specification belongs will be able to understand that the present specification can be implemented in other specific forms without changing the technical idea or essential characteristics thereof. Thus, the above-described embodiments should be understood in all aspects as exemplary, not limiting. The scope of the present specification is indicated by the scope of the appended patent claims, not the detailed description, and the meaning and scope of the patent claims and all modifications or variations derived from the equivalent concept thereof should be interpreted as included in the scope of the present specification.

[0223] On the other hand, in the present specification and drawings, preferred embodiments of the present specification are disclosed, although specific terms are used, which are used only in the general meaning for easily explaining the technical content of the present specification and helping the understanding of the utility model, not to limit the scope of the present specification. Other modifications based on the technical idea of the present specification are also possible, which will be apparent to those skilled in the art to which the present specification belongs, in addition to the embodiments disclosed herein.

Claims

1. A display device, characterized by comprising: comprises: a substrate; a first electrode on the substrate; a light-emitting layer on the first electrode; a second electrode on the light-emitting layer; and a wire grid polarizer on the second electrode, the wire grid polarizer including a plurality of grating patterns, a pitch between grating patterns configured in correspondence with a blue light-emitting region of a blue pixel that provides blue light is smaller than a pitch between grating patterns configured in correspondence with a light-emitting region of a pixel that provides light different from the blue light.

2. The display device according to claim 1, wherein the pixel that provides the different light includes: a green pixel that provides green light; and a red pixel that provides red light.

3. The display device according to claim 2, wherein a pitch between grating patterns configured in correspondence with a green light-emitting region of the green pixel and a pitch between grating patterns configured in correspondence with a red light-emitting region of the red pixel are the same.

4. The display device according to claim 1, wherein the display device further includes: a phase retardation layer between the second electrode and the wire grid polarizer.

5. The display device according to claim 1, wherein the display device further includes: a color filter layer between the second electrode and the wire grid polarizer.

6. The display device according to claim 5, wherein the color filter layer includes: a red color filter that transmits red light; a green color filter that transmits green light; and a blue color filter that transmits blue light.

7. The display device according to claim 6, wherein a pitch between grating patterns configured in correspondence with the blue color filter is smaller than a pitch between grating patterns configured in correspondence with the green color filter.

8. The display device according to claim 6, wherein a pitch between grating patterns configured in correspondence with the blue color filter is smaller than a pitch between grating patterns configured in correspondence with the red color filter.

9. The display device according to claim 1, wherein a pitch between grating patterns configured in correspondence with the blue light-emitting region is 50 nm to 90 nm.

10. The display device according to claim 1, wherein a pitch between grating patterns configured in correspondence with a light-emitting region of the pixel that provides the different light is 100 nm to 150 nm.

11. The display device according to claim 1, wherein at least one of the grating patterns of the wire grid polarizer has a thickness of 100 nm to 300 nm.

12. The display device according to claim 1, wherein the display device further includes: a lens layer between the second electrode and the wire grid polarizer.

13. The display device according to claim 1, wherein the display device further includes: a lens layer on the wire grid polarizer. comprises:

14. An optical device, characterized by a display device; and a light path conversion member on the display device, the display device including: a substrate; a first electrode on the substrate; a light-emitting layer on the first electrode; a second electrode on the light-emitting layer; and a wire grid polarizer on the second electrode, the wire grid polarizer including a plurality of grating patterns, ​ ​ A pitch between grid patterns configured in correspondence with blue light emitting regions of blue pixels that provide blue light is smaller than a pitch between grid patterns configured in correspondence with light emitting regions of pixels that provide light different from the blue light.

15. The optical device of claim 14, wherein The pixels that provide the different light include: green pixels that provide green light; and red pixels that provide red light.

16. The optical device of claim 15, wherein A pitch between grid patterns configured in correspondence with green light emitting regions of the green pixels and a pitch between grid patterns configured in correspondence with red light emitting regions of the red pixels are the same.

17. The optical device of claim 14, wherein The optical device further includes: a phase retardation layer between the second electrode and the wire grid polarizer.

18. The optical device of claim 14, wherein The optical device further includes: a color filter layer between the second electrode and the wire grid polarizer.

19. The optical device of claim 18, wherein The color filter layer includes: a red color filter that transmits red light; a green color filter that transmits green light; and a blue color filter that transmits blue light.

20. The optical device of claim 19, wherein A pitch between grid patterns configured in correspondence with the blue color filter is smaller than a pitch between grid patterns configured in correspondence with the green color filter.

21. The optical device of claim 19, wherein A pitch between grid patterns configured in correspondence with the blue color filter is smaller than a pitch between grid patterns configured in correspondence with the red color filter.

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