Low-noise amplification circuit with feedback structure

Abstract

The utility model belongs to the technical field of low-noise amplification circuits, and relates to a low-noise amplification circuit with a feedback structure, the low-noise amplification circuit comprises a first-stage fully-differential amplification circuit, a second-stage low-noise operational amplification circuit and a power supply, the first-stage fully-differential amplification circuit comprises a common-source amplification circuit of two symmetrical JFET devices which are connected in parallel, and an NPN type BJT device is connected with the two JFET devices; drain electrodes of the left JFET device and the right JFET device serve as input and are in coupled connection with a direct-current bias feedback loop. The second-stage low-noise operational amplifier circuit adopts a low-noise operational amplifier, and the output ends of the two direct-current bias feedback loops in the first-stage fully-differential amplification circuit are used as double inputs to form an amplification circuit with a subtraction structure; drain electrodes of the JFETs on the two sides are coupled with a direct-current bias feedback loop, the problem that the JFETs on the two sides of a conventional circuit are asymmetric due to parameter discreteness between the JFETs is eliminated, the JFETs on the two sides do not need to be provided with current sources and adjusted to a quiescent working point respectively, and normal work of the first-stage fully-differential amplification circuit is simply and efficiently guaranteed.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of low-noise amplification circuit, and particularly relates to a low-noise amplification circuit with a feedback structure. BACKGROUND

[0002] In many fields including seismic detection, electronic communication and precision instruments, amplification and detection of weak voltage signals are often carried out, and the measured weak signals are usually in the order of microvolts or even smaller. The conventional amplifier for amplifying and collecting weak voltage signals has the following problems: on the one hand, since the conventional amplifier usually adopts a single-ended input mode, one end of the measured device measurement port needs to be grounded, which may not be able to well suppress common-mode interference; on the other hand, the device itself usually inevitably introduces too much additional noise, and if the circuit background noise and the measured weak signal are in the same order of magnitude, the originally very weak measured signal may be covered and interfered by the noise signal, so that the measured signal information is difficult to accurately extract and subsequent analysis is difficult to carry out. These problems are unacceptable for high-performance weak signal amplification and detection devices, and therefore, by designing an amplification circuit with a feedback structure and low background noise, the sensitivity of weak voltage signal detection can be ensured. SUMMARY

[0003] The application aims to provide a low-noise amplification circuit with a feedback structure to solve the problem of insufficient weak voltage signal detection.

[0004] The application is implemented in the following manner,

[0005] The low-noise amplification circuit with a feedback structure comprises a first full-differential amplification circuit, a second low-noise operational amplifier circuit and a power supply, wherein the first full-differential amplification circuit comprises two symmetric two-way JFET device common-source amplification circuits connected in parallel, a NPN type BJT device connected with the two JFET devices to provide a drain current as a constant current source, and a direct current bias feedback loop coupled and connected with the drain of the left and right JFET devices as inputs.

[0006] The second low-noise operational amplifier circuit adopts a low-noise operational amplifier, and the outputs of the two direct current bias feedback loops in the first full-differential amplification circuit are used as double inputs to form a subtraction structure amplification circuit.

[0007] The power supply provides a positive 12V and a negative 12V power supply by a lithium battery.

[0008] Further, the input end of the first full-differential amplification circuit is in a double-ended input differential mode, the double-ended inputs are connected with one end of two capacitors C1 and C2, respectively, the other end of the capacitors C1 and C2 is connected with two resistors R1 and R2 and the gates of two JFET devices J1 and J2, respectively.

[0009] The NPN type BJT device T1 is used to provide the conduction current in the stable working state, wherein the collector of the NPN type BJT device T1 is connected with the resistor R6 and the resistor R7, the base of the NPN type BJT device T1 is grounded, the emitter of the BJT device T1 is connected with the resistor R3, and the other end of the resistor R3 is connected with the negative pole of the lithium battery.

[0010] The first full differential amplification circuit module adopts the JFET device J1 and the JFET device J2 in the left-right symmetrical structure to form a parallel common source circuit for amplification, the drain of the JFET device J1 on one side is connected with the resistor R4, the other end of the resistor R4 is connected with the positive pole of the lithium battery, the gate of the JFET device J1 is connected with one end of the double-end input, i.e. the connection end of the capacitor C1 and the resistor R1, and the source of the JFET device J1 is connected with the resistor R6; the drain of the JFET device J2 on the other side is connected with the resistor R5, the other end of the resistor R5 is connected with the positive pole of the lithium battery, the gate of the JFET device J2 is connected with the other end of the double-end input, i.e. the connection end of the capacitor C2 and the resistor R2, and the source of the JFET device J2 is connected with the resistor R7.

[0011] Further, the drains of the JFET device J1 and the JFET device J2 on two sides are connected with two DC bias feedback loops to the sources of the JFET devices in a differential form respectively;

[0012] The two DC bias feedback loop structures are symmetrical, the DC bias feedback loop on one side takes the drains of the JFET device J1 and the JFET device J2 as inputs and includes that one side of the resistor R10 is connected with the drain of the JFET device J1, the other side of the resistor R10 is connected with the reverse input end of the operational amplifier U1 and the resistor R13, the other side of the resistor R13 is connected with the signal output end of the operational amplifier U1, serving as one end output of the first full differential amplification circuit module, one side of the resistor R11 is connected with the drain of the JFET device J2, the other side of the resistor R11 is connected with the forward input end of the operational amplifier U1 and the resistor R12, the other side of the resistor R12 is connected with the ground, one side of the resistor R8 is connected with the signal output end of the operational amplifier U1, and the other side of the resistor R8 is connected with the source of the JFET device J1.

[0013] The DC bias feedback loop on the other side takes the drains of the JFET device J1 and the JFET device J2 as inputs and includes that one side of the resistor R15 is connected with the drain of the JFET device J2, the other side of the resistor R15 is connected with the reverse input end of the operational amplifier U1 and the resistor R18; the other side of the resistor R18 is connected with the signal output end of the operational amplifier U1, serving as the other output end of the first full differential amplification circuit module; one side of the resistor R16 is connected with the drain of the JFET device J1, the other side of the resistor R16 is connected with the forward input end of the operational amplifier U2 and the resistor R17; the other side of the resistor R17 is connected with the ground; one side of the resistor R9 is connected with the signal output end of the operational amplifier U1, and the other side of the resistor R9 is connected with the source of the JFET device J2.

[0014] Further, the secondary low-noise operational amplifier circuit module is a subtraction circuit structure, comprising resistors R19, R20, R21, R22, a low-noise operational amplifier U3, one side of the resistor R19 is connected with one side signal output of the primary full-differential amplifier circuit module, i.e. the output terminal of the operational amplifier U1, the other side is connected with the reverse input terminal of the low-noise operational amplifier U3 and the resistor R22, the other side of the resistor R22 is connected with the output terminal of the low-noise operational amplifier U3, as the output terminal of the whole amplifier circuit; one side of the resistor R20 is connected with the other side signal output terminal of the primary full-differential amplifier circuit module, i.e. the output terminal of the operational amplifier U2, the other side is connected with the resistor R21 and the forward input terminal of the low-noise operational amplifier U3, the other side of the resistor R21 is connected with the ground.

[0015] Compared with the prior art, the present application has the advantages of:

[0016] Compared with the prior art, the present application has the advantages of:

[0017] The amplifier circuit has low equivalent input noise, and the integrated operational amplifier with low noise can better reduce the interference of noise on the measurement of weak voltage signals.

[0018] The DC bias feedback loop coupled with the drain of the JFET on both sides is proposed, which eliminates the asymmetry of the JFET on both sides of the conventional circuit due to the parameter discreteness of the JFET, and does not need to set current sources and adjust to the static working point for the JFET on both sides, thereby simply and efficiently ensuring the normal work of the primary full-differential amplifier circuit.

[0019] The present application has the advantages of simple structure, easy implementation and wide application in the field of collection and detection of various weak voltage signals. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The low-noise amplifier circuit provided by the embodiment of the present application is shown in the overall block diagram;

[0021] Figure 2 The low-noise amplifier circuit provided by the embodiment of the present application is shown in the overall block diagram; DETAILED DESCRIPTION

[0022] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application is further described in detail below with reference to the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0023] Referring to Figure 1 In combination with Figure 2As shown, a low noise amplifier circuit with feedback structure includes a full differential amplifier circuit, a low noise amplifier circuit, and a power supply. The full differential amplifier circuit includes two parallel symmetric JFET devices, a NPN BJT device connected to the two JFET devices as a constant current source, and two DC bias feedback loops coupled to the drains of the two JFET devices. The low noise amplifier circuit uses a low noise operational amplifier with the outputs of the two DC bias feedback loops as inputs. The power supply provides 12V positive and negative power supply.

[0024] The input of the full differential amplifier circuit is in differential mode. The two inputs of the full differential amplifier circuit are connected to one end of capacitors C1 and C2, respectively. The other ends of the capacitors C1 and C2 are connected to resistors R1 and R2 and the gates of JFET devices J1 and J2, respectively, to filter low frequency interference and retain high frequency parts of the input signal.

[0025] The NPN BJT device T1 provides a stable conduction current during operation. The collector of the NPN BJT device T1 is connected to resistors R6 and R7, the base of the NPN BJT device T1 is grounded, and the emitter of the BJT device T1 is connected to resistor R3, the other end of which is connected to the negative terminal of the lithium battery.

[0026] The full differential amplifier circuit module uses symmetric JFET devices J1 and J2 to form a parallel common-source circuit for amplification. The drain of the left JFET device J1 is connected to resistor R4, the other end of which is connected to the positive terminal of the lithium battery. The gate of the JFET device J1 is connected to one end of the double-ended input, i.e., the connection end of capacitor C1 and resistor R1. The source of the JFET device J1 is connected to resistor R6.

[0027] The right side is connected in the same way. The drain of the right JFET device J2 is connected to resistor R5, the other end of which is connected to the positive terminal of the lithium battery. The gate of the JFET device J2 is connected to the other end of the double-ended input, i.e., the connection end of capacitor C2 and resistor R2. The source of the JFET device J2 is connected to resistor R7.

[0028] The drains of the two JFET devices J1 and J2 are connected to two DC bias feedback loops connected to the sources of the JFET devices in differential mode, to reduce the bias between the drain voltages of the JFET devices J1 and J2 and eliminate the parameter differences and asymmetry between the JFET devices J1 and J2 caused by manufacturing processes.

[0029] The two DC bias feedback loops are symmetrically structured. The left DC bias feedback loop uses the drains of JFET devices J1 and JFET devices J2 as inputs. It includes: resistor R10 connected on one side to the drain of JFET device J1, and on the other side connected to the inverting input of operational amplifier U1 and resistor R13. The other side of resistor R13 is connected to the signal output of operational amplifier U1, serving as one output of a first-stage fully differential amplifier module. Resistor R11 connected on one side to the drain of JFET device J2, and on the other side connected to the non-inverting input of operational amplifier U1 and resistor R12. The other side of resistor R12 is grounded. Resistor R8 connected on one side to the signal output of operational amplifier U1, and on the other side to the source of JFET device J1.

[0030] The right-side connections are identical. The right-side DC bias feedback loop uses the drains of JFET devices J1 and J2 as inputs. One side of resistor R15 is connected to the drain of JFET device J2, and the other side is connected to the inverting input of operational amplifier U1 and resistor R18. The other side of resistor R18 is connected to the signal output of operational amplifier U1, serving as another output of the first-stage fully differential amplifier module. One side of resistor R16 is connected to the drain of JFET device J1, and the other side is connected to the non-inverting input of operational amplifier U2 and resistor R17. The other side of resistor R17 is grounded. One side of resistor R9 is connected to the signal output of operational amplifier U1, and the other side is connected to the source of JFET device J2.

[0031] The two-stage low-noise operational amplifier (LNO) circuit module is a subtraction circuit structure, including resistors R19, R20, R21, and R22, and a low-noise operational amplifier U3. One side of resistor R19 is connected to one signal output of the first-stage fully differential amplifier module, i.e., the output terminal of operational amplifier U1; the other side is connected to the inverting input terminal of low-noise operational amplifier U3 and resistor R22. The other side of resistor R22 is connected to the output terminal of low-noise operational amplifier U3, serving as the output terminal of the entire amplifier circuit. One side of resistor R20 is connected to the other signal output terminal of the first-stage fully differential amplifier module, i.e., the output terminal of operational amplifier U2; the other side is connected to resistor R21 and the non-inverting input terminal of low-noise operational amplifier U3. The other side of resistor R21 is grounded. The two-stage LNO module further amplifies the signal amplified by the first-stage fully differential amplifier module.

[0032] See in this invention Figure 2 As shown, V1, V2, V3, V4, V5, V6, V7, and V8 all refer to the power supply terminals.

[0033] The circuit of the present application adopts two-stage low-noise differential amplification circuit to amplify weak voltage signals, and a DC bias feedback loop is coupled at the first stage to reduce the parameter difference between the left and right JFETs in the discrete JFET amplifier. The first stage is a full-differential amplifier circuit module, and the second stage low-noise operational amplifier circuit module receives the double-ended differential output of the first stage and generates a single-ended output result after differential amplification.

[0034] The input end of the first-stage full-differential amplifier circuit module is in the form of double-ended input differential mode, which can effectively suppress common-mode interference from the input end.

[0035] A high-pass filter composed of capacitor C1, resistor R1, capacitor C2 and resistor R2 is coupled in front of the gates of the two JFET devices to eliminate the interference of power frequency signals and low-frequency parts of the input signals in the environment.

[0036] The emitter of NPN-type BJT device T1 is connected to resistor R3, and the collector of NPN-type BJT device T1 is connected to resistor R6 and resistor R7, which constitute a constant current source to provide stable drain current for the two JFET devices after being turned on.

[0037] The first-stage full-differential amplifier circuit module adopts a completely symmetrical JFET common-source amplification circuit structure with the two JFETs connected in parallel, which can reduce the generation of background noise in the circuit due to the large input impedance and small noise of JFET devices.

[0038] In practice, there is usually a certain deviation in the parameters of the two JFET devices due to process defects, which makes the actual static operating points not completely consistent when the same current source is used, resulting in static operating point deviation. Therefore, the amplification circuit cannot normally amplify the weak voltage signals collected. Coupling the DC bias feedback of the subtracter structure at the drain of the first-stage two JFETs can ensure that the drain currents of the two JFETs are basically the same even in the case of large deviation, so as to reduce the bias between the drain voltages of the two JFET devices.

[0039] The second stage adopts a low-noise integrated operational amplifier, and the two input ends are respectively connected to the output ends of the two DC bias feedback circuits of the first-stage full-differential amplifier circuit module to form a subtraction structure amplification circuit, which further amplifies the output signal of the first stage without introducing excessive noise, so as to improve the gain of the amplification circuit.

[0040] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A low noise amplifier circuit with a feedback structure, characterized by, The low noise amplifier circuit with feedback structure comprises a first full differential amplifier circuit, a second low noise amplifier circuit and a power supply, wherein the first full differential amplifier circuit comprises two symmetrical JFET devices in parallel, a NPN type BJT device is connected to the two JFET devices to provide a drain current as a constant current source, and a DC bias feedback loop is coupled to the left and right JFET device drains as inputs; The second low noise amplifier circuit adopts a low noise operational amplifier, and the two DC bias feedback loop outputs of the first full differential amplifier circuit are used as double inputs to form a subtraction structure amplifier circuit; The power supply provides positive and negative 12V power supply by a lithium battery.

2. The low noise amplifier circuit with feedback structure according to claim 1, wherein the input of the first full differential amplifier circuit is in a differential mode, and the two inputs are connected to one end of the capacitors C1 and C2, respectively, and the other end of the capacitors C1 and C2 is connected to the gates of the JFET devices J1 and J2 and the resistors R1 and R2, respectively; The NPN type BJT device T1 is used to provide a stable conduction current during operation, wherein the collector of the NPN type BJT device T1 is connected to the resistors R6 and R7, the base of the NPN type BJT device T1 is grounded, the emitter of the BJT device T1 is connected to the resistor R3, and the other end of the resistor R3 is connected to the negative electrode of the lithium battery; The first full differential amplifier circuit module adopts JFET devices J1 and J2 in a left-right symmetrical structure to form a parallel common-source circuit for amplification, the drain of the JFET device J1 on one side is connected to the resistor R4, the other end of the resistor R4 is connected to the positive electrode of the lithium battery, the gate of the JFET device J1 is connected to one end of the double inputs, i.e. the connection end of the capacitor C1 and the resistor R1, and the source of the JFET device J1 is connected to the resistor R6; the drain of the JFET device J2 on the other side is connected to the resistor R5, the other end of the resistor R5 is connected to the positive electrode of the lithium battery, the gate of the JFET device J2 is connected to the other end of the double inputs, i.e. the connection end of the capacitor C2 and the resistor R2, and the source of the JFET device J2 is connected to the resistor R7.

3. The low noise amplifier circuit with feedback structure according to claim 2, wherein the drains of the JFET devices J1 and J2 on both sides are connected to two DC bias feedback loops to the sources of the JFET devices in a differential mode. ​ ​ The two DC bias feedback loop structures are symmetrical. One side DC bias feedback loop takes the drain of JFET device J1 and JFET device J2 as input, and includes: one side of resistor R10 is connected with the drain of JFET device J1, and the other side is connected with the reverse input end of operational amplifier U1 and resistor R13, the other side of resistor R13 is connected with the signal output end of operational amplifier U1, and is taken as one end output of the first full differential amplification circuit module; one side of resistor R11 is connected with the drain of JFET device J2, and the other side is connected with the forward input end of operational amplifier U1 and resistor R12, the other side of resistor R12 is connected with the ground, and one side of resistor R8 is connected with the signal output end of operational amplifier U1, and the other side is connected with the source of JFET device J1; The other side DC bias feedback loop takes the drain of JFET device J1 and JFET device J2 as input; one side of resistor R15 is connected with the drain of JFET device J2, and the other side is connected with the reverse input end of operational amplifier U1 and resistor R18; the other side of resistor R18 is connected with the signal output end of operational amplifier U1, and is taken as the other output end of the first full differential amplification circuit module; one side of resistor R16 is connected with the drain of JFET device J1, and the other side is connected with the forward input end of operational amplifier U2 and resistor R17; the other side of resistor R17 is connected with the ground; one side of resistor R9 is connected with the signal output end of operational amplifier U1, and the other side is connected with the source of JFET device J2.

4. The low noise amplification circuit with feedback structure according to claim 3, characterized in that, The second low noise operational amplifier circuit module is a subtraction circuit structure, and includes resistor R19, resistor R20, resistor R21, resistor R22, low noise operational amplifier U3, one side of resistor R19 is connected with the signal output of the first full differential amplification circuit module, i.e. the output end of operational amplifier U1, and the other side is connected with the reverse input end of low noise operational amplifier U3 and resistor R22, the other side of resistor R22 is connected with the output end of low noise operational amplifier U3, and is taken as the output end of the whole amplification circuit; one side of resistor R20 is connected with the other signal output end of the first full differential amplification circuit module, i.e. the output end of operational amplifier U2, and the other side is connected with resistor R21 and the forward input end of noise operational amplifier U3, and the other side of resistor R21 is connected with the ground.

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