Display module and display device

Abstract

The embodiment of the utility model provides a display module and a display device, relates to the technical field of display, and is used for improving the accuracy of detecting the binding quality of a display panel and a chip on film. The display module comprises a display panel and a chip on film. The display panel comprises a binding part, and the binding part comprises a plurality of first binding pins and at least one second binding pin; the plurality of first binding pins and the at least one second binding pin are arranged along a first direction; each second binding pin is located between two adjacent first binding pins; the chip on film comprises a plurality of first wires and a plurality of first test wires; the plurality of first wires are distributed at intervals in the first direction; the first test line crosses over at least one first wire and is electrically insulated from the first wire; the first binding pin is in binding connection with the first wire, and the second binding pin is in binding connection with the first target test wire and the second target test wire. The display module is used for displaying images.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display module and display device. Background Technology

[0002] Liquid crystal displays (LCDs) are popular due to their advantages such as small size, high brightness, energy efficiency, and low radiation. An LCD device consists of a backlight module that provides backlighting and a display panel that displays the image. Large-screen televisions (e.g., 65-inch) are particularly popular.

[0003] In related technologies, after the bonding pins of the display panel and the flip-chip film are bonded together, the bonding pins need to be manually inspected to determine the bonding quality between the bonding pins and the flip-chip film. However, manual inspection is time-consuming and has low accuracy. Utility Model Content

[0004] The purpose of this disclosure is to provide a display module and display device for improving the accuracy of detecting the bonding quality of the display panel and the flip-chip film.

[0005] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0006] On one hand, a display module is provided. The display module includes a display panel and a flip-chip film. The display panel includes a bonding portion, which includes a plurality of first bonding pins and at least one second bonding pin; the plurality of first bonding pins and the at least one second bonding pin are arranged along a first direction; the second bonding pin is located between two adjacent first bonding pins; the flip-chip film includes a plurality of first traces and a plurality of first test lines; along the first direction, the plurality of first traces are spaced apart; the first test lines cross at least one first trace, and any two first test lines cross different first traces, and the first test lines are electrically insulated from the first traces; the first bonding pins are bonded to the first traces, and the second bonding pins are bonded to a first target test line and a second target test line; wherein, one of the two first test lines corresponding to the two first traces on both sides of the second bonding pin is a first target test line and the other is a second target test line.

[0007] In the aforementioned display module, multiple first test lines can be connected sequentially, i.e., multiple first test lines are connected in series. A test signal is input to one end of each of the multiple first test lines, and the first test signal is output from the other end of each of the multiple first test lines. The test signal input at one end of each of the multiple first test lines is compared with the test signal output at the other end of each of the multiple first test lines. If the input test signal and the output test signal are equal, it proves that the bonding quality between the first bonding pin and the first trace is good. If the input test signal and the output test signal are not equal, it proves that the bonding quality between the first bonding pin and the first trace is poor. In other words, the bonding quality between the first bonding pin and the first trace does not depend on the subjective intention of the tester, thereby improving the accuracy of the test results.

[0008] In some embodiments, the bonding portion includes a plurality of second bonding pins, and the first bonding pins and the second bonding pins are arranged alternately along the first direction; the first test line crosses a first trace.

[0009] In some embodiments, the plurality of first test lines include a plurality of first sub-lines and a plurality of second sub-lines. Along the first direction, the first traces corresponding to the plurality of first sub-lines and the first traces corresponding to the plurality of second sub-lines are arranged alternately. The extension directions of the plurality of first sub-lines coincide, the extension directions of the plurality of second sub-lines coincide, and the extension directions of the first sub-lines and the extension directions of the second sub-lines are parallel.

[0010] In some embodiments, the flip-chip film further includes a second test line and a third test line. Along the first direction, the second test line is located on one side of the plurality of first traces; the second test line is connected to the first test line closest to the second test line among the plurality of first test lines; along the first direction, the third test line is located on the other side of the plurality of first traces; the third test line is connected to the first test line closest to the third test line among the plurality of first test lines.

[0011] In some embodiments, the bonding portion further includes a third bonding pin and a fourth bonding pin. Along the first direction, the third bonding pin is located on the side of the plurality of first bonding pins closest to the second test line; a gap exists between the third bonding pin and the first test line closest to the second test line among the plurality of first test lines; the third bonding pin is bonded to the second test line and the first test line closest to the second test line among the plurality of first test lines; and / or, along the first direction, the fourth bonding pin is located on the side of the plurality of first bonding pins closest to the third test line; a gap exists between the fourth bonding pin and the first test line closest to the third test line among the plurality of first test lines; the fourth bonding pin is bonded to the third test line and the first test line closest to the third test line among the plurality of first test lines.

[0012] In some embodiments, the first test line includes a third main body segment, a third adapter block, and a fourth adapter block; in the orthographic projection on the reference plane, the third adapter block is located on one side of the first trace, and the fourth adapter block is located on the other side of the first trace; the third main body segment overlaps with the first trace, one end of the third main body segment is located on one side of the first trace and connected to the third adapter block through a via, and the other end extends to the other side of the first trace and is connected to the fourth adapter block through a via; the flip-chip film includes a first conductive layer and a second conductive layer. The first conductive layer includes the plurality of first traces, the second test line, the third test line, the third adapter block, and the fourth adapter block; the second conductive layer is located on one side of the first conductive layer, and the second conductive layer includes the third main body segment.

[0013] In some embodiments, the second test line and the first test line closest to the second test line among the plurality of first test lines are connected by a via; and / or, the third test line and the first test line closest to the third test line among the plurality of first test lines are connected by a via.

[0014] In some embodiments, the first test line closest to the second test line among the plurality of first test lines includes a first body segment and a first adapter block. On the orthographic projection of the reference plane, the first adapter block is located on the side of the first trace away from the second test line. The first body segment overlaps with the first trace. One end of the first body segment is located on the side of the first trace closest to the second test line and is connected to the second test line via a via. The other end extends to the side of the first trace away from the second test line and is connected to the first adapter block via a via. The flip-chip film includes a first conductive layer and a second conductive layer. The first conductive layer includes the plurality of first traces, the second test line, the third test line, and the first adapter block. The second conductive layer is located on one side of the first conductive layer and includes the first body segment.

[0015] In some embodiments, the first test line closest to the third test line among the plurality of first test lines includes a second body segment and a second adapter block. On the orthographic projection of the reference plane, the second adapter block is located on the side of the first trace away from the third test line. The second body segment overlaps with the first trace. One end of the second body segment is located on the side of the first trace closest to the third test line and is connected to the third test line via a via. The other end extends to the side of the first trace away from the third test line and is connected to the second adapter block via a via. The flip-chip film includes a first conductive layer and a second conductive layer. The first conductive layer includes the plurality of first traces, the second test line, the third test line, and the second adapter block. The second conductive layer is located on one side of the first conductive layer and includes the second body segment.

[0016] In some embodiments, the middle first test line among the plurality of first test lines includes a third main body segment, a third adapter block, and a fourth adapter block; in the orthographic projection on the reference plane, the third adapter block is located on one side of the first trace, and the fourth adapter block is located on the other side of the first trace; the third main body segment overlaps with the first trace, one end of the third main body segment is located on one side of the first trace and connected to the third adapter block through a via, and the other end extends to the other side of the first trace and is connected to the fourth adapter block through a via; the flip-chip film includes a first conductive layer and a second conductive layer. The first conductive layer includes the plurality of first traces, the second test line, the third test line, the third adapter block, and the fourth adapter block; the second conductive layer is located on one side of the first conductive layer, and the second conductive layer includes the third main body segment.

[0017] In some embodiments, the display module further includes a driver chip, a power chip, and a first sub-circuit. The driver chip is connected to the display panel; the power chip is connected to the second test line; the first sub-circuit is coupled to the power chip, the third test line, and the driver chip. The first sub-circuit is configured to control the driver chip to transmit or not transmit data signals to the display panel based on signals transmitted from the power chip to the first sub-circuit and signals transmitted from the third test line to the first sub-circuit; wherein the signals transmitted from the power chip to the second test line and the signals transmitted from the power chip to the first sub-circuit are the same.

[0018] In some embodiments, the first sub-circuit includes a voltage comparator, the first input terminal of which is connected to the power supply chip, the second input terminal of which is connected to the third test line, and the first output terminal of which is connected to the driver chip.

[0019] In some embodiments, the display module further includes a printed circuit board and a motherboard. The printed circuit board is connected to the first trace, the second test line, and the third test line; the motherboard is connected to the printed circuit board; wherein the power chip and the first sub-circuit are located on the motherboard; and / or, the driver chip is located on the flip-chip film.

[0020] In some embodiments, the display panel includes a plurality of bonding portions, and the display module includes a plurality of flip-chip films, with one flip-chip film bonded to one of the bonding portions.

[0021] On the other hand, a display device is provided. The display device includes a display module as described in any of the above embodiments.

[0022] The above-described display device has the same structure and beneficial technical effects as the display module provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0024] Figure 1 This is a structural diagram of a display device according to some embodiments;

[0025] Figure 2 This is another structural diagram of a display device according to some embodiments;

[0026] Figure 3 This is a structural diagram of a display module according to some embodiments;

[0027] Figure 4 for Figure 3 A magnified view of a portion of C;

[0028] Figure 5 for Figure 3 Another magnified view of part C;

[0029] Figure 6 for Figure 4 Cross-sectional view along section line DD;

[0030] Figure 7 for Figure 5 Cross-sectional view along section line EE;

[0031] Figure 8 for Figure 5 Cross-sectional view along section line FF;

[0032] Figure 9 A structural diagram of a motherboard including a power chip and a first sub-circuit according to some embodiments;

[0033] Figure 10 This is a timing diagram of a display module according to some embodiments. Detailed Implementation

[0034] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0035] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0036] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0037] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0038] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0039] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0040] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0041] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0042] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0043] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0044] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0045] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0046] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0047] like Figure 1 As shown, some embodiments of this disclosure provide a display device 1000, which can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0048] For example, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, wearable device, augmented reality (AR) device, virtual reality (VR) device, in-vehicle display, or flight display.

[0049] In some examples, such as Figure 1 As shown, the display device 1000 can be a large-scale display product. For example, the display device 1000 can be a television set.

[0050] In some other examples, such as Figure 2 As shown, the display device 1000 can be a wearable device. For example, the display device 1000 can be a watch.

[0051] In some embodiments, such as Figure 2 and Figure 3 As shown, the display device 1000 includes a display module 100, which includes a display panel 10 and a flip-chip film 20.

[0052] The display panel 10 mentioned above includes various types, and can be selected and set according to actual needs.

[0053] For example, the display panel 10 described above may be: an organic light-emitting diode (OLED) display panel 10, a quantum dot light-emitting diode (QLED) display panel 10, an active matrix organic light-emitting diode (AMOLED) display panel 10, a liquid crystal display (LCD) display panel 10, or a mini / micro light-emitting display (MLED) display panel 10, etc. The embodiments disclosed herein do not impose specific limitations.

[0054] For example, Micro LED refers to an LED with a size (e.g., length) of less than 50 μm, while Mini LED refers to an LED with a size (e.g., length) of 50 μm to 200 μm.

[0055] like Figure 3 As shown, the display panel 10 has a display area AA and a peripheral area BB disposed on at least one side of the display area AA. Figure 3 Taking the peripheral area BB surrounding the display area AA as an example, the peripheral area BB is the area where no image is displayed. The peripheral area BB is configured to set up the display driving circuit, such as the scan driving circuit and the source driving circuit.

[0056] like Figure 3 and Figure 4 As shown, the display panel 10 includes a bonding part 11 located in the peripheral area BB, and the bonding part 11 includes a plurality of first bonding pins 111.

[0057] In some examples, such as Figure 4 As shown, multiple first bonding pins 111 are arranged at intervals along the first direction X.

[0058] In some embodiments, such as Figure 4 As shown, the flip-chip film 20 includes a plurality of first traces 21 extending along a second direction Y and spaced apart along a first direction X. The first direction X and the second direction Y intersect; for example, the first direction X and the second direction Y are perpendicular. The first traces 21 are configured to transmit drive signals, such as gate drive signals, data signals, and power signals.

[0059] In related technologies, the bonding portion of the display panel and the flip-chip film need to be bonded together, specifically, the first bonding pin and the first trace need to be bonded together. This allows drive signals to be transmitted to the display panel through the first trace and the first bonding pin to drive the display panel to display images. After the display panel and the flip-chip film are bonded together, the connection quality of the first bonding pin and the first trace needs to be manually inspected. For example, inspectors may visually inspect the connection point of the first bonding pin and the first trace, or they may inspect the connection point using a microscope. However, inspectors are easily affected by external factors (e.g., fatigue), which can lead to lower accuracy of manual inspection results.

[0060] To solve the above technical problems, such as Figure 3 , Figure 4 and Figure 5 As shown, some embodiments of this disclosure provide a display module 100, which includes a display panel 10 and a flip-chip film 20. In the display panel 10, the bonding portion 11 further includes at least one second bonding pin 112. Along the first direction X, a plurality of first bonding pins 111 and at least one second bonding pin 112 are arranged along the first direction X, and the second bonding pin 112 is located between two adjacent first bonding pins 111.

[0061] The flip-chip film 20 also includes multiple first test lines 22. Each first test line 22 crosses at least one first trace 21, and any two first test lines 22 cross different first traces 21. The first test lines are electrically insulated from the first traces 21. A first bonding pin 111 is bonded to the first trace 21, and a second bonding pin 112 is bonded to the first target test line and the second target test line. Specifically, one of the two first test lines 22 corresponding to the two first traces 21 on either side of the second bonding pin 112 is the first target test line, and the other is the second target test line.

[0062] In this configuration, multiple first test lines 22 can be connected sequentially, i.e., multiple first test lines 22 are connected in series. A test signal is input to one end of each of the multiple first test lines 22, and the first test signal is output from the other end of each of the multiple first test lines 22. The test signal input to one end of each of the multiple first test lines 22 is compared with the test signal output from the other end of each of the multiple first test lines 22. If the input test signal and the output test signal are equal, it proves that the bonding quality between the first bonding pin 111 and the first trace 21 is good. If the input test signal and the output test signal are not equal, it proves that the bonding quality between the first bonding pin 111 and the first trace 21 is poor. In other words, the bonding quality between the first bonding pin 111 and the first trace 21 does not depend on the subjective intention of the tester, thereby improving the accuracy of the test results.

[0063] In some examples, the input test signal and the output test signal are equal, which can mean that the voltage value of the input test signal and the voltage value of the output test signal are equal.

[0064] It should be noted that if the bonding quality between the first bonding pin 111 and the first trace 21 is poor, for example, if the first bonding pin 111 and the first trace 21 separate, this separation will cause the second bonding pin 112 and the first test line 22 surrounding the first bonding pin 111 to separate. In other words, the bonding quality between the second bonding pin 112 and the first test line 22 is poor, which will affect the signal in the first test line 22, resulting in the input test signal and the output test signal being unequal.

[0065] If the bonding quality of the first bonding pin 111 and the first trace 21 is good, the bonding quality of the second bonding pin 112 and the first test line 22 around the first bonding pin 111 will be good, and the input test signal and the output test signal will be equal.

[0066] Based on the above principle, the quality of the bonding connection between the first bonding pin 111 and the first trace 21 can be determined by comparing the input test signal and the output test signal.

[0067] In some embodiments, such as Figure 4 and Figure 5 As shown, the bonding section 11 includes a plurality of second bonding pins 112. Along the first direction X, the plurality of first bonding pins 111 and the plurality of second bonding pins 112 are arranged alternately, and the first test line 22 crosses a first trace 21.

[0068] With this configuration, a second binding pin 112 is provided between any two first binding pins 111. During the testing process, the quality of the binding connection between all the first binding pins 111 and the first trace 21 can be tested, which can further improve the testing quality.

[0069] In some embodiments, such as Figure 4 and Figure 5 As shown, the multiple first test lines 22 include multiple first sub-lines 221 and multiple second sub-lines 222. Along the first direction X, the first traces 21 corresponding to the multiple first sub-lines 221 and the first traces 21 corresponding to the multiple second sub-lines 222 are arranged alternately. The extension directions of the multiple first sub-lines 221 coincide, the extension directions of the multiple second sub-lines 222 coincide, and the extension directions of the first sub-lines 221 and the second sub-lines 222 are parallel.

[0070] By setting it in this way, the dimensions of the multiple first test lines 22 along the second direction Y can be made smaller, thereby making the dimensions of the bonding portion 11 in the display panel along the second direction Y smaller, and thus making the width of the peripheral area smaller.

[0071] In some embodiments, based on this, such as Figure 4 and Figure 5 As shown, the flip-chip film 20 also includes a second test line 23 and a third test line 24. Along the first direction X, it connects to the first test line 22 closest to the second test line 23 among a plurality of first test lines 22.

[0072] like Figure 4 and Figure 5 As shown, along the first direction X, the third test line 24 is located on the other side of the plurality of first traces 21. When the first traces 21 and the first bonding pin 111 are bonded together, the third test line 24 is connected to the first test line 22 that is closest to the third test line 24 among the plurality of first test lines 22.

[0073] In some embodiments, such as Figure 4As shown, the bonding part 11 also includes a third bonding pin 113. Along the first direction X, the third bonding pin 113 is located on the side of the plurality of first bonding pins 111 close to the second test line 23. There is a gap between the third bonding pin 113 and the first test line 22 closest to the second test line 23 among the plurality of first test lines 22. The third bonding pin 113 is bonded to the second test line 23 and the first test line 22 closest to the second test line 23 among the plurality of first test lines 22.

[0074] In some embodiments, such as Figure 4 As shown, the bonding part 11 also includes a fourth bonding pin 114. Along the first direction X, the fourth bonding pin 114 is located on the side of the plurality of first bonding pins 111 close to the third test line 24. There is a gap between the fourth bonding pin 114 and the first test line 22 closest to the third test line 24 among the plurality of first test lines 22. The fourth bonding pin 114 is bonded to the third test line 24 and the first test line 22 closest to the third test line 24 among the plurality of first test lines 22.

[0075] In some embodiments, such as Figure 4 and Figure 6 As shown, the first test line 22 includes a third main body segment 2201, a third adapter block 2202, and a fourth adapter block 2203. On the orthographic projection of the reference plane, the third adapter block 2202 is located on one side of the first trace 21, and the fourth adapter block 2203 is located on the other side of the first trace 21. The third main body segment 2201 overlaps with the first trace 21. One end of the third main body segment 2201 is located on one side of the first trace 21 and is connected to the third adapter block 2202 through a via. The other end extends to the other side of the first trace 21 and is connected to the fourth adapter block 2203 through a via.

[0076] At this point, the third adapter block 2202 of the first test line 22 closest to the second test line 23 is connected to the third bonding pin 113, and the fourth adapter block 2203 is connected to the second bonding pin 112. The third adapter block 2202 of the first test line 22 closest to the third test line 24 is connected to the fourth bonding pin 114, and the fourth adapter block 2203 is connected to the second bonding pin 112. Both the third adapter block 2202 and the fourth adapter block 2203 of the first test line 22 closest to the third test line 24 are connected to the second bonding pin 112.

[0077] Based on this, such as Figure 4 and Figure 6As shown, the flip-chip thin film 20 includes a first conductive layer 201 and a second conductive layer 202. The first conductive layer 201 includes multiple first traces 21, second test lines 23, third test lines 24, a third adapter block 2202, and a fourth adapter block 2203. The second conductive layer 202 is located on one side of the first conductive layer 201, and the second conductive layer 202 includes a third main body segment 2201.

[0078] In some embodiments, such as Figure 5 and Figure 7 As shown, the second test line 23 and the first test line 22 closest to the second test line 23 among the multiple first test lines 22 are connected by a via.

[0079] In some examples, the first test line 22 closest to the second test line 23 among multiple first test lines 22 includes a first main body segment 2204 and a first adapter block 2205. On the orthographic projection of the reference plane, the first adapter block 2205 is located on the side of the first trace 21 away from the second test line 23. The first main body segment 2204 overlaps with the first trace 21. One end of the first main body segment 2204 is located on the side of the first trace 21 close to the second test line 23 and is connected to the second test line 23 through a via. The other end extends to the side of the first trace 21 away from the second test line 23 and is connected to the first adapter block 2205 through a via.

[0080] Based on this, such as Figure 5 and Figure 7 As shown, the flip-chip thin film 20 includes a first conductive layer 201 and a second conductive layer 202.

[0081] The first conductive layer 201 includes multiple first traces 21, second test lines 23, third test lines 24, and a first adapter block 2205.

[0082] The second conductive layer 202 is located on one side of the first conductive layer 201, and the second conductive layer 202 includes a first main body segment 2204.

[0083] In some embodiments, such as Figure 5 and Figure 8 As shown, the third test line 24 and the first test line 22 closest to the third test line 24 among the multiple first test lines 22 are connected by a via.

[0084] In some examples, such as Figure 5 and Figure 8As shown, the first test line 22 closest to the third test line 24 among the multiple first test lines 22 includes a second main body segment 2206 and a second adapter block 2207. In the orthographic projection on the reference plane, the second adapter block 2207 is located on the side of the first trace 21 away from the third test line 24. The second main body segment 2206 overlaps with the first trace 21. One end of the second main body segment 2206 is located on the side of the first trace 21 closest to the third test line 24 and is connected to the third test line 24 via a via. The other end extends to the side of the first trace 21 away from the third test line 24 and is connected to the second adapter block 2207 via a via. Based on this, as shown in the figure, the flip-chip thin film 20 includes a first conductive layer 201 and a second conductive layer 202. The first conductive layer 201 includes multiple first traces 21, second test lines 23, third test lines 24, and a second adapter block 2207. The second conductive layer 202 is located on one side of the first conductive layer 201, and the second conductive layer 202 includes a second main body segment 2206.

[0085] In some examples, the middle first test line 22 among multiple first test lines 22 includes a third main body segment 2201, a third adapter block 2202, and a fourth adapter block 2203. On the orthographic projection of the reference plane, the third adapter block 2202 is located on one side of the first trace 21, and the fourth adapter block 2203 is located on the other side of the first trace 21. The third main body segment 2201 overlaps with the first trace 21. One end of the third main body segment 2201 is located on one side of the first trace 21 and is connected to the third adapter block 2202 through a via. The other end extends to the other side of the first trace 21 and is connected to the fourth adapter block 2203 through a via.

[0086] Based on this, such as Figure 6 As shown, the flip-chip thin film 20 includes a first conductive layer 201 and a second conductive layer 202. The first conductive layer 201 includes multiple first traces 21, second test lines 23, third test lines 24, a third adapter block 2202, and a fourth adapter block 2203. The second conductive layer 202 is located on one side of the first conductive layer 201 and includes a third main body segment 2201.

[0087] In some embodiments, such as Figure 9 As shown, the display module 100 also includes a driver chip 30, a power supply chip 40, and a first sub-circuit 50.

[0088] The driver chip 30 is connected to the display panel 10. The power chip 40 is connected to the second test line 23. The first sub-circuit 50 is coupled to the power chip 40, the third test line 24, and the driver chip 30. The first sub-circuit 50 is configured to control the driver chip 30 to transmit or not transmit data signals to the display panel based on the signals transmitted from the power chip 40 to the first sub-circuit 50 and the signals transmitted from the third test line 24 to the first sub-circuit 50. The signals transmitted from the power chip 40 to the second test line 23 are the same as the signals transmitted from the power chip 40 to the first sub-circuit 50.

[0089] In some examples, the first sub-circuit 50 includes a voltage comparator 51. The first input of the voltage comparator 51 is connected to the power supply chip 40, the second input is connected to the third test line 24, and the first output is connected to the driver chip 30.

[0090] In other examples, the first sub-circuit 50 includes an amplifier or a linear regulator.

[0091] Based on the above structure, the detection process is as follows: When the display device 1000 is powered on, the power chip 40 sends a test signal to the second test line 23 and the first sub-circuit 50. The test signal is transmitted to the first sub-circuit 50 through the second test line 23, the second bonding pin 112, the first test line 22, and the third test line 24. The first sub-circuit 50 is configured to control the driver chip 30 to transmit or not transmit data signals to the display panel according to the signal transmitted from the power chip 40 to the first sub-circuit 50 and the signal transmitted from the third test line 24 to the first sub-circuit 50.

[0092] The first sub-circuit 50 compares the signal transmitted from the power supply chip 40 to the first sub-circuit 50 with the signal transmitted from the third test line 24 to the first sub-circuit 50. If the signal transmitted from the power supply chip 40 to the first sub-circuit 50 and the signal transmitted from the third test line 24 to the first sub-circuit 50 are equal, the driver chip 30 transmits a data signal to the display panel 10 to drive the display panel 10 to display an image. If the signal transmitted from the power supply chip 40 to the first sub-circuit 50 and the signal transmitted from the third test line 24 to the first sub-circuit 50 are not equal, the driver chip 30 does not transmit a data signal to the display panel 10, and the display panel 10 does not display an image.

[0093] In some embodiments, such as Figure 9As shown, the display module 100 also includes a motherboard 60 and a printed circuit board 70. The motherboard 60 and the printed circuit board 70 are connected, and the printed circuit board 70 is connected to the flip-chip film 20, that is, the printed circuit board 70 is connected to the first trace 21, the second test line 23, and the third test line 24. The motherboard 60 inputs specific signals to the printed circuit board 200, and the printed circuit board 200 processes and controls the input signals, thereby displaying various images, text, and audio content on the display panel 10.

[0094] The power supply chip 40 and the first sub-circuit 50 are located on the motherboard 60. And / or, the driver chip 30 is located on the flip-chip film 20.

[0095] In some embodiments, the display panel 10 includes a plurality of bonding portions 11, and the display module 100 includes a plurality of flip-chip films 20, with one flip-chip film 20 bonded to one bonding portion 11.

[0096] The following, in conjunction with the timing diagram, provides a detailed explanation of the operation of the power supply chip 40, the first sub-circuit 50, and the driver chip 30. For example... Figure 10 As shown, the display panel 10 has a detection stage P, which includes a first detection stage P1 and a second detection stage P2.

[0097] In the first detection phase P1, the power chip 40 sends a test signal to the second test line 23 and the first sub-circuit 50. The test signal is transmitted to the first sub-circuit 50 through the second test line 23, the second bonding pin 112, the first test line 22 and the third test line 24.

[0098] In the second detection phase P2, the first sub-circuit 50 compares the signal transmitted from the power supply chip 40 to the first sub-circuit 50 with the signal transmitted from the third test line 24 to the first sub-circuit 50. If the signals transmitted from the power supply chip 40 to the first sub-circuit 50 and the third test line 24 to the first sub-circuit 50 are equal, the first sub-circuit 50 transmits a display signal to the driver chip 30. After receiving the display signal transmitted from the first sub-circuit 50, the driver chip 30 transmits a data signal to the display panel 10, thereby causing the display panel 10 to display an image.

[0099] If the signal transmitted from the power supply chip 40 to the first sub-circuit 50 is not equal to the signal transmitted from the third test line 24 to the first sub-circuit 50, the first sub-circuit 50 will not transmit a signal to the driver chip 30. As a result, the driver chip 30 cannot receive the display signal transmitted from the first sub-circuit 50, and the driver chip 30 will not transmit a data signal to the display panel 10, so the display panel 10 cannot display an image.

[0100] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0101] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display module, characterized by The display panel comprises a binding part, the binding part comprises a plurality of first binding pins and at least one second binding pin; the plurality of first binding pins and the at least one second binding pin are arranged along a first direction; the second binding pin is located between two adjacent first binding pins; The COF comprises a plurality of first traces and a plurality of first test lines; along the first direction, the plurality of first traces are distributed at intervals; the first test line crosses at least one first trace, and any two first test lines cross different first traces; the first test line is electrically insulated from the first trace; the first binding pin and the first trace are connected by binding; the second binding pin is connected to the first target test line and the second target test line by binding; wherein one of the two first test lines corresponding to the two first traces on both sides of the second binding pin is the first target test line, and the other is the second target test line. The binding part comprises a plurality of second binding pins, and the first binding pins and the second binding pins are alternately arranged along the first direction; the first test line crosses one first trace.

2. The display module of claim 1, wherein, The plurality of first test lines comprises a plurality of first sub-lines and a plurality of second sub-lines, and the first traces corresponding to the plurality of first sub-lines and the first traces corresponding to the plurality of second sub-lines are alternately arranged along the first direction; wherein the extension directions of the plurality of first sub-lines coincide, the extension directions of the plurality of second sub-lines coincide, and the extension direction of the first sub-line and the extension direction of the second sub-line are parallel.

3. The display module of claim 2, wherein, The COF further comprises:

4. The display module of claim 2 or 3, wherein, A second test line, along the first direction, the second test line is located on one side of the plurality of first traces; the second test line is connected to the first test line closest to the second test line in the plurality of first test lines; A third test line, along the first direction, the third test line is located on the other side of the plurality of first traces; the third test line is connected to the first test line closest to the third test line in the plurality of first test lines. The binding part further comprises:

5. The display module of claim 4, wherein, A third binding pin, along the first direction, the third binding pin is located on one side of the plurality of first binding pins close to the second test line; the third binding pin and the first test line closest to the second test line in the plurality of first test lines have a gap; the third binding pin is connected to the second test line and the first test line closest to the second test line in the plurality of first test lines by binding; and / or A fourth binding pin, along the first direction, the fourth binding pin is located on the other side of the plurality of first binding pins close to the third test line; the fourth binding pin and the first test line closest to the third test line in the plurality of first test lines have a gap; the fourth binding pin is connected to the third test line and the first test line closest to the third test line in the plurality of first test lines by binding. ​ 6. The display module of claim 5, wherein, The first test line comprises a third main segment, a third adapter block and a fourth adapter block; on the orthographic projection on the reference plane, the third adapter block is located on one side of the first trace, and the fourth adapter block is located on the other side of the first trace; the third main segment overlaps the first trace, one end of the third main segment is located on one side of the first trace and connected to the third adapter block through a via, and the other end extends to the other side of the first trace and is connected to the fourth adapter block through a via; The COF comprises: A first conductive layer comprising the plurality of first traces, the second test line, the third test line, a third adapter block and a fourth adapter block; A second conductive layer located on one side of the first conductive layer, the second conductive layer comprising the third main segment.

7. The display module of claim 4, wherein, The second test line and the first test line closest to the second test line among the plurality of first test lines are connected through a via; and / or, the third test line and the first test line closest to the third test line among the plurality of first test lines are connected through a via.

8. The display module of claim 7, wherein, The first test line closest to the second test line among the plurality of first test lines comprises a first main segment and a first adapter block, on the orthographic projection on the reference plane, the first adapter block is located on the side of the first trace away from the second test line, and the first main segment overlaps the first trace, one end of the first main segment is located on the side of the first trace close to the second test line and connected to the second test line through a via, and the other end extends to the side of the first trace away from the second test line and is connected to the first adapter block through a via; The COF comprises: A first conductive layer comprising the plurality of first traces, the second test line, the third test line and a first adapter block; A second conductive layer located on one side of the first conductive layer, the second conductive layer comprising the first main segment.

9. The display module of claim 7, wherein, The first test line closest to the third test line among the plurality of first test lines comprises a second main segment and a second adapter block, on the orthographic projection on the reference plane, the second adapter block is located on the side of the first trace away from the third test line, and the second main segment overlaps the first trace, one end of the second main segment is located on the side of the first trace close to the third test line and connected to the third test line through a via, and the other end extends to the side of the first trace away from the third test line and is connected to the second adapter block through a via; The COF comprises: A first conductive layer comprising the plurality of first traces, the second test line, the third test line and a second adapter block; A second conductive layer located on one side of the first conductive layer, the second conductive layer comprising the second main segment. The first test line closest to the third test line among the plurality of first test lines comprises a second main segment and a second adapter block, on the orthographic projection on the reference plane, the second adapter block is located on the side of the first trace away from the third test line, and the second main segment overlaps the first trace, one end of the second main segment is located on the side of the first trace close to the third test line and connected to the third test line through a via, and the other end extends to the side of the first trace away from the third test line and is connected to the second adapter block through a via; The COF comprises: A first conductive layer comprising the plurality of first traces, the second test line, the third test line and a second adapter block; A second conductive layer located on one side of the first conductive layer, the second conductive layer comprising the second main segment.

10. The display module of claim 7, wherein, The first test line in the middle of the plurality of first test lines comprises a third main segment, a third adapter block and a fourth adapter block; on the orthographic projection on the reference plane, the third adapter block is located on one side of the first trace, and the fourth adapter block is located on the other side of the first trace; the third main segment overlaps the first trace, one end of the third main segment is located on one side of the first trace and connected to the third adapter block through a via, and the other end extends to the other side of the first trace and is connected to the fourth adapter block through a via; The COF comprises: A first conductive layer comprising the plurality of first traces, the second test line, the third test line, the third adapter block and the fourth adapter block; A second conductive layer located on one side of the first conductive layer, the second conductive layer comprising the third main segment.

11. The display module of any one of claims 1-3, wherein, Further comprising: A driving chip connected to the display panel; A power supply chip connected to the second test line; A first sub-circuit coupled to the power supply chip, the third test line and the driving chip, the first sub-circuit being configured to control the driving chip to transmit or not to transmit a data signal to the display panel according to a signal transmitted by the power supply chip to the first sub-circuit and a signal transmitted by the third test line to the first sub-circuit; wherein the signal transmitted by the power supply chip to the second test line is the same as the signal transmitted by the power supply chip to the first sub-circuit.

12. The display module of claim 11, wherein, The first sub-circuit comprises: A voltage comparator, a first input terminal of the voltage comparator being connected to the power supply chip, a second input terminal being connected to the third test line, and a first output terminal being connected to the driving chip.

13. The display module of claim 11, wherein, Further comprising: A printed circuit board connected to the first trace, the second test line and the third test line; A main board connected to the printed circuit board; Wherein, the power supply chip and the first sub-circuit are located on the main board; and / or, the driving chip is located on the COF.

14. The display module of any one of claims 1-3, wherein, The display panel comprises a plurality of binding parts, and the display module comprises a plurality of COFs, one of the COFs being connected to one of the binding parts.

15. A display device comprising: The display module comprises any one of claims 1-14. The display module comprises any one of claims 1-14.

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