Chip on film package and display device including the same

Abstract

The present disclosure provides a chip on film package and a display device including the same. The chip on film package includes a base film having a top surface and a bottom surface and a circuit area, a source driver chip and a gate driver chip mounted on the circuit area, a first conductive line on the top surface of the base film, a second conductive line on the bottom surface of the base film, and a conductive via connecting the first conductive line and the second conductive line to each other, a first row of bonding pads on the circuit area and connected to the source driver chip, a second row of bonding pads on the circuit area and connected to the source driver chip and the gate driver chip, and a test pad outside the circuit area and connected to the first conductive line and the second conductive line and the conductive via.

Description

Technical Field

[0001] This disclosure relates to chip-on-film (COF) packaging and display devices including such COF packaging, and more specifically, to COF packaging in which different types of semiconductor chips are arranged and display devices including such COF packaging. Background Technology

[0002] Chip-on-film (COF) packaging can include a semiconductor chip mounted on a substrate film, and this semiconductor chip can be electrically connected to an external device via conductive lines in the substrate film and conductive pads connected to the conductive lines. In recent years, with the increasing demand for scaled-down bezels and thinner panels in display devices, the types and number of semiconductor chips mounted in a COF package have gradually increased. Summary of the Invention

[0003] The present invention provides a novel arrangement of conductive lines and conductive pads to ensure a predetermined bonding pitch in a chip-on-film (COF) package in which different types of semiconductor chips are arranged.

[0004] The technical objectives of this invention are not limited to those described above, and other objectives will become apparent to those skilled in the art based on the following description.

[0005] According to one aspect of the present invention, a COF package is provided, comprising a substrate film having a top surface and a bottom surface opposite to each other and further comprising a circuit region. The COF package includes a source driver chip and a gate driver chip mounted on the circuit region on the top surface of the substrate film, a first conductive line on the top surface of the substrate film, a second conductive line on the bottom surface of the substrate film, and a conductive path connecting the first and second conductive lines to each other. Furthermore, the COF package includes: a first row of bonding pads on the top surface of the substrate film on the circuit region and connected to the source driver chip; a second row of bonding pads on the top surface of the substrate film on the circuit region and connected to the source driver chip and the gate driver chip; and test pads on the top surface of the substrate film outside the circuit region and connected to the first and second conductive lines and the conductive path.

[0006] According to another aspect of the present invention, a COF package is provided, comprising a substrate film having a top surface and a bottom surface opposite to each other, the substrate film further comprising a circuit region. The COF package includes a source driver chip and a gate driver chip mounted on the circuit region on the top surface of the substrate film, a first conductive line on the top surface of the substrate film, a second conductive line on the bottom surface of the substrate film, and a conductive path connecting the first and second conductive lines to each other. Furthermore, the COF package includes: a first row of bonding pads on the bottom surface of the substrate film on the circuit region and connected to the gate driver chip; a second row of bonding pads on the bottom surface of the substrate film on the circuit region and connected to the source driver chip; and test pads on the bottom surface of the substrate film outside the circuit region and connected to the first and second conductive lines and the conductive path.

[0007] According to another aspect of the present invention, a display device is provided, comprising a COF package having a substrate film, a display panel facing a portion of the top surface of the substrate film, and a driver printed circuit board (PCB) facing another portion of the top surface of the substrate film. The COF package includes a substrate film, a source driver chip and a gate driver chip mounted on the top surface of the substrate film, a first conductive line on the top surface of the substrate film, a second conductive line on the bottom surface of the substrate film, and a conductive path connecting the first and second conductive lines. Furthermore, the COF package includes: a first row of bonding pads on the top surface of the substrate film and connected to the source driver chip; and a second row of bonding pads on the top surface of the substrate film and connected to the source driver chip and the gate driver chip.

[0008] According to another aspect of the present invention, a display device is provided, comprising a COF package having a substrate film, a display panel facing a portion of the bottom surface of the substrate film, and a driver PCB facing a portion of the top surface of the substrate film. The COF package includes a substrate film, a source driver chip and a gate driver chip mounted on the top surface of the substrate film, a first conductive line on the top surface of the substrate film, a second conductive line on the bottom surface of the substrate film, and a conductive path connecting the first and second conductive lines to each other. Furthermore, the COF package includes: a first row of bonding pads on the bottom surface of the substrate film and connected to the gate driver chip; and a second row of bonding pads on the bottom surface of the substrate film and connected to the source driver chip. Attached Figure Description

[0009] The embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a schematic perspective view of a display device including a chip-on-film (COF) package according to one embodiment;

[0011] Figures 2A to 2E This is a schematic diagram of a COF package according to one embodiment;

[0012] Figure 3 This is a schematic plan view of a portion of a COF package according to one embodiment;

[0013] Figure 4 This is a schematic plan view of a COF package according to one embodiment;

[0014] Figures 5A to 5E This is a schematic diagram of a COF package according to one embodiment;

[0015] Figure 6 This is a schematic plan view of a portion of a COF package according to one embodiment;

[0016] Figure 7 This is a schematic plan view of a COF package according to one embodiment;

[0017] Figure 8 This is a schematic plan view of a COF package according to one embodiment;

[0018] Figure 9A and Figure 9B This is a schematic diagram of a display device including a COF package according to one embodiment; and

[0019] Figure 10A and Figure 10B This is a schematic diagram of a display device including a COF package according to one embodiment. Detailed Implementation

[0020] In the following text, embodiments will be described in detail with reference to the accompanying drawings.

[0021] Figure 1 This is a schematic perspective view of a display device 1000 including a chip-on-film (COF) package according to one embodiment.

[0022] Reference Figure 1 The display device 1000 may include at least one COF package 100, a driver printed circuit board (PCB) 400, and a display panel 500.

[0023] COF package 100 may be a package that includes a semiconductor chip. The semiconductor chip may be a display driver IC (DDI). Different types of semiconductor chips may be arranged on at least one COF package 100. For example, the semiconductor chip may include a source driver chip and a gate driver chip.

[0024] COF package 100 can be located between driver PCB 400 and display panel 500, and connected to each of driver PCB 400 and display panel 500. COF package 100 can receive signals output by driver PCB 400 and send those signals to display panel 500.

[0025] At least one driver circuit chip 410 may be mounted on the driver PCB 400. At least one driver circuit chip 410 may simultaneously or sequentially apply power and signals to the COF package 100.

[0026] Display panel 500 can be, for example, a liquid crystal display (LCD) panel, a light-emitting diode (LED) panel, an organic LED (OLED) panel, and a plasma display panel (PDP).

[0027] The COF package 100 can be electrically connected to the driver interconnect 430 of the driver PCB 400 and the panel interconnect 530 of the display panel 500.

[0028] In some implementations, a COF package 100 may be connected between the driver PCB 400 and the display panel 500. For example, when the display panel 500 provides a small screen area for small-sized devices (e.g., mobile phones) or supports relatively low resolution, the display device 1000 may include only one COF package 100.

[0029] In other embodiments, multiple COF packages 100 may be connected between the driver PCB 400 and the display panel 500. For example, when the display panel 500 provides a large screen area for large-size devices (e.g., televisions) or supports relatively high resolutions, the display device 1000 may include multiple COF packages 100.

[0030] The COF package 100 may be connected to only one side of the display panel 500. However, the inventive concept is not limited thereto, and in some embodiments, at least one COF package 100 may be connected to each of at least two sides of the display panel 500.

[0031] The display panel 500 may include a transparent substrate 510, an image region 520 formed on the transparent substrate 510, and panel interconnects 530. The transparent substrate 510 may be, for example, a glass substrate or a transparent flexible substrate. The plurality of pixels included in the image region 520 may be connected to the corresponding plurality of panel interconnects 530 and operate in response to signals provided by a semiconductor chip mounted on the COF package 100.

[0032] The input pad can be formed at one end of the COF package 100, and the output pad can be formed at the other end. The input pad and the output pad can be connected to the driver interconnect 430 of the driver PCB 400 and the panel interconnect 530 of the display panel 500, respectively, through the anisotropic conductive layer 600.

[0033] The anisotropic conductive layer 600 may include, for example, anisotropic conductive film or anisotropic conductive paste. The anisotropic conductive layer 600 may have a structure in which conductive particles are distributed within an insulating adhesive layer. Furthermore, the anisotropic conductive layer 600 may have anisotropic electrical properties, such that electrodes can be formed only along a second direction (e.g., the Z direction) during connection. Figure 2A While establishing a conductive path, the anisotropic conductive layer 600 can also be positioned between adjacent electrodes along a first direction (e.g., the X direction). Figure 2A Insulation. When the adhesive is melted by applying heat and pressure to the anisotropic conductive layer 600, conductive particles can be arranged between opposing electrodes, for example, between input pads and driver interconnects 430 and between output pads and panel interconnects 530, to form conductive paths between opposing electrodes, while the adhesive can fill between adjacent electrodes to insulate adjacent electrodes from each other.

[0034] The COF package 100 according to this embodiment will be described in detail below.

[0035] Figures 2A to 2E This is a schematic diagram of a COF package 100 according to one embodiment.

[0036] Specifically, Figure 2A This is a plan view of a COF package 100. Figure 2B This is a bottom view of the COF package 100. Additionally, Figure 2C It is along Figure 2A A cross-sectional view taken by line C-C'. Figure 2D It is along Figure 2A A cross-sectional view taken by line D-D'. Figure 2E It is along Figure 2A A sectional view taken from line E-E'.

[0037] Reference Figures 2A to 2E The COF package 100 may include a base film 110, conductive interconnects 120 and conductive pads CP formed in the base film 110, and a semiconductor chip SC mounted on the base film 110.

[0038] The base film 110 may be a flexible film comprising polyimide, which is a material with a high coefficient of thermal expansion and high durability. The materials used for the base film 110 are not limited to this and may include, for example, synthetic resins such as epoxy resin, polyacryl resin, polyether nitrile, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate.

[0039] The base film 110 may include a circuit region 111 defined inside the dicing line 101 and through-hole (PF) regions 112 located at both ends of the base film 110. The circuit region 111 may be a region in which a semiconductor chip SC is mounted. In some embodiments, the dicing line 101 may be an imaginary boundary / dividing line.

[0040] The PF region 112 may be located at both ends of the basement membrane 110 and includes a plurality of PF holes 114. The winding of the basement membrane 110 around a winding shaft (not shown) and the release of the basement membrane 110 from the winding shaft may be controlled by the PF holes 114.

[0041] Typically, because the PF holes 114 are arranged with a constant pitch, the length of the substrate film 110 can be determined by the number of PF holes 114. At the same time, the width and length of the substrate film 110 can be determined by the number and size of the semiconductor chips SC mounted on the substrate film 110, as well as the structure of the conductive interconnects 120 and conductive pads CP formed in the substrate film 110.

[0042] Although not shown, a protective layer may be formed on the top surface 110T and bottom surface 110B of the substrate film 110 to protect / prevent physical and / or chemical damage to the conductive interconnect 120 due to external factors. The protective layer may cover the conductive interconnect 120 formed on the top surface 110T and bottom surface 110B of the substrate film 110 while exposing a predetermined portion of the conductive interconnect 120. The protective layer may include, for example, a solder resist or a dry film resist. Alternatively, the protective layer may include a typical insulating film comprising silicon oxide or silicon nitride.

[0043] The conductive interconnect 120 may include a first conductive line 121, a second conductive line 122, and a conductive path 123. The conductive interconnect 120 may include, for example, aluminum foil or copper foil. In some embodiments, the conductive interconnect 120 may be formed by patterning a metal layer on a substrate film 110 using, for example, a casting process, a lamination process, or an electroplating process.

[0044] The conductive interconnect 120 may include a first conductive line 121 formed on the top surface 110T of the substrate film 110 and a second conductive line 122 formed on the bottom surface 110B of the substrate film 110. That is, the conductive interconnect 120 may be formed on both the top surface 110T and the bottom surface 110B of the substrate film 110. Furthermore, the conductive interconnect 120 may include a conductive path 123 that passes through the substrate film 110 and electrically connects the first conductive line 121 to the second conductive line 122. In some embodiments, a portion of the first conductive line 121 on the top surface 110T of the substrate film 110 (e.g., the portion adjacent to the bonding pads 131 or 132) may overlap in the Z direction with a portion of the second conductive line 122 on the bottom surface 110B of the substrate film 110.

[0045] Conductive pads CP can be formed at each of the portions adjacent to the edges of one and the other ends of the substrate film 110 and connected to the conductive interconnect 120. Conductive pads CP can be formed on the top surface 110T of the substrate film 110.

[0046] The conductive pads CP may include: a first row of bonding pads 131 and a second row of bonding pads 132, connected to the display panel (see reference). Figure 1 (500 in the middle) and driver PCB (refer to Figure 1 400); driver connection pad 150, connected to the driver PCB (refer to 400); Figure 1 (400 in the middle); and test pad 140, configured to test conductive interconnect 120. As used herein, the terms "first row bonding pad" and "second row bonding pad" may refer to the bonding pad of the first row and the bonding pad of the second row, respectively.

[0047] The conductive pad CP can be a first portion of the conductive interconnect 120, or a second portion of the conductive interconnect 120 plated with tin (Sb), gold (Au), nickel (Ni), or lead (Pb). In some embodiments, the conductive pad CP can be electrically connected to the conductive interconnect 120 and includes a separately formed conductive material.

[0048] The semiconductor chip SC can be a DDI used to drive the display. For example, the semiconductor chip SC can be a source driver chip 300, which is configured to generate an image signal using a data signal sent from a timing controller and output the image signal to the display panel (see reference). Figure 1 (refer to 500). Alternatively, the semiconductor chip SC can be a gate driver chip 200 configured to output a scan signal, including on / off signals of transistors, to the display panel (see 500). Figure 1 (500 in the middle).

[0049] Although one gate driver chip 200 and two source driver chips 300 are shown, the type and number of semiconductor chips SC are not limited thereto. However, given the display device (see reference...) Figure 1 Due to the characteristic of 1000, the number of source driver chips 300 can be greater than or equal to the number of gate driver chips 200.

[0050] The semiconductor chip SC is not limited to the gate driver chip 200 or the source driver chip 300. For example, when the COF package 100 is combined with an electronic device other than the display device 1000, the semiconductor chip SC can be a chip configured to drive the corresponding electronic device.

[0051] The semiconductor chip SC can be disposed in the circuit region 111 of the substrate film 110 and mounted on the substrate film 110 using a flip-chip bonding process. In other words, the connection terminals 221, such as solder balls... Figure 2D The chip pad 211 can be arranged on the active surface exposed to the gate driver chip 200. Figure 2D On, such as solder ball connection terminal 321 ( Figure 2C Chip pads 311 can be arranged on the active surface of each of the multiple source driver chips 300. Figure 2C Furthermore, connection terminals 221 and 321 can be physically and electrically coupled to conductive interconnect 120, so that gate driver chip 200 and multiple source driver chips 300 can be mounted on substrate film 110.

[0052] A portion of the chip pad 211 of the gate driver chip 200 and a portion of the chip pad 311 of each of the plurality of source driver chips 300 can be used as an input terminal, and another portion of the chip pad 211 of the gate driver chip 200 and another portion of the chip pad 311 of each of the plurality of source driver chips 300 can be used as an output terminal.

[0053] Although not shown, the semiconductor chip SC can be sealed with a sealing member to protect / prevent physical and / or chemical damage to the semiconductor chip SC due to external factors. Furthermore, an underfill (not shown) can be filled between the semiconductor chip SC and the substrate film 110. The underfill can be formed using, for example, a capillary underfill process. The underfill may include, for example, epoxy resin, but the inventive concept is not limited thereto.

[0054] In recent years, with the increasing demand for proportional reduction of bezels and thinning of panels in display devices 1000, the types and number of semiconductor chips SC mounted in a COF package 100 have shown a gradual increasing trend. Therefore, the number of conductive interconnects 120 and conductive pads CP connected to the semiconductor chips SC can also be increased. Thus, the efficient arrangement of conductive interconnects 120 and conductive pads CP within the limited circuit region 111 of the substrate film 110 with a predetermined bonding pitch can significantly affect the improvement of the productivity and economic efficiency of the COF package 100.

[0055] As used herein, the bonding pitch can refer to the distance measured between two corresponding points of adjacent conductive interconnects 120 in a direction perpendicular to the length direction of the conductive interconnect 120, or the distance measured between two corresponding center points of adjacent conductive pads CP. For example, the bonding pitch can refer to the distance measured in the X direction between the centers of two adjacent first conductive lines 121, or the distance measured in the X direction between the centers of two adjacent first row bonding pads 131.

[0056] Therefore, the COF package 100 according to this embodiment can be designed to realize conductive interconnects 120 and conductive pads CP with a predetermined bonding pitch while arranging different types of semiconductor chips SC (i.e., at least one gate driver chip 200 and at least two source driver chips 300) on the substrate film 110.

[0057] For this purpose, connect to the display panel (see reference). Figure 1 The conductive pads CP of the 500 chip may include a first row of bonding pads 131 and a second row of bonding pads 132. Here, the conductive interconnects 120 may be configured such that the first row of bonding pads 131 is connected (e.g., electrically connected) only to the source driver chip 300, and the conductive interconnects 120 may be configured such that the second row of bonding pads 132 is connected (e.g., electrically connected) to both the gate driver chip 200 and the source driver chip 300. For example, the second row of bonding pads 132 may include a first bonding pad electrically connected to the gate driver chip 200 through a first portion of a conductive path 123, and may also include a second bonding pad electrically connected to the source driver chip 300 through a second portion of a conductive path 123.

[0058] The distance between the first row of bonding pads 131 and the source driver chip 300 can be less than the distance between the second row of bonding pads 132 and the source driver chip 300, and the first row of bonding pads 131 and the second row of bonding pads 132 can be arranged in a zigzag pattern in the X and Y directions. Therefore, the first row of bonding pads 131 and the second row of bonding pads 132 can be non-collinear in the Y direction, which is spaced from the source driver chip 300.

[0059] The source driver chip 300 may include a first source driver chip 301 and a second source driver chip 302. The first source driver chip 301 may have some signal connections to a first row bonding pad 131 and other signal connections to a second row bonding pad 132. Similarly, the second source driver chip 302 may have some signal connections to the first row bonding pad 131 and other signal connections to the second row bonding pad 132.

[0060] The connection relationship between the source driver chip 300 and the first and second row bonding pads 131 and 132 will now be described in detail. First, the first row bonding pad 131 can be connected (e.g., electrically connected) to the source driver chip 300 via a first conductive line 121 (i.e., through the top surface 110T of the substrate film 110), without passing through the conductive path 123. Second, the second row bonding pad 132 can be indirectly connected (e.g., electrically connected) to the source driver chip 300 via the conductive path 123 arranged between the first row bonding pad 131 and the source driver chip 300 and the conductive path 123 arranged between the second row bonding pad 132 and the dicing line 101 near the second row bonding pad 132.

[0061] Unlike the source driver chip 300, the gate driver chip 200 can have all signal connections to the second row bonding pad 132.

[0062] The connection between the gate driver chip 200 and the second row bonding pad 132 will now be described in detail. The second row bonding pad 132 can be indirectly connected (e.g., electrically connected) to the gate driver chip 200 through conductive paths 123 arranged between the gate driver chip 200 and the source driver chip 300 and conductive paths 123 arranged between the second row bonding pad 132 and the cleaving line 101 near the second row bonding pad 132.

[0063] That is, given the configuration of the semiconductor chip SC, a relatively large number of conductive pads CP can be used for signal connections, and the source driver chips 300, provided in a relatively large quantity, can exclusively use the first row of bonding pads 131, while additional conductive pads CP can use a portion of the second row of bonding pads 132. In this case, because the first conductive line 121 configured to connect the source driver chip 300 to the first row of bonding pads 131 is formed on the top surface 110T of the substrate film 110, the first conductive line 121 can be relatively free in its arrangement relationship with the second conductive line 122 formed on the bottom surface 110B of the substrate film 110. Furthermore, because the source driver chip 300 is located at a relatively small distance from the first row of bonding pads 131, and the first conductive line 121 is formed in a straight shape, the routing path can be reduced / minimized, thus facilitating fast signal transmission. That is, the conductive interconnect 120 can be designed to have a predetermined bonding pitch on the top surface 110T of the substrate film 110.

[0064] Furthermore, given the configuration of the semiconductor chip SC, the gate driver chip 200, which uses a relatively small number of conductive pads CP for signal connections and is provided in a relatively small quantity, can utilize the remaining portion of the second row of bonding pads 132. In this case, because the second conductive line 122, configured to connect the gate driver chip 200 to the second row of bonding pads 132, is formed on the bottom surface 110B of the substrate film 110, the second conductive line 122 can be relatively free in its arrangement relationship with the first conductive line 121 formed on the top surface 110T of the substrate film 110. Although a portion of the second row of bonding pads 132 is electrically connected to the source driver chip 300, the signal connections of the source driver chip 300 can utilize the first row of bonding pads 131. That is, the conductive interconnect 120 can be designed to have a predetermined bonding pitch on the bottom surface 110B of the substrate film 110.

[0065] Unlike typical memory semiconductor packages, the COF package 100 may include test pads 140 formed in a substrate film 110. Test pads 140 can be used to test for connection faults, such as short circuits in the first conductive line 121, the second conductive line 122, and the conductive path 123. However, because test pads 140 may play a less significant role after the test results are examined and it is determined whether the COF package 100 has a connection fault, test pads 140 may be positioned outside the cut line 101 (i.e., outside the circuit region 111).

[0066] Test pads 140, configured to test the conductive interconnects 120 connecting the source driver chip 300 to the first row of bonding pads 131, can be disposed on the top surface 110T of the substrate film 110. Among the conductive paths 123, those disposed between the second row of bonding pads 132 and the test pads 140 can be disposed outside the circuit region 111. That is, the COF package 100 can be designed to reduce / minimize the number of conductive paths 123 disposed in the circuit region 111, such that the conductive interconnects 120 have a predetermined bonding pitch.

[0067] Additionally, test pads 140 configured to test the conductive interconnects 120 connecting the gate driver chip 200 to the second row bonding pads 132 can be arranged on the top surface 110T of the substrate film 110.

[0068] In some embodiments, the test pads 140 may be arranged only in the region adjacent to the second row of bonding pads 132. In other words, the test pads 140 may be arranged only in the region adjacent to one edge of the base film 110. However, the arrangement of the test pads 140 is not limited to this.

[0069] As a result, in the COF package 100 according to this embodiment, while at least one gate driver chip 200 and at least two source driver chips 300 are arranged on the substrate film 110, the conductive interconnects 120 and conductive pads CP having a predetermined bonding spacing can be designed so that they do not cross or overlap each other, and the test pads 140 configured to test the conductive interconnects 120 can be arranged so as not to affect the wiring. Therefore, the productivity and economic efficiency of the COF package 100 can be improved.

[0070] Figure 3 This is a schematic plan view of a portion of a COF package 100a according to one embodiment.

[0071] The following describes most of the components included in the COF package 100a, as well as the materials included in the components and references. Figures 2A to 2E The descriptions are essentially the same or similar. Therefore, for the sake of brevity, the COF package 100a according to this embodiment can be mainly described as similar to the COF package described above (refer to...). Figure 2A The difference between 100 and 100.

[0072] Figure 3 The first and second row bonding pads 131 and 132 on the top surface 110T of the substrate film 110 are shown, as well as the test pad 140 electrically connected to the first and second row bonding pads 131 and 132 via the first conductive line 121.

[0073] The test pads 140 may include a first row of test pads 141 and a second row of test pads 142. The distance between the first row of test pads 141 and the second row of bonding pads 132 may be less than the distance between the second row of test pads 142 and the second row of bonding pads 132, and the first row of test pads 141 and the second row of test pads 142 may be arranged in a zigzag pattern in the X and Y directions.

[0074] Since the first row of test pads 141 and the second row of test pads 142 can play an insignificant role after checking the test results and identifying connection faults in the COF package 100a, the first row of test pads 141 and the second row of test pads 142 can be arranged outside the cut line 101 (i.e., outside the circuit area 111).

[0075] The first row of bonding pads 131 and the second row of bonding pads 132 can be arranged parallel in the X direction (e.g., collinear in the Y direction). That is, unlike the first row of test pads 141 and the second row of test pads 142, the first row of bonding pads 131 and the second row of bonding pads 132 can be arranged in a non-zigzag pattern in the X and Y directions.

[0076] Therefore, the first row of bonding pads 131 can be connected to the second row of test pads 142 via the first conductive line 121, and the second row of bonding pads 132 can be connected to the first row of test pads 141 via the first conductive line 121.

[0077] Furthermore, the first conductive line 121 configured to connect the first row of bonding pads 131 to the second row of test pads 142 may have at least one bent portion, and the first conductive line 121 configured to connect the second row of bonding pads 132 to the first row of test pads 141 may have a straight shape.

[0078] Although not shown, in other embodiments, the first row of bonding pads 131 and the second row of bonding pads 132 may be arranged in a zigzag pattern in both the X and Y directions. In this case, the first row of test pads 141 and the second row of test pads 142 may be arranged parallel in the X direction (e.g., collinear in the Y direction). That is, the first row of test pads 141 and the second row of test pads 142 may not be arranged in a zigzag pattern in both the X and Y directions.

[0079] Figure 4 This is a schematic plan view of a COF package 100b according to one embodiment.

[0080] The following describes most of the components in the COF package 100b, as well as the materials and references included in those components. Figures 2A to 2EThe descriptions are essentially the same or similar. Therefore, for the sake of brevity, the COF package 100b according to this embodiment can be mainly described as similar to the COF package described above (refer to...). Figure 2A The difference between 100 and 100.

[0081] Reference Figure 4 The COF package 100b may include a substrate film 110, conductive interconnects 120 and conductive pads CP formed in the substrate film 110, and a semiconductor chip SC mounted on the substrate film 110.

[0082] Although two gate driver chips 200 and two source driver chips 300 are shown, the type and number of semiconductor chips SC are not limited thereto. This is in view of the display device (see reference). Figure 1 Due to the characteristic of 1000, the number of source driver chips 300 can be greater than or equal to the number of gate driver chips 200.

[0083] The gate driver chip 200 may include a first gate driver chip 201 and a second gate driver chip 202. The first gate driver chip 201 may have a signal connection to the second row bonding pad 132. Similarly, the second gate driver chip 202 may have a signal connection to the second row bonding pad 132.

[0084] The gate driver chip 200 and the source driver chip 300 can be arranged parallel in the X direction (e.g., collinear in the Y direction). Furthermore, the gate driver chip 200 can be arranged at a predetermined distance from the source driver chip 300 in the Y direction.

[0085] The connection between the first gate driver chip 201 and the second row bonding pad 132 will now be described in detail. The second row bonding pad 132 can be indirectly connected to the first gate driver chip 201 through a conductive path 123 arranged between the first gate driver chip 201 and the first source driver chip 301 and a conductive path 123 arranged between the second row bonding pad 132 and the dicing line 101 near the second row bonding pad 132.

[0086] The connection between the second gate driver chip 202 and the second row bonding pad 132 will now be described in detail. The second row bonding pad 132 can be indirectly connected to the second gate driver chip 202 through conductive paths 123 arranged between the second gate driver chip 202 and the second source driver chip 302, and conductive paths 123 arranged between the second row bonding pad 132 and the dicing line 101 near the second row bonding pad 132.

[0087] According to this embodiment, the COF package 100b can be designed to realize conductive interconnects 120 and conductive pads CP with a predetermined bonding pitch while arranging at least two gate driver chips 200 and at least two source driver chips 300 on the substrate film 110.

[0088] Figures 5A to 5E This is a schematic diagram of a COF package 100c according to one embodiment.

[0089] Specifically, Figure 5A This is a plan view of the COF package 100c. Figure 5B This is a bottom view of the COF package 100c. Additionally, Figure 5C It is along Figure 5A A cross-sectional view taken by line C-C'. Figure 5D It is along Figure 5A A cross-sectional view taken by line D-D'. Figure 5E It is along Figure 5A A sectional view taken from line E-E'.

[0090] The following describes most of the components included in the COF package 100c, as well as the materials included in the components and references. Figures 2A to 2E The descriptions are essentially the same or similar. Therefore, for the sake of brevity, the COF package 100c according to this embodiment can be mainly described as similar to the COF package described above (refer to...). Figure 2A The difference between 100 and 100.

[0091] Reference Figures 5A to 5E The COF package 100c may include a base film 110, conductive interconnects 120 and conductive pads CP formed in the base film 110, and a semiconductor chip SC mounted on the base film 110.

[0092] The conductive interconnect 120 may include a first conductive line 121, a second conductive line 122, and a conductive path 123. The conductive interconnect 120 may include the first conductive line 121 formed on the top surface 110T of the substrate film 110 and the second conductive line 122 formed on the bottom surface 110B of the substrate film 110. That is, the conductive interconnect 120 may be formed on both the top surface 110T and the bottom surface 110B of the substrate film 110. Furthermore, the conductive interconnect 120 may include a conductive path 123 that passes through the substrate film 110 and electrically connects the first conductive line 121 to the second conductive line 122.

[0093] Conductive pads CP can be formed at each of the portions adjacent to the edges of one and the other ends of the substrate film 110 and connected to the conductive interconnect 120. The conductive pads CP can be formed on the top surface 110T or the bottom surface 110B of the substrate film 110. Specifically, driver connection pads 150 can be arranged on the top surface 110T of the substrate film 110 and connected to the driver PCB (see reference). Figure 1 (Referring to 400). First row bonding pads 131 and second row bonding pads 132, as well as test pads 140 including first row test pads 141 and second row test pads 142, can be provided on the bottom surface 110B of the substrate film 110. First row bonding pads 131 and second row bonding pads 132 can be connected to a display panel (see reference 400). Figure 1 (500 in the middle), and the first row of test pads 141 and the second row of test pads 142 can be used to test conductive interconnects 120.

[0094] According to this embodiment, the COF package 100c can be designed to realize conductive interconnects 120 and conductive pads CP with a predetermined bonding pitch while arranging at least one gate driver chip 200 and at least two source driver chips 300 on the substrate film 110.

[0095] Although a gate driver chip 200 and two source driver chips 300 are shown, the inventive concept is not limited thereto. However, in view of display devices (see reference 1), Figure 1 Due to the characteristic of 1000, the number of source driver chips 300 can be greater than or equal to the number of gate driver chips 200.

[0096] Connect to the display panel (see reference) Figure 1 The conductive pad CP of the substrate 110 (500) may include a first row of bonding pads 131 and a second row of bonding pads 132. Both the first row of bonding pads 131 and the second row of bonding pads 132 may be arranged on the bottom surface 110B of the substrate 110.

[0097] Here, the conductive interconnect 120 can be configured such that the first row of bonding pads 131 are connected only to the gate driver chip 200, and the conductive interconnect 120 can be configured such that the second row of bonding pads 132 are connected only to the source driver chip 300.

[0098] The distance between the first row of bonding pads 131 and the source driver chip 300 can be less than the distance between the second row of bonding pads 132 and the source driver chip 300, and the first row of bonding pads 131 and the second row of bonding pads 132 can be arranged in a Z-shape in the X and Y directions.

[0099] The source driver chip 300 may include a first source driver chip 301 and a second source driver chip 302. The first source driver chip 301 may have signal connections only to the second row bonding pad 132. Similarly, the second source driver chip 302 may have signal connections only to the second row bonding pad 132.

[0100] The connection between the source driver chip 300 and the second row bonding pad 132 will now be described in detail. The source driver chip 300 may have all signal connections to the second row bonding pad 132. The second row bonding pad 132 may be connected to the source driver chip 300 via a first conductive line 121 and a conductive path 123, which is arranged between the second row bonding pad 132 and a cut line 101 adjacent to the second row bonding pad 132.

[0101] Furthermore, the connection relationship between the gate driver chip 200 and the first row bonding pad 131 will now be described in detail. The gate driver chip 200 may have all signal connections to the first row bonding pad 131. The first row bonding pad 131 can be connected to the gate driver chip 200 via a second conductive line 122 and a conductive path 123 arranged between the gate driver chip 200 and the source driver chip 300.

[0102] That is, given the configuration of the semiconductor chip SC, the source driver chips 300, which use a relatively large number of conductive pads CP for signal connection and are provided in a relatively large quantity, can exclusively use the second row of bonding pads 132. In this case, since the first conductive line 121 configured to connect the source driver chip 300 to the second row of bonding pads 132 is formed on the top surface 110T of the substrate film 110, the first conductive line 121 can be relatively free in its arrangement relationship with the second conductive line 122 formed on the bottom surface 110B of the substrate film 110.

[0103] Furthermore, given the configuration of the semiconductor chip SC, a relatively small number of conductive pads CP can be used for signal connections, and the gate driver chips 200, provided in a relatively small quantity, can exclusively use the first row of bonding pads 131. In this case, because the second conductive line 122, configured to connect the gate driver chip 200 to the first row of bonding pads 131, is formed on the bottom surface 110B of the substrate film 110, the second conductive line 122 can be relatively free in its arrangement relationship with the first conductive line 121 formed on the top surface 110T of the substrate film 110. Here, some of the first row of bonding pads 131 can be formed as dummy pads not connected to the first conductive line 121 and the second conductive line 122. Therefore, the dummy pads can provide free space for arranging the conductive interconnects 120 and the conductive pads CP at a predetermined bonding pitch.

[0104] Unlike typical memory semiconductor packages, the COF package 100c may include test pads 140 formed in the substrate film 110. The test pads 140 can be used to test for connection faults, such as short circuits in the first conductive line 121, the second conductive line 122, and the conductive path 123. However, because the test pads 140 may play a less significant role after the test results are examined and connection faults in the COF package 100c are identified, the test pads 140 may be positioned outside the cut line 101 (i.e., outside the circuit area).

[0105] The second row of test pads 142, configured to test the conductive interconnects 120 connecting the source driver chip 300 to the second row of bonding pads 132, can be arranged on the bottom surface 110B of the substrate film 110. Similarly, the first row of test pads 141, configured to test the conductive interconnects 120 connecting the gate driver chip 200 to the first row of bonding pads 131, can be arranged on the bottom surface 110B of the substrate film 110.

[0106] In some embodiments, the first row of test pads 141 connected to the first row of bonding pads 131 may be arranged in an area adjacent to the driver bonding pads 150. Furthermore, the second row of test pads 142 connected to the second row of bonding pads 132 may be arranged in an area adjacent to the second row of bonding pads 132. In other words, the test pads 140 may be divided and arranged in areas adjacent to two opposite edges of the substrate film 110. However, the arrangement of the test pads 140 is not limited to this.

[0107] As a result, in the COF package 100c according to this embodiment, while at least one gate driver chip 200 and at least two source driver chips 300 are arranged on the substrate film 110, the conductive interconnects 120 and conductive pads CP having a predetermined bonding pitch can be designed so that they do not cross or overlap each other, and the test pads 140 configured to test the conductive interconnects 120 can be arranged so as not to affect the wiring. Therefore, the productivity and economic efficiency of the COF package 100c can be improved.

[0108] Figure 6 This is a schematic plan view of a portion of a COF package 100d according to one embodiment.

[0109] The following describes most of the components included in the COF package 100d, as well as the materials included in the components and references. Figures 5A to 5E The descriptions are essentially the same or similar. Therefore, for the sake of brevity, the COF package 100d according to this embodiment can be mainly described as similar to the COF package described above (refer to...). Figure 5A The difference between 100c in the middle.

[0110] Figure 6 The second row test pad 142 is shown to be electrically connected to the second row bonding pad 132 via the second conductive line 122 at the bottom surface 110B of the substrate film 110.

[0111] Test pads (refer to) Figure 5A 140 in the middle) may include the first row of test pads (refer to Figure 5A The first row of test pads 141 and the second row of test pads 142. The distance between the second row of test pads 142 and the second row of bonding pads 132 can be less than the distance between the second row of test pads 142 and the first row of bonding pads 131, and the first row of test pads 141 and the second row of test pads 142 can be arranged separately in different areas of the base film 110.

[0112] Because the second row of test pads 142 can play a minor role after checking the test results and determining whether the COF package 100d has a connection fault, the second row of test pads 142 can be arranged outside the cut line 101 (i.e., outside the circuit area).

[0113] The first row of bonding pads 131 and the second row of bonding pads 132 can be arranged parallel in the X direction (e.g., collinear in the Y direction). That is, the first row of bonding pads 131 and the second row of bonding pads 132 can be arranged in a non-zigzag pattern in the X and Y directions.

[0114] The first row of bonding pads 131 can be electrically connected to the first row of test pads 141 via a second conductive line 122, and the second row of bonding pads 132 can be electrically connected to the second row of test pads 142 via another second conductive line 122. Furthermore, each of the second conductive lines 122 configured to connect the first row of bonding pads 131 to the first row of test pads 141 and the second conductive lines 122 configured to connect the second row of bonding pads 132 to the second row of test pads 142 can have a straight shape.

[0115] Although not shown, in other embodiments, the first row of bonding pads 131 and the second row of bonding pads 132 may be arranged in a zigzag pattern in the X and Y directions.

[0116] Figure 7 This is a schematic plan view of a COF package 100e according to one embodiment.

[0117] The following describes most of the components included in the COF package 100e, as well as the materials included in the components and references. Figures 5A to 5E The descriptions are essentially the same or similar. Therefore, for the sake of brevity, the COF package 100e according to this embodiment can be mainly described as similar to the COF package described above (refer to...). Figure 5AThe difference between 100c in the middle.

[0118] Figure 7 Test pad 140 is shown, which is connected to the second conductive line (see reference). Figure 5B 122) is electrically connected to the first row bonding pad 131 and the second row bonding pad 132 and is formed on the bottom surface 110B of the substrate film 110.

[0119] Unlike typical memory semiconductor packages, the COF package 100e may include test pads 140 within the substrate film 110. Test pads 140 can be used to test for connection faults, such as the first conductive line 121, the second conductive line (see reference 121). Figure 5B The short circuit in 122) and conductive path 123. However, since the test pad 140 can play a minor role after checking the test results and determining whether the COF package 100e has a connection fault, the test pad 140 can be arranged outside the cut line 101 (i.e., outside the circuit area).

[0120] Test pads 140 configured to test the conductive interconnects 120 connecting the source driver chip 300 to the conductive interconnects 120 of the second row bonding pads 132 can be arranged on the bottom surface 110B of the substrate film 110. Similarly, test pads 140 configured to test the conductive interconnects 120 connecting the gate driver chip 200 to the conductive interconnects 131 of the first row bonding pads can be arranged on the bottom surface 110B of the substrate film 110.

[0121] In some embodiments, the test pads 140 may be arranged only in the region adjacent to the second row of bonding pads 132. In other words, the test pads 140 configured to test the first row of bonding pads 131 and the second row of bonding pads 132 may not be divided but may be arranged only in the region adjacent to one edge of the base film 110. However, the arrangement of the test pads 140 is not limited to this.

[0122] Figure 8 This is a schematic plan view of a COF package 100f according to one embodiment.

[0123] The following describes most of the components included in the COF package 100f, as well as the materials included in the components and references. Figures 5A to 5E The descriptions are essentially the same or similar. Therefore, for the sake of brevity, the COF package 100f according to this embodiment can be mainly described as similar to the COF package described above (refer to...). Figure 5A The difference between 100c in the middle.

[0124] Reference Figure 8The COF package 100f may include a substrate film 110, conductive interconnects 120 and conductive pads CP formed in the substrate film 110, and a semiconductor chip SC mounted on the substrate film 110.

[0125] Despite Figure 8 The diagram shows two gate driver chips 200 and two source driver chips 300, but the inventive concept is not limited thereto. However, considering the display device (see reference 1), Figure 1 Due to the characteristic of 1000, the number of source driver chips 300 can be greater than or equal to the number of gate driver chips 200.

[0126] The gate driver chip 200 may include a first gate driver chip 201 and a second gate driver chip 202. The first gate driver chip 201 may have signal connections only to the first row bonding pad 131. Similarly, the second gate driver chip 202 may have signal connections only to the first row bonding pad 131.

[0127] The gate driver chip 200 and the source driver chip 300 can be arranged parallel in the X direction (e.g., collinear in the Y direction). Furthermore, the gate driver chip 200 can be arranged at a predetermined distance from the source driver chip 300 in the Y direction.

[0128] The connection relationship between the first gate driver chip 201 and the first row bonding pad 131 will now be described in detail. The first row bonding pad 131 can be connected via a second conductive line (see reference). Figure 5B 122) and conductive path 123 are connected to the first gate driver chip 201, and the conductive path 123 is arranged between the first gate driver chip 201 and the first source driver chip 301.

[0129] The connection between the second gate driver chip 202 and the second row bonding pad 132 will now be described in detail. The first row bonding pad 131 can be connected via the second conductive line (see reference). Figure 5B The conductive path 122) and conductive path 123 are connected to the second gate driver chip 202, and the conductive path 123 is arranged between the second gate driver chip 202 and the second source driver chip 302.

[0130] According to this embodiment, the COF package 100f can be designed to realize conductive interconnects 120 and conductive pads CP with a predetermined bonding pitch while arranging at least two gate driver chips 200 and at least two source driver chips 300 on the substrate film 110.

[0131] Figure 9A and Figure 9BThis is a schematic diagram of a display device 1000a including a COF package 100' according to one embodiment.

[0132] Specifically, Figure 9A This is a cross-sectional view of the display device 1000a. Figure 9B yes Figure 9A A magnified view of a portion of area BB.

[0133] Reference Figure 9A and Figure 9B The display device 1000a may include a COF package 100', a driver PCB 400, and a display panel 500.

[0134] The display panel 500 may include a transparent substrate 510, an image region 520 formed on the transparent substrate 510, and a plurality of panel interconnects 530. In some embodiments, the image region 520 and the plurality of panel interconnects 530 may be formed on the front surface 510T of the transparent substrate 510. The plurality of pixels included in the image region 520 may be connected to the plurality of panel interconnects 530.

[0135] Here, COF package 100' can refer only to the above reference. Figures 2A to 2E A portion of circuit region 111 cut along dicing line 101 in the described COF package 100.

[0136] A portion of the COF package 100' may face a portion of the display panel 500. Specifically, a portion of the substrate film 110 on which bonding pads 130 are disposed may be opposite a portion of the front surface 510T of the transparent substrate 510. The bonding pads 130 may include a first row of bonding pads (see reference). Figure 2A 131 in the middle) and the second row of bonding pads (refer to) Figure 2A (132 in the middle).

[0137] COF package 100' can receive signals output from driver PCB 400 and send those signals to display panel 500. At least one driver circuit chip (see reference) is capable of simultaneously or sequentially applying power and signals to COF package 100'. Figure 1 The 410 in the middle can be installed on the driver PCB 400.

[0138] COF package 100' may include source driver chip 300, gate driver chip 200, and a first conductive line formed on the top surface of substrate film 110 (see reference). Figure 2C 121), and a second conductive line formed on the bottom surface of the base film 110 (refer to 121). Figure 2C 122), and a conductive path configured to connect the first conductive line 121 and the second conductive line 122 to each other (see reference 122). Figure 2C(123 in the middle).

[0139] The display panel 500 may have a front surface 510T of a transparent substrate 510 and a rear surface 510B opposite to the front surface 510T, and an image area 520 including multiple pixels is arranged on the front surface 510T. The COF package 100' may be bent and fixed (i.e., attached) to the display panel 500 toward the rear surface 510B of the display panel 500, and the driver PCB 400 may face the rear surface 510B of the display panel 500.

[0140] The display device 1000a according to this embodiment can achieve conductive interconnects with a predetermined bonding pitch while arranging at least one gate driver chip 200 and at least two source driver chips 300 on the substrate film 110 of the COF package 100' (see reference). Figure 2C 120 in the middle) and conductive pads (refer to Figure 2A (CP in the COF package). Therefore, the productivity and economic efficiency of the display device 1000a, including the COF package 100', can be improved.

[0141] Figure 10A and Figure 10B This is a schematic diagram of a display device 1000b including a COF package 100c' according to one embodiment.

[0142] Specifically, Figure 10A This is a cross-sectional view of display device 1000b. Figure 10B yes Figure 10A A magnified view of a portion of area BB.

[0143] Reference Figure 10A and Figure 10B The display device 1000b may include a COF package 100c', a driver PCB 400, and a display panel 500.

[0144] The display panel 500 may include a transparent substrate 510, an image region 520 formed on the transparent substrate 510, and a plurality of panel interconnects 530. In some embodiments, the image region 520 and the plurality of panel interconnects 530 may be formed on the front surface 510T of the transparent substrate 510. The plurality of pixels included in the image region 520 may be connected to the plurality of panel interconnects 530.

[0145] Here, COF package 100c' can refer only to the above reference. Figures 5A to 5E A portion of circuit region 111 cut along dicing line 101 in the described COF package 100c.

[0146] A portion of the COF package 100c' may face a portion of the display panel 500. Specifically, a portion of the substrate film 110 on which bonding pads 130 are disposed may be opposite a portion of the front surface 510T of the transparent substrate 510. The bonding pads 130 may include a first row of bonding pads (see reference). Figure 5A 131 in the middle) and the second row of bonding pads (refer to) Figure 5A (132 in the middle).

[0147] The COF package 100c' can receive signals output from the driver PCB 400 and send those signals to the display panel 500. At least one driver circuit chip (see reference) is capable of simultaneously or sequentially applying power and signals to the COF package 100c'. Figure 1 The 410 in the middle can be installed on the driver PCB 400.

[0148] COF package 100c' may include source driver chip 300, gate driver chip 200, and a first conductive line formed on the top surface of substrate film 110 (see reference). Figure 5C 121), and a second conductive line formed on the bottom surface of the base film 110 (refer to 121). Figure 5C 122 in the middle), and a conductive path configured to connect the first conductive line 121 and the second conductive line 122 to each other (see reference 122). Figure 5C (123 in the middle).

[0149] The display panel 500 may have a front surface 510T of a transparent substrate 510 and a rear surface 510B opposite to the front surface 510T, and an image region 520 including multiple pixels is arranged on the front surface 510T. The COF package 100c' may be bent toward the rear surface 510B of the display panel 500 and fixed to the display panel 500, and the driver PCB 400 may be arranged spaced apart from the rear surface 510B of the display panel 500 and having the COF package 100c' therebetween.

[0150] According to this embodiment, the display device 1000b can achieve conductive interconnects with a predetermined pitch while arranging one gate driver chip 200 and at least two source driver chips 300 on the substrate film 110 of the COF package 100c' (see reference). Figure 5C 120 in the middle) and conductive pads (refer to Figure 5A (CP in the COF package). Therefore, the productivity and economic efficiency of the display device 1000b, including the COF package 100c', can be improved.

[0151] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the scope of the appended claims.

[0152] This application claims the benefit of Korean Patent Application No. 10-2019-0112367, filed on September 10, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A chip-on-film package, comprising: The basement membrane has a top surface and a bottom surface that are opposite to each other, and also has a circuit region; The source driver chip and the gate driver chip are mounted on the top surface of the substrate film on the circuit region and are respectively arranged in different rows; A first conductive line on the top surface of the base film, a second conductive line on the bottom surface of the base film, and a conductive path connecting the first conductive line and the second conductive line to each other. The bonding pads of the first row are on the top surface of the substrate film on the circuit region and are connected only to the source driver chip via the first conductive line. The bonding pads of the first row are spaced apart from the source driver chip and the gate driver chip along the top surface of the substrate film. The bonding pads of the second row are on the circuit region on the top surface of the substrate film and are connected to the source driver chip and the gate driver chip via the second conductive line. The bonding pads of the second row are spaced apart from the source driver chip and the gate driver chip along the top surface of the substrate film. as well as The test pads are located on the top surface of the substrate film outside the circuit region and are connected to the first conductive line, the second conductive line, and the conductive path. The first distance between the bonding pads in the first row and the source driver chip is less than the second distance between the bonding pads in the second row and the source driver chip.

2. The chip-on-film package of claim 1, wherein the conductive path is connected to the test pad outside the circuit region.

3. The chip-on-film packaging according to claim 1, The source driver chip includes at least two source driver chips, and the gate driver chip includes at least one gate driver chip. The number of source driver chips is greater than or equal to the number of gate driver chips.

4. The chip-on-film package according to claim 1, wherein the bonding pads of the first row and the bonding pads of the second row are arranged in a zigzag pattern.

5. The chip-on-film package of claim 1, wherein the bonding pads of the first row are connected to the source driver chip via the first conductive line, without passing through the conductive path.

6. The chip-on-film package of claim 1, wherein the bonding pads of the second row are connected to the source driver chip via the conductive path.

7. The chip-on-film package of claim 1, wherein the bonding pads of the second row are connected to the gate driver chip via the conductive path.

8. The chip-on-film package of claim 1, wherein the test pads comprise a plurality of test pads, each of the plurality of test pads being in a region adjacent to the edge of the substrate film.

9. The chip-on-film package of claim 1, wherein a portion of the first conductive line on the top surface of the substrate film overlaps with a portion of the second conductive line on the bottom surface of the substrate film.

10. The chip-on-film package of claim 1, wherein the test pad is connected to the bonding pad of the second row via the first conductive line.

11. A chip-on-film package, comprising: A basement membrane having a top surface and a bottom surface opposite to each other, the basement membrane also having a circuit region; The source driver chip and the gate driver chip are mounted on the top surface of the substrate film on the circuit region and are respectively arranged in different rows; A first conductive line on the top surface of the base film, a second conductive line on the bottom surface of the base film, and a conductive path connecting the first conductive line and the second conductive line to each other. The bonding pads of the first row are on the circuit region on the bottom surface of the substrate film and are connected only to the gate driver chip via the second conductive line. The bonding pads of the first row are spaced apart along the bottom surface of the substrate film from the regions of the bottom surface of the substrate film corresponding to the source driver chip and the gate driver chip. The bonding pads in the second row are on the circuit area on the bottom surface of the substrate film and are connected only to the source driver chip via the first conductive line. The bonding pads in the second row are spaced apart along the bottom surface of the substrate film from the areas of the bottom surface of the substrate film corresponding to the source driver chip and the gate driver chip. as well as The test pads are located on the bottom surface of the substrate film outside the circuit region and are connected to the first conductive line, the second conductive line, and the conductive path. The first distance between the bonding pads in the first row and the source driver chip is less than the second distance between the bonding pads in the second row and the source driver chip.

12. The chip-on-film packaging according to claim 11, The source driver chip includes at least two source driver chips, and the gate driver chip includes at least one gate driver chip. The number of source driver chips is greater than or equal to the number of gate driver chips.

13. The chip-on-film packaging according to claim 11, The bonding pads in the first row and the bonding pads in the second row are arranged in a Z-shape, and Some of the bonding pads in the first row are dummy pads that are not connected to the first conductive line and the second conductive line.

14. The chip-on-film package of claim 11, wherein the bonding pads of the first row are connected to the gate driver chip via the conductive path.

15. The chip-on-film package of claim 11, wherein the bonding pads of the second row are connected to the source driver chip via the conductive path.

16. A display device, comprising: Chip-on-film packaging with a base film; The display panel, the first portion of the top surface of the base film; as well as The driver printed circuit board, facing the second portion of the top surface of the substrate film, The on-film chip package includes: Basement membrane; Source driver chip and gate driver chip are mounted on the top surface of the substrate film and respectively arranged in different rows; A first conductive line on the top surface of the base film, a second conductive line on the bottom surface of the base film, and a conductive path connecting the first conductive line and the second conductive line to each other. The bonding pads in the first row are connected only to the source driver chip on the top surface of the substrate film and via the first conductive line, and the bonding pads in the first row are spaced apart from the source driver chip and the gate driver chip along the top surface of the substrate film; and The bonding pads in the second row are located on the top surface of the substrate film and are connected to the source driver chip and the gate driver chip via the second conductive line. These bonding pads are spaced apart from the source driver chip and the gate driver chip along the top surface of the substrate film. The first distance between the bonding pads in the first row and the source driver chip is less than the second distance between the bonding pads in the second row and the source driver chip.

17. The display device according to claim 16, wherein the substrate film is a flexible film.

18. The display device according to claim 17, The display panel described therein has a front surface comprising multiple pixels and a rear surface opposite to the front surface. The on-film chip package is bent toward the rear surface of the display panel and attached to the display panel, and The driver printed circuit board faces the rear surface of the display panel.

19. The display device according to claim 16, wherein, In the chip-on-film package, the bonding pads of the first row are connected to the source driver chip via the first conductive line, without passing through the conductive path.

20. The display device according to claim 16, wherein, In the chip-on-film package, the bonding pads of the second row are connected to the source driver chip or the gate driver chip via the conductive path.

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