Thin film chip on film package and display device including the same

Abstract

A chip-on-film (COF) package and a display device including the same are provided. The COF package includes a film substrate, a chip disposed in a chip region on the film substrate, external pins disposed on the same side of the chip region on the film substrate, the external pins being arranged in at least two rows and including input external pins and output external pins, and internal pins disposed on a first side and a second side of the chip and connected to the chip, the internal pins including input internal pins and output internal pins, wherein the output internal pins are connected to the output external pins to provide signals output from the chip to the output external pins, and the input internal pins are connected to the input external pins to provide signals from the input external pins to the chip, and wherein the at least two rows of external pins include a first row of external pins and a second row of external pins, the first row of external pins is interposed between the second row of external pins and the chip, and at least some of the external pins in the second row of external pins are connected to the internal pins on the second side of the chip in a looped manner.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 241,108, filed September 7, 2021, with the United States Patent and Trademark Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and more specifically, to a chip-on-film (COF) package and a display device including the chip-on-film package. Background Technology

[0004] Generally, in display devices, driver chips can be packaged using technologies such as chip-on-film (COF), tape-carrier package (TCP), and chip-on-glass (COG). Compared to TCP and COG technologies, COF offers finer pitch and better flexibility, making it superior in terms of dimensional stability, high circuit density, flame retardancy, and environmental friendliness.

[0005] COF packaging can be used to bond a printed circuit board (hereinafter also referred to as a control board) on which display control circuitry is disposed to the substrate of a display panel (e.g., an LCD display panel or an OLED display panel), or to bond a printed circuit board (hereinafter also referred to as a control board) on which backlight control circuitry is disposed to the substrate of a backlight board (e.g., a backlight board for an LCD display panel). Of course, COF packaging can also be used for bonding other similar circuit boards.

[0006] As the requirements for the size and thickness of display devices, as well as production efficiency, become increasingly stringent, COF packaging, which is typically placed on the edge or back of the display panel or backlight, also places higher demands on the size and thickness of COF packaging. Furthermore, if COF packaging can quickly achieve the bonding between circuit boards, it will be beneficial to improving the production efficiency of display devices. Summary of the Invention

[0007] According to a first aspect of this application, a thin-film flip-chip package is provided, comprising: a film substrate; a chip disposed in a chip region on the film substrate; external pins disposed on the same side of the chip region on the film substrate, the external pins being arranged in at least two rows and including input external pins and output external pins; and internal pins disposed on a first side and a second side of the chip and connected to the chip, wherein the first side of the chip is the side facing the external pins, and the internal pins include input internal pins and output internal pins; wherein the output internal pins are connected to the output external pins for providing a signal output by the chip to the output external pins, and the input internal pins are connected to the input external pins for providing a signal from the input external pins to the chip, wherein the at least two rows of external pins include a first row of external pins and a second row of external pins, the first row of external pins being located between the second row of external pins and the chip, and at least a portion of the pins in the second row of external pins having a loop-type connection between the traces and the second side internal pins of the chip.

[0008] According to a second aspect of this application, a display device is provided, comprising: a thin-film flip-chip package as described in the first aspect of this application; a display panel for displaying content to be displayed; a backlight panel having a backlight circuit thereon for providing backlight to the display panel; and a control circuit board having a control circuit thereon for providing a backlight control signal to a chip in the thin-film flip-chip package and / or obtaining a backlight-related signal from the chip, wherein an input pin in the thin-film flip-chip package obtains a backlight control signal from the control circuit, and an output pin provides a backlight drive signal to the backlight circuit and / or provides a backlight-related signal to the control circuit, the backlight drive signal being generated by the chip based on the backlight control signal.

[0009] According to a third aspect of this application, a display device is provided, comprising: a thin-film flip-chip package as described in the first aspect of this application; a display panel having a display circuit disposed thereon; and a control circuit board having a control circuit disposed thereon for providing a display control signal to the display circuit and providing a display drive control signal to a chip in the thin-film flip-chip package or obtaining a drive-related signal from the chip, wherein an input external pin in the thin-film flip-chip package obtains a drive control signal from the control circuit, and an output external pin provides a display drive signal to the display circuit or provides a drive-related signal to the control circuit, the display drive signal being generated by the chip based on the display drive control signal.

[0010] Referring to the COF package structure described in this application, it is possible to use a single conductive material layer to form two rows, or two conductive material layers to form three or four rows of input external pins and output external pins, as well as traces connecting them to internal pins. This increases the number of output signals of the COF package, allowing for the use of fewer COF packages and reducing the thickness of the COF package, thereby reducing costs and meeting size requirements. Furthermore, by setting some traces in a loop, wiring space can be fully utilized, ensuring that the spacing between traces or pins is not too small, thus improving the stability of signal transmission. In addition, when this COF package is bonded to the backlight panel or display panel and control circuit board in a display device, only one bonding process is required, thereby improving production efficiency. Attached Figure Description

[0011] The accompanying drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same / similar components or steps.

[0012] Figure 1A A schematic diagram of a COF package is shown.

[0013] Figure 1B A schematic diagram of a COF package is shown.

[0014] Figure 1C It shows Figure 1A A cross-sectional schematic diagram of a COF package (using a single conductor layer).

[0015] Figure 1D It shows Figure 1B A cross-sectional schematic diagram of a COF package (using two conductor layers).

[0016] Figure 2 References are shown Figure 1A-1D The described schematic structure is applied to a display device.

[0017] Figure 3 A schematic planar representation of an improved COF package is shown.

[0018] Figures 4A-4B A schematic diagram of the planar structure of an improved COF package according to an embodiment of this application is shown.

[0019] Figure 4C An example of a practical layout diagram of an improved COF package according to an embodiment of this application is shown.

[0020] Figures 5A-5BA simplified planar structure diagram of different types of COF packages based on external and internal pins is shown.

[0021] Figures 6A-6C An exemplary arrangement of the external pins is shown.

[0022] Figure 7 This shows when the external pin is pressed. Figure 6C Arrangement along Figure 6C A schematic diagram of the cross section obtained by connecting line A-A'.

[0023] Figures 8A-8B A simplified planar structure diagram of a COF package with three or four rows of external pins is shown according to an embodiment of this application.

[0024] Figure 9A The use of reference is shown Figure 4A-8B A schematic diagram of the planar structure of a COF-packaged display device.

[0025] Figure 9B It shows Figure 9A The left view obtained by the display device along the B-B' line.

[0026] Figure 10A The use of reference is shown Figure 4A-8B A plan view of another display device with COF packaging described.

[0027] Figure 10B It shows Figure 10A The left view of the display device along line C-C'.

[0028] Figure 11 The use of reference is shown Figure 4A-8B A cross-sectional schematic diagram of another display device with COF packaging described.

[0029] Figure 12 The use of reference is shown Figure 4A-8B A plan view of another display device with COF packaging described. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application more apparent, exemplary embodiments according to this application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0031] In this specification and accompanying drawings, steps and elements that are substantially the same or similar are indicated by the same or similar reference numerals, and repeated descriptions of these steps and elements are omitted. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance or order. Unless explicitly stated otherwise, singular expressions may refer to plural forms, and plural expressions may refer to singular forms.

[0032] Figure 1A A schematic diagram of a COF package is shown.

[0033] like Figure 1A As shown, the COF package 100 includes a film substrate 110, a chip 120, and a first set of external leads 130 and a second set of external leads 140 respectively arranged on both sides of the chip. In this disclosure, a lead (or lead bonding) can also refer to a conductive design for bonding with an external device. The external lead bonding (OLB) of the COF package refers to the leads on both sides of the COF package. For ease of description, only a small number of leads are schematically shown in the accompanying drawings of this application; however, those skilled in the art should understand that the number of leads can be set according to actual needs.

[0034] Chip 120 is disposed in a chip region on the film substrate 110, and the film substrate 110 includes inner pins (not shown), the inner pins including those disposed on a first side of the chip. Figure 1A The inner pin on the upper side and the second side (in the middle) Figure 1A The inner pins (on the lower side of the chip) can be connected to the conductive bumps (output bumps or input bumps) of the chip for signal transmission. Optionally, the chip 120 can be a display driver chip (driver IC) for receiving display driver control signals, processing them, and outputting display driver signals; or the chip 120 can be a backlight driver chip for receiving backlight control signals, processing them, and outputting backlight driver signals.

[0035] The first set of external pins 130 and the second set of external pins 140 are pins that can be connected to an external circuit board, corresponding to the internal pins on the first side and the second side of the chip, respectively. Depending on the direction of signal transmission, one of the first set of external pins 130 and the second set of external pins 140 can be an input pin, and the other can be an output pin.

[0036] exist Figure 1AThe second set of external pins 140 is shown as an input pin, and the first set of external pins 130 is an output pin. Thus, the input internal pins on the second side of the chip are used to provide signals from the second set of external pins 140 to the chip, and the output internal pins on the first side of the chip are used to provide signals output by the chip to the first set of external pins 130.

[0037] exist Figure 1A In the first group of external pins and the second group of external pins are both in a row, and the traces between the external pins and the internal pins are all straight-through, and these traces are formed by a single conductor layer (e.g., copper).

[0038] In some other embodiments, the first and second sets of external pins can each be designed as two rows to provide more signal paths. For example... Figure 1B The diagram shows a COF package with two rows of external pins in the first group. Of course, the second group of external pins can also be arranged in two rows. This requires a smaller trace spacing to connect the external and internal pins. Considering the large number of external pins, the trace spacing must be minimized as much as possible, but it cannot be too small. To ensure a suitable trace spacing, two conductive layers (conductive material layers) arranged on two opposite surfaces (top and bottom) of the film substrate are needed to form the traces between each row of external pins and their corresponding internal pins.

[0039] Figure 1C It shows Figure 1A A cross-sectional schematic diagram of a COF package (using a single conductor layer) is shown. Figure 1D It shows Figure 1B A cross-sectional schematic diagram of a COF package (using two conductor layers).

[0040] exist Figure 1C In the single row, each external pin in the first group and the second group of external pins, as well as the traces between them and the internal pins, are formed by a single conductive material (copper) layer.

[0041] exist Figure 1D In the middle, the first group of external pins in the double row and the second group of external pins in the double row are arranged in the area not covered by the solder mask layer. Two conductive material layers are arranged on two opposite surfaces of the film substrate and are used to form the traces between all external pins and their corresponding internal pins. Figure 1D Although the example shows two sets of external pins in double rows, it is also possible for one set of external pins (e.g., input external pins) to be in a single row.

[0042] Figure 2 References are shown Figure 1A-1D The described schematic structure is applied to a display device.

[0043] Figure 2The example described uses COF packaging for bonding with a backlight panel (in this document, bonding with the substrate of the backlight panel). However, it should be understood that COF packaging can also be used for bonding with LED display panels or LCD display panels (in this document, bonding with the substrate of the display panel) or with other circuit boards, etc.

[0044] like Figure 2 As shown, the COF package is bonded to the bonding area at the edge of the backlight panel via a first set of external pins, and to the bonding area of ​​the control board via a second set of external pins. Figure 2 Only one COF package is shown schematically, but it should be understood that there may be multiple COF packages edge-joined to the backlight panel, depending on the number of signals required to be supplied to the backlight panel in the actual application.

[0045] exist Figure 2 In the process, the control circuit on the control circuit board provides a backlight control signal to the inner pins on the second side of the chip (e.g., the driver chip) via the trace between the second set of external pins connected to the control circuit board and the inner pins on the second side of the chip. After the backlight control signal is processed by the chip, a backlight drive signal is generated. The backlight drive signal is provided to the backlight panel via the trace between the inner pins on the first side of the chip and the first set of external pins, and via the connected first set of external pins, so as to drive the backlight panel to emit light.

[0046] For reference Figure 1A-1D The example COF package described, and the reference Figure 2 The description includes example display devices in this COF package. In many cases, the number of output pins is often large, and it may be desirable to use output pins (such as...) for output signals. Figure 2 The first group of external pins shown is arranged in two rows. In this case, to ensure that the trace spacing is not too narrow, which could cause short circuits or introduce noise, a reference pin is required. Figure 1D The structure shown is based on two layers of conductor material, which increases the thickness of COF and requires higher manufacturing costs. In addition, when COF packaging is applied to display devices, it requires two bonding processes (also known as pressing, pressing, etc.) because COF packaging needs to be bonded separately in the bonding area of, for example, the backlight panel and the control circuit board. This makes the production process cumbersome and limits production efficiency.

[0047] exist Figure 3 Another COF packaging structure was proposed.

[0048] exist Figure 3 In this context, similar components or features may have the same characteristics as... Figure 1A The same reference numerals are used, for example, chip 120, first set of external pins 130, second set of external pins 140, etc. The following refers to... Figure 3 COF packaging relative to Figure 1A-1D The differences between COF packaging and COF packaging will be introduced.

[0049] like Figure 3 As shown, the first group of external pins 130 and the second group of external pins 140 are both located on the same side of the chip area. The first group of external pins 130 serves as an output external pin, and the second group of external pins 140 serves as an input external pin.

[0050] Similarly, the input internal pin (not shown) connected to the conductive bump of chip 120 is connected to the second set of external pins 140 by a trace, for inputting signals to be processed (e.g., backlight control signals or display drive control signals) to the chip via the second set of external pins 140. The output internal pin (not shown) connected to the conductive bump of chip 120 is connected to the first set of external pins 130 by a trace, for providing signals processed by the chip (e.g., display drive signals and backlight drive signals) from the first set of external pins 130.

[0051] Optionally, when Figure 3 When the COF package shown is used to bond with a backlight board and a control circuit board, since the input and output pins are located on the same side of the chip area, it can only be bonded to one circuit board. In this case, the backlight control signal that the control circuit on the control circuit board needs to transmit to the chip on the COF package can be first transmitted to the backlight board, and then transmitted to the corresponding bonding pad in the bonding area of ​​the backlight board through the traces arranged on the backlight board. In this way, when the COF package is bonded to the bonding area of ​​the backlight board, the backlight control signal to be provided to the chip (i.e., the backlight driver chip) can be obtained at the input pin of the COF package as the input signal of the COF package. After being processed by the chip, the backlight drive signal is provided from the output pin to the backlight circuit of the backlight board through the corresponding bonding pad in the bonding area of ​​the backlight board.

[0052] In other words, Figure 3 The COF package shown requires only one bonding process when bonded to the backlight (or display panel) and control circuit board (no further bonding with the control circuit board is needed because the control signal has already been transmitted to the corresponding bonding pad in the bonding area of ​​the backlight). Furthermore, a single conductive material layer can be used to form the traces connecting the input external pins and output external pins to the corresponding internal pins, thereby reducing the thickness of the COF package, lowering costs, and improving production efficiency.

[0053] For reference Figure 3The described COF package has input and output pins arranged on the edge of the film substrate in a row. Therefore, when the COF package is arranged around the edge of the display panel or backlight panel and the edge size of the display panel or backlight panel is small, it is necessary to compress the spacing between the input and output pins and the spacing between the traces connecting the external pins and the corresponding internal pins. This may result in the spacing between traces or the spacing between pins being too small, which may cause interference between signals or even short circuits.

[0054] Therefore, according to a first aspect of this disclosure, an improved COF package structure is provided, which can use a single conductive material layer or two conductive material layers to form a greater number of external pins and a greater number of traces connecting the external pins to the corresponding internal pins, thereby reducing the thickness of the COF package, reducing the number of COF packages, reducing costs and improving production efficiency. Furthermore, by setting some traces in a loop, the wiring space can be fully utilized, ensuring that the spacing between traces or between pins is not too small, thereby improving the stability of signal transmission.

[0055] The term "loop" as used in this application may also be referred to as cyclic, closed-loop, loop routing, or loop connection or similar expressions, indicating that the routing between the inner and outer pins from the second side of the chip (the first side of the chip is the side of the chip facing the outer pin area) wraps around the chip area and a portion of the outer pin area and has a curved shape.

[0056] The term "pull-through routing or pull-through connection or similar expression" used in this application refers to a connection from the first side of the chip (the first side and the second side are determined according to...) Figure 1A In the COF package definition, the traces between the inner and outer pins are included between the chip area and the outer pin area and are composed of straight lines.

[0057] Figures 4A-4B A schematic diagram of the planar structure of an improved COF package according to an embodiment of this application is shown.

[0058] like Figures 4A-4B As shown, the COF package 400 includes a film substrate 110, a chip 120, external pins (including a first group of external pins 130 and a second group of external pins 140), and internal pins located on both sides of the chip 120.

[0059] Chip 120 is disposed in the chip region on the film substrate. Figure 4A In this example, only one chip is shown, but in many cases, chip 120 can include multiple chips in a chipset. For example... Figure 4BAs shown, chip 120 includes chip 120-1 and chip 120-2. Each chip acquires the input signal, processes the signal, and then outputs the processed signal.

[0060] External pins are arranged on the same side of the chip region on the film substrate 110, and the external pins are arranged in at least two rows and include input external pins and output external pins.

[0061] The internal pins are arranged on the first and second sides of the chip 120 and connected to the chip 120 (e.g., conductive bumps of the chip). The first side of the chip faces the external pins. The internal pins include input internal pins and output internal pins.

[0062] The internal output pin is connected to the external output pin (first group of external pins 130) to provide the signal output by the chip 120 to the external output pin, and the internal input pin is connected to the external input pin (second group of external pins 140) to provide the signal from the external input pin to the chip 120.

[0063] It should be understood that, based on the quantitative relationship between the chip's input and output signals and the direction of signal transmission, Figure 4A The first set of external pins 130 can also be used as input external pins, and the second set of external pins 140 can also be used as output external pins.

[0064] Figures 4A-4B The COF package shown includes a first row of external pins and a second row of external pins. The first row of external pins is located between the second row of external pins and the chip 120. At least some of the pins in the second row of external pins are connected to the inner pins on the second side of the chip in a loop-like manner. For example, the traces between the inner pins on the first side of the chip 120 and the first row of external pins are connected in a straight-pull manner; and the traces between the inner pins on the second side of the chip 120 and the second row of external pins are connected in a loop-like manner.

[0065] The area on the film substrate 110 where external leads are arranged is called the external lead area, wherein the external lead area is at a predetermined distance from the edge of the film substrate (in Figure 4A (Indicated by "D"), the area defined by the predetermined distance is used to arrange the traces of the loop connection method. For example, the predetermined distance can be 100µm. Figures 4A-4B As shown, the area between the edge of the film substrate 110 and the second row of external pins can provide space for arranging loop-shaped traces.

[0066] Figure 4C An example of a practical layout diagram of an improved COF package according to an embodiment of this application is shown.

[0067] like Figure 4C As shown, there are two rows of external pins in the external pin area. The external pins corresponding to the white dashed box area and the external pins corresponding to the white solid box area can be used as input external pins and output external pins, respectively.

[0068] exist Figures 4A-4C In this example, the external pins include two rows of arranged external pins, and the first group of external pins 130 and the second group of external pins 140 are used as output external pins and input external pins, respectively. However, those skilled in the art should understand that different configurations of input external pins and output external pins can be made according to the actual signal transmission.

[0069] Optionally, each row of external pins may include different types of external pins, such as both input and output external pins, or only one type of external pin. The type of each external pin in each row can be determined according to the specific arrangement of the input and output conductive bumps of the chip. For example, as Figure 4C As shown, the inner pins on the second side of the chip include both input inner pins and output inner pins, and the inner pins on the first side of the chip include output inner pins. Therefore, the first row of outer pins connected to the output inner pins on the first side of the chip via a pull-through connection is correspondingly an output outer pin, the second row of outer pins connected to the output inner pins on the second side of the chip via a loop connection is correspondingly an output outer pin, and the second row of outer pins connected to the input inner pins on the second side of the chip via a loop connection is correspondingly an input outer pin.

[0070] For example, in one example scenario, the output internal pins can be arranged on both sides of the chip, and / or, the input internal pins can also be arranged on both sides of the chip, for ease of description. Figure 5A Only a small number of traces between external pins and their corresponding internal pins are shown, such as Figure 5A As shown, the traces between the output internal pins arranged on the first side of the chip and their corresponding output external pins are connected in a pull-through manner, and the traces between the output internal pins arranged on the second side of the chip and their corresponding output external pins are connected in a loop manner; and / or, the traces between the input internal pins arranged on the first side of the chip and their corresponding input external pins are connected in a pull-through manner, and the traces between the input internal pins arranged on the second side of the chip and their corresponding input external pins are connected in a loop manner.

[0071] In one example scenario, all output pins are arranged on the first side of the chip or all on the second side of the chip, and / or, all input pins are arranged on the first side of the chip or all on the second side of the chip. For example... Figure 5BAs shown, when all output internal pins are arranged on the first side of the chip, the traces between the output internal pins and their corresponding output external pins are connected in a pull-through manner, and / or, when all input internal pins are arranged on the second side of the chip, the traces between the input internal pins and their corresponding input external pins are connected in a loop manner; similarly, when all output internal pins are arranged on the second side of the chip, the traces between the output internal pins and their corresponding output external pins are connected in a loop manner, and / or, when all input internal pins are arranged on the first side of the chip, the traces between the input internal pins and their corresponding input external pins are connected in a pull-through manner.

[0072] Furthermore, the two rows of external leads in a COF package can be aligned or staggered. The number of external leads in each row can be unequal, and the spacing between adjacent external leads can also be unequal.

[0073] Figures 6A-6C Several exemplary arrangements of the external pins are shown.

[0074] For example, in Figure 6A In the middle, and the previous text Figures 4A-4C as well as Figures 5A-5B The diagrams both illustrate the aligned arrangement of two rows of external pins. Of course, external pins can also be arranged in an interleaved manner, such as... Figure 6B As shown.

[0075] Additionally, when the number of external pins in each row is not equal, such as Figure 6C As shown, the second row of external pins can have more pins than the first row of external pins. In this case, the routing between a portion of the external pins in the second row and the internal pins on the second side of the chip can use a loop connection method. Figure 6C The diagram illustrates a loop-like trace (with an arc), and the trace between another portion of the second row of external pins and the internal pins on the first side of the chip is a straight-pull connection.

[0076] The above explanation uses a two-row external pin arrangement as an example. However, it should be understood that the arrangement of three or four rows of external pins, the routing between pins, and the determination of the external pin type are all similar. The only difference is that an additional conductor layer (conductive material layer) is needed to form one or two additional sets of traces, as will be discussed later. Figures 8A-8B Described.

[0077] For example, if the external pins are arranged in only two rows, only a single conductive material layer is needed to form all the traces between the input external pins and the input internal pins, and between the output internal pins and the output external pins. For example, in Figures 4A-4CIn this configuration, the first set of traces S1 and the second set of traces S2 can be formed using only a single conductive material layer. The first set of external pins 130 and the second set of external pins 140 can also be formed using this single conductive material layer.

[0078] Figure 7 This shows the effect when the external pins are arranged in two rows. Figure 6C A schematic diagram of the cross section taken by the line connecting A-A'.

[0079] like Figure 7 As shown, external leads (including input and output external leads) and traces are formed in a conductive material layer on the film substrate, and a solder mask layer covers the portion of the traces. The input external leads are electrically connected to traces using a loop connection method, and the output external leads are electrically connected to traces using a pull-through connection method. The conductive material can be copper. There is a spacing between the input and output external leads in the horizontal direction shown. Of course, depending on the type of internal leads on both sides of the chip... Figure 7 The types of input and output external pins can be adjusted.

[0080] Furthermore, if the external pins are arranged in three or four rows, all traces between the input external pins and the input internal pins, and between the output internal pins and the output external pins, can be formed using two isolated conductive material layers on two opposite surfaces of the film substrate. The specific structure is as follows: Figures 8A-8B As shown.

[0081] Figures 8A-8B A simplified planar structure diagram of a COF package with three or four rows of external pins is shown according to an embodiment of this application.

[0082] like Figure 8A As shown, if the external pins are arranged in three rows, the first conductive material layer (conductive layer L1) on the first surface of the film substrate (the surface where the chip is located) can be used to form all the traces between the first to third rows of external pins and their corresponding internal pins. Similarly, the second conductive material layer (conductive layer L2) on the second surface of the film substrate (opposite to the surface where the chip is located) can be used to form all the traces between the third row of external pins and their corresponding internal pins. As mentioned earlier, the type (input or output) of each external and internal pin is designed according to the specific circumstances.

[0083] exist Figure 8A In the middle, and in conjunction with the preceding text Figure 1D The arrangement of the two conductive material layers shown enables the connection between some external pins and corresponding internal pins through traces formed on the conductive material layers and passing through the film substrate 110.

[0084] The routing design on conductive layer L1 is referenced in the previous text. Figures 4A-4C As described above, conductive layer L2 is used to form the traces between the outer pins of the third row and their corresponding inner pins. Figure 8A In the example, the routing between the third row of external pins and the internal pins on the first side of the chip uses a straight-pull connection (this routing needs to pass through the film substrate twice). It should be understood that, depending on the specific design of the type of internal pins, the third row of external pins can be connected to the internal pins on the second side of the chip, and the routing between them can use a loop connection or a straight-pull connection (this routing needs to pass through the film substrate twice).

[0085] In addition, Figure 8A In this configuration, the third row of external pins is positioned close to the first row of external pins. However, it should be understood that the third row of external pins can be positioned between the first and second rows of external pins because the traces associated with the third row of external pins are formed on another conductive material layer. The traces only pass through the film substrate 110 in the region of the third row of external pins and the corresponding inner pin region to achieve the connection between the third row of external pins and the corresponding inner pins. Therefore, it will not affect the traces associated with the first and second rows of external pins.

[0086] Similarly, such as Figure 8B As shown, if the external pins are arranged in four rows, the first to fourth rows of external pins, as well as all traces between the first and second rows of external pins and their corresponding internal pins, can be formed on the first conductive material layer (conductive layer L1) on the first surface of the film substrate (the surface where the chip is located). Furthermore, all traces between the third and fourth rows of external pins and their corresponding internal pins can be formed on the second conductive material layer (conductive layer L2) on the second surface of the film substrate (opposite to the surface where the chip is located). As mentioned earlier, the type (input or output) of each external and internal pin is designed according to the actual situation.

[0087] The routing design on conductive layer L1 is referenced in the previous text. Figures 4A-4C As described above, conductive layer L2 is used to form the traces between the outer pins of the third and fourth rows and their corresponding inner pins. Figure 8B To simplify the description, only two examples of traces are shown for each row. Although in... Figure 8B Taking the example of a straight-pull connection between the third row of external pins and the first side of the chip's internal pins, and a loop connection between the fourth row of external pins and the second side of the chip's internal pins, it should be understood that the connection method between the external pins and the internal pins can also be adjusted depending on the specific design of the internal pins.

[0088] In addition, Figure 8BIn this configuration, the third and fourth rows of external pins are positioned close to the first row. However, it should be understood that the third and fourth rows of external pins can be positioned between the first and second rows of external pins, or the fourth row of external pins can be positioned between the second and first rows of external pins, and the first row of external pins can be positioned between the fourth and third rows of external pins. Because the traces between the third and fourth rows of external pins and their corresponding internal pins are formed on another conductive material layer, the traces only pass through the film substrate 110 in the regions of the third and fourth rows of external pins and their corresponding internal pins to achieve the connection between the third and fourth rows of external pins and their corresponding internal pins. Therefore, it will not affect the traces related to the first and second rows of external pins.

[0089] refer to Figure 4A-8B The described COF package structure allows for the use of a single conductive material layer to form two rows, or two conductive material layers to form three or four rows, of traces between the external pins and their corresponding internal pins. This increases the number of output signals from the COF package, enabling the use of fewer COF packages and reducing the thickness of the COF package. Consequently, costs are reduced while meeting size requirements. Furthermore, by setting some traces in a loop configuration, wiring space is fully utilized, ensuring that the spacing between traces or pins is not too small, thus improving signal transmission stability. In addition, when this COF package is bonded to the backlight panel or display panel and control circuit board in a display device, only a single bonding process is required, thereby improving production efficiency.

[0090] According to another aspect of this application, COF packaging can be used in display devices to enable signal transmission between a control circuit board and a backlight panel or display panel.

[0091] The following will be a reference for use. Figure 4A-8B The COF packaged display device is described.

[0092] The display device can be a liquid crystal display (LCD) or an LED (including OLED) display. In the case of an LCD display, the backlight panel includes backlight circuitry that needs to be driven to emit light using drive signals, such as a light source like an LED, i.e., an LED backlight panel. Therefore, a backlight drive signal needs to be provided to the backlight panel, and the backlight panel may also need to receive signals such as timing signals and clock signals. Furthermore, the display circuitry of the display panel (LCD or LED display panel) (e.g., including multiple pixel circuits) also requires various signals such as gate drive signals or data signals for driving and control. The signals provided to the backlight panel and / or display panel can be generated by basic control circuitry and obtained after processing the signals provided by the control circuitry by a chip. A printed circuit board on which the control circuitry is arranged serves as the control circuit board.

[0093] Figures 9A-9B For reference Figure 4A-8B A schematic diagram of a COF-packaged display device.

[0094] Figure 9A The use of reference is shown Figure 4A-8B A schematic diagram of the planar structure of a COF-packaged display device.

[0095] like Figure 9A As shown, the display device is an LCD display device as an example for explanation. The display device 900 includes: a COF package 910, a display panel 920, a backlight panel 930, and a control circuit board 940.

[0096] The COF packaged 910 can have the features described in the previous reference. Figure 4A-8B Describes various structures of COF packaging.

[0097] Display panel 920 is used to display the content to be displayed.

[0098] The backlight panel 930 is provided with a backlight circuit for providing backlight to the display panel.

[0099] For example, the backlight circuit (e.g., a multi-row LED light-emitting circuit) on the backlight panel 930, which includes a backlight source, can make the backlight source emit light based on a backlight drive signal obtained from the COF package. Figures 9A-9B The image shows a simple example of an LED backlight panel, but an actual LED backlight panel is a complete backlight module, including polarizers and diffusers, etc.

[0100] The control circuit board 940 is provided with a control circuit for providing backlight control signals to the chip in the COF package and / or obtaining backlight-related signals from the chip.

[0101] For example, the control circuitry on the control circuit board can generate various control signals related to the backlight driving and display processes, and can also obtain signals from other circuits. For instance, for the backlight driving process, the control circuitry can provide control signals such as timing signals and clock signals to the backlight board, and can provide backlight control signals to driver chips (packaged in a COF package, one or more). Furthermore, it can obtain backlight-related signals (e.g., detection signals obtained by monitoring the backlight driving process) from the driver chips. Thus, the input pins in the COF package obtain backlight control signals from the control circuitry, and the output pins provide backlight driving signals to the backlight circuitry on the backlight board and / or provide backlight-related signals to the control circuitry on the control circuit board.

[0102] Alternatively, since at least two rows of input and output pins in the COF package are located on the same side of the chip area, only one bonding is required, thus enabling one of the control board and the backlight board to be bonded to the COF package.

[0103] When the control circuit board is not bonded to the COF package, such as Figure 9A As shown, the backlight control signal that the control circuit on the control board needs to transmit to the driver chip on the COF package can be carried out by the backlight board, and the corresponding transmission path is arranged on the backlight board.

[0104] A bonding area is provided on the backlight panel 930, where the input and output pins of the COF package 910 are attached (bonded). Backlight control signals from the control circuit board are transmitted to the bonding area of ​​the backlight panel, providing the backlight control signals to the input pins of the COF package via the bonding area, and providing backlight drive signals generated by the chip to the backlight circuitry on the backlight panel via the output pins of the COF package. For example, the output pins of the COF package are connected to drive lines on the backlight panel. One drive line can connect to a column of LEDs; for instance, if a COF package includes 400 output pins, when connected to 400 drive lines on the backlight panel, it can provide drive current to drive 400 columns of LEDs.

[0105] Optionally, such as Figure 9A As shown, the control circuit board can transmit the signals that the control circuit on the control circuit board needs to directly transmit to the backlight board, along with the backlight control signals that need to be transmitted to the driver chip on the COF package, to the backlight board via a connecting circuit board. At least a portion of the signals from the control circuit are then transmitted through traces on the backlight board to the corresponding bonding pads in the bonding area of ​​the backlight board. In this way, when the COF package is bonded to the bonding area of ​​the backlight board, the COF package can obtain the backlight control signals to be provided to the driver chip at the input external pin of the COF package. As the input signal of the COF package, after being processed by the driver chip on the COF package, the backlight drive signal is provided to the backlight circuit of the backlight board from the output external pin through the corresponding bonding pads in the bonding area of ​​the backlight board.

[0106] Optionally, the connecting circuit board can be a flexible circuit board, and specific implementation methods can include, for example, PCB / FPC / BT / ABF, etc.

[0107] In this case, the COF packaged film substrate 910 may not have external pins that are electrically connected to the control circuit board for input / output purposes. The side of the COF package closest to the control circuit board can be considered as floating, and the film substrate can be fixed in other ways (e.g., by adhesive or by other components) to prevent deformation.

[0108] Furthermore, since the number of backlight drive signals used to drive the backlight circuitry on the backlight board is usually quite large, multiple driver chips are needed to generate these backlight drive signals. Therefore, multiple COF packages can be used. Various signals can be transmitted between adjacent COF packages. For example, connection traces can be arranged between bonding pads in adjacent bonding areas of the backlight board. The control circuit on the control board provides backlight control signals to a certain COF package as input signals via connection circuit boards such as FPCs, corresponding connection traces on the backlight board, and corresponding bonding pads in the bonding areas of the backlight board to which the COF package is bonded. The COF package can provide backlight control signals to the input pins of an adjacent COF package via some output pins and corresponding connection traces on the backlight board. Optionally, the COF package may not process certain input signals (e.g., backlight control signals) input from the external input pins and may pass these input signals to an adjacent COF package; or, a portion of the input signals of the driver chip of the next COF package may be a portion of the output signals processed by the driver chip of the previous COF package. This application does not limit the types of signals passed between COF packages.

[0109] Figure 9B It shows Figure 9A The left view obtained by the display device along the B-B' line.

[0110] like Figure 9B As shown, the COF package's film substrate is located at the bottom, with the control circuit board and backlight panel laminated on top of it. The side of the COF package closest to the control circuit board can be considered floating, or the film substrate can be fixed in other ways (e.g., with adhesive or other mechanisms) to prevent deformation. The side of the COF package closest to the backlight panel is bonded to the backlight panel at the bonding area. Although in Figure 9B In the left view obtained along line B-B', the chip is located between the control board and the backlight. However, it should be understood that the chip is not directly connected to the control board or the flexible circuit board (FPC). The control board is connected to the backlight via the FPC to transmit the control signals to be provided to the chip.

[0111] pass Figures 9A-9B The display device shown can use fewer COF packages because the external pins of the included COF packages can be arranged in at least two rows, increasing the number of pins and reducing the size. This reduces the size and cost of the display device. In addition, when transmitting signals between the COF packages and the backlight and control circuit boards, only one bonding process can be used, thus improving production efficiency.

[0112] Figures 10A-10B The use of reference is shown Figure 4A-8BA schematic diagram of another display device with COF packaging is described, wherein, Figure 10A A plan view of this other display device is shown, and Figure 10B The left view taken along line C-C' is shown.

[0113] For the sake of brevity, Figures 10A-10B The display device 1000 and Figure 9A The components similar to the display device 900 in the text will not be described again; only their differences will be explained.

[0114] like Figures 10A-10B As shown, with Figure 9A The display devices in them are different. Figures 10A-10B The COF package is bonded to the control circuit board.

[0115] A bonding area is provided on the control circuit board 1040, and the input and output external pins of the COF package 1010 are attached (bonded) to the bonding area. The control circuit on the control circuit board provides backlight control signals to the input external pins of the COF package via the bonding area, and provides backlight drive signals from the output external pins of the COF package 1010 to the backlight circuit on the backlight board via the same bonding area. Here, the backlight drive signals are generated by the driver chip in the COF package 1010 based on the backlight control signals.

[0116] For example, the bonding pads in the bonding area on the control circuit board obtain the backlight drive signal generated by the driver chip based on the backlight control signal from the output external pin of the COF package 1010. Then, the backlight drive signal is transmitted to the backlight circuit on the backlight board via the bonding pads in the bonding area on the control circuit board, the traces on the control circuit board, and the connection circuit board between the control circuit board and the backlight board.

[0117] In other words, the backlight drive signals (and other control signals such as timing signals and clock signals) required by the backlight panel are transmitted from the control circuit board through the connecting circuit board.

[0118] In addition, as a response to Figures 10A-10B A replacement for the display device in the middle, Figure 11 A cross-sectional schematic diagram of another display device is shown.

[0119] For the sake of brevity, Figure 11 Display device and Figure 9A and 10A Components similar to those in the display device in -10B will not be described again; only their differences will be explained.

[0120] like Figure 11 As shown, the COF package is bonded to the control circuit board and... Figures 10A-10B Unlike other backlights, the control circuit board 1140 is vertically disposed below the backlight panel 1130. The lower surface of the control circuit board 1140 (the surface of the COF package is set as the upper surface of the control circuit board) is in contact with the lower surface of the backlight panel 1130 (the lower surface of the substrate). A bonding area is provided on the upper surface of the control circuit board 1140, and the input external pins and output external pins of the COF package 1110 are attached (bonded) to the bonding area.

[0121] The control circuit on the control circuit board 1140 provides a backlight control signal to the input pin of the COF package via the bonding area, and provides a backlight drive signal generated by the chip from the output pin of the COF package based on the backlight control signal to the backlight circuit on the backlight board 1130 via the bonding area.

[0122] For example, the bonding pads in the bonding area on the control circuit board obtain the backlight drive signal from the output external pin of the COF package 1010. The backlight drive signal is transmitted to the backlight circuit on the backlight board via the bonding pads in the bonding area on the control circuit, the traces on the control circuit board, and the connection circuit board between the control circuit board and the backlight board.

[0123] In other words, the backlight drive signals (and other control signals such as timing signals and clock signals) required by the backlight panel are transmitted from the control circuit board through the connecting circuit board.

[0124] Similarly, through Figures 10A-10B The display device shown in Figure 11, and Figure 9A Similar to the display devices in the text, the size of the display device can be reduced, and production efficiency can be improved.

[0125] The above combination Figure 9A-11 The description addresses the case where the COF package outputs a backlight drive signal from its external pins to drive the backlight circuitry on the backlight panel of a display device. Furthermore, the COF package can also be used to output a display drive signal to drive the display circuitry on the display panel of a display device. In this case, the connection method between the COF package and the display panel and control circuit board is as described in the reference. Figure 9A-11 The connection method described in the text is similar to that of the backlight panel and control circuit board.

[0126] For example, Figure 12 For reference Figure 4A-8B A schematic diagram of another display device with a COF package.

[0127] like Figure 12 As shown, the display device 1200 includes: a COF package 1210, a display panel 1220, and a control circuit board 1230.

[0128] The COF packaged 1210 can have the features described in the previous reference. Figure 4A-8B The various structures of the COF package described herein include a display panel 1220 with a display circuit for displaying the content to be displayed. Optionally, the display circuit needs to acquire display-related signals such as gate drive signals and data signals.

[0129] The control circuit board 1230 is provided with a control circuit for providing display control signals (e.g., data signals, clock signals, etc.) to the display circuit, and providing display drive control signals (e.g., gate drive signals, etc.) to the chip in the COF package or obtaining drive-related signals from the chip.

[0130] For example, the control circuitry on the control circuit board can generate various control signals related to the display process and display driving process, and can also obtain signals from other circuits. For instance, the control circuitry can provide display driving control signals to driver chips (packaged in a COF package, one or more), and optionally obtain display driving-related signals (e.g., detection signals obtained from monitoring the display driving process) from the driver chips. Thus, the input pins in the COF package can obtain display driving control signals from the control circuitry, and the output pins can provide display driving signals to the display circuitry on the display panel and / or provide display driving-related signals to the control circuitry.

[0131] Alternatively, since the input and output pins arranged in at least two rows in the COF package are located on the same side of the chip area, only one connection with a circuit board can be made, thus allowing one of the control circuit board and the display panel to be connected to the COF package.

[0132] like Figure 12 As shown, when the control circuit board is not connected to the COF package, the display panel can be used to forward the display drive control signals that the control circuit on the control circuit board needs to pass to the driver chip on the COF package. The display panel has corresponding transmission paths.

[0133] A bonding area is provided on the display panel 1220. The input external pin and output external pin of the COF package 1210 are attached (pressed) to the bonding area. The display drive control signal from the control circuit board is transmitted to the bonding area of ​​the display panel. The display drive control signal is provided to the input external pin of the COF package through the bonding area, and the display drive signal generated by the driver chip is provided to the display circuit on the display panel through the output external pin of the COF package.

[0134] Optionally, such as Figure 12As shown, the control circuit board can transmit the display drive control signal to the driver chip on the COF package to the display panel via the connecting circuit board, and then transmit it to the corresponding bonding pad in the bonding area of ​​the display panel through the traces (not shown) on the display panel. In this way, when the COF package is bonded to the bonding area of ​​the display panel, the COF package can obtain the display drive control signal to be provided to the driver chip at the input external pin of the COF package. As the input signal of the driver chip on the COF package, after being processed by the driver chip on the COF package, the display drive signal generated by the chip is provided to the display circuit of the display panel from the output external pin through the corresponding bonding pad in the bonding area of ​​the display panel.

[0135] Optionally, the connecting circuit board can be a flexible circuit board, and the specific implementation method can be, for example, PCB / FPC / BT / ABF, etc.

[0136] In this case, the COF packaged film substrate 1210 may not have external pins that are electrically connected to the control circuit board for input / output purposes. The side of the COF package closest to the control circuit board can be considered as floating, and the film substrate can be fixed in other ways (e.g., by adhesive or by other mechanisms) to prevent deformation.

[0137] Furthermore, since the number of display drive signals used to drive the display circuitry on the display panel is usually quite large, multiple driver chips are needed to generate these display drive signals. Therefore, multiple COF packages can be used. For example, various signals can be transmitted between adjacent COF packages. For instance, connection traces can be arranged between bonding pads in adjacent bonding areas of the display panel. The control circuit on the control board provides signals to a certain COF package as input signals via a connection board such as an FPC, corresponding connection traces on the display panel, and corresponding bonding pads in the bonding area of ​​the display panel to which the COF package is bonded. Optionally, a certain COF package may not process certain input signals (e.g., display control signals) input from external input pins and transmit these input signals to an adjacent COF package; or, part of the input signal of the driver chip of the next COF package may be part of the output signal processed by the driver chip of the previous COF package. This application does not limit the types of signals transmitted between COF packages. For example, when a COF package includes a gate drive circuit (GOA), the previous level COF package can provide a start signal and / or a clock signal shared by all GOA circuits in the next level COF package.

[0138] Similarly, alternatives such as Figure 12 The COF package described herein is bonded to the bonding area of ​​the display panel. The COF package can also be bonded to the control circuit board, as described in the previous reference. Figures 10A-10B as well as Figure 11 The layout described is similar, except that the backlight is replaced with a display panel.

[0139] For example, in the first example where the COF package can also control the bonding of the circuit board, the control circuit board is provided with a bonding area, the input external pins and output external pins of the COF package are attached (bonded) to the bonding area, the control circuit provides the display drive control signal to the input external pins of the COF package via the bonding area, and provides the display drive signal generated by the chip based on the display drive control signal from the output external pins of the COF package to the display circuit on the display panel via the bonding area.

[0140] For example, in a second example where the COF package can also control the bonding of the circuit board, the control circuit board is vertically positioned below the display panel, with its lower surface in contact with the lower surface of the display panel. A bonding area is provided on the upper surface of the control circuit board, and the input and output pins of the COF package are attached (bonded) to the bonding area. The control circuit provides the display drive control signal to the input pin of the COF package via the bonding area, and provides the display drive signal generated by the chip based on the display drive control signal from the output pin of the COF package to the display circuit on the display panel via the bonding area.

[0141] Similarly, through Figure 12 The display device shown can use fewer COF packages because the external pins of the included COF package can be arranged in at least two rows, increasing the number of pins and reducing the size. This reduces the size and cost of the display device. In addition, when transmitting signals between the COF package and the display panel and control circuit board, only one bonding process can be used, thus improving production efficiency.

[0142] Although the above references Figure 9A-12 The described display device describes COF packaging and their bonding methods for the backlight panel and the display panel respectively. However, it should be understood that in an LCD display device, since both a backlight panel and a display panel are included, COF packaging according to the embodiments of this application can be used for both the backlight panel and the display panel.

[0143] Although this application has been disclosed above with reference to embodiments, it is not intended to limit this application. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of this application. Therefore, the scope of protection of this application shall be determined by the appended claims.

Claims

1. A thin-film flip-chip package, comprising: membrane substrate; Chips, arranged in the chip region on the film substrate; External pins are arranged on the same side of the chip region on the film substrate, and the external pins are arranged in at least two rows and include input external pins and output external pins; Internal pins are arranged on the first and second sides of the chip and connected to the chip. The first side of the chip faces the external pins. The internal pins include input internal pins and output internal pins. The internal output pin is connected to the external output pin and is used to provide the signal output by the chip to the external output pin. Similarly, the internal input pin is connected to the external input pin and is used to provide the signal from the external input pin to the chip. The at least two rows of external pins include a first row of external pins and a second row of external pins. The first row of external pins is located between the second row of external pins and the chip. The routing between at least a portion of the external pins in the second row of external pins and the internal pins on the second side of the chip adopts a loop connection method.

2. The thin-film flip-chip packaging according to claim 1, wherein, The at least two rows of external leads are arranged in the external lead region of the film substrate. The outer pin area is at a predetermined distance from the edge of the film substrate, and the area defined by the predetermined distance is used to arrange the traces of the loop connection method.

3. The thin-film flip-chip packaging according to claim 1, wherein, The wiring between the inner pins on the first side of the chip and the first row of outer pins in the two rows adopts a straight-pull connection method; and The routing between the inner pins on the second side of the chip and the second row of outer pins in the two rows adopts a loop connection method.

4. The thin-film flip-chip packaging according to claim 1, wherein, The output internal pins are arranged on both sides of the chip. The traces between the internal output pins on the first side of the chip and their corresponding external output pins are connected in a straight-pull manner, while the traces between the internal output pins on the second side of the chip and their corresponding external output pins are connected in a loop manner.

5. The thin-film flip-chip packaging according to claim 1, wherein, The output pins are either all located on the first side of the chip or all located on the second side of the chip. With all the internal output pins arranged on the first side of the chip, the traces between the internal output pins and their corresponding external output pins are connected using a pull-through method, and With all the internal output pins arranged on the second side of the chip, the routing between the internal output pins and their corresponding external output pins adopts a loop connection method.

6. The thin-film flip-chip packaging according to claim 1, wherein, The input pins are arranged on both sides of the chip. The traces between the input internal pins arranged on the first side of the chip and their corresponding input external pins are connected in a straight-pull manner, and the traces between the input internal pins arranged on the second side of the chip and their corresponding input external pins are connected in a loop manner.

7. The thin-film flip-chip packaging according to claim 1, wherein, The input pins are either all located on the first side of the chip or all located on the second side of the chip. With all the input internal pins arranged on the first side of the chip, the traces between the input internal pins and their corresponding input external pins are connected using a straight-pull connection method, and With all the input internal pins arranged on the second side of the chip, the routing between the input internal pins and their corresponding input external pins adopts a loop connection method.

8. The thin-film flip-chip package according to any one of claims 1 to 7, wherein, The at least two rows of external pins are arranged either aligned or staggered.

9. The thin-film flip-chip package according to any one of claims 1 to 7, wherein, All traces between the input external pin and the input internal pin, and between the output internal pin and the output external pin, are formed by a single conductor layer on the film substrate.

10. The thin-film flip-chip packaging according to claim 1, wherein, The input and output external pins are arranged in three rows or four rows.

11. The thin-film flip-chip packaging according to claim 10, wherein, All traces between the input external pin and the input internal pin, and between the output internal pin and the output external pin, are formed by two mutually isolated conductive layers formed on two opposite surfaces of the film substrate.

12. The thin-film flip-chip packaging according to claim 1, wherein, The thin-film flip-chip package enables signal input to and output from the chip via a single bonding process with an external circuit board at only the external pins.

13. A display device, comprising: Thin-film flip-chip packaging as described in any one of claims 1-12; The display panel is used to display the content to be displayed; A backlight panel, on which a backlight circuit is provided, for providing backlight to the display panel; A control circuit board, on which control circuitry is provided, is used to provide backlight control signals to the chip in the thin-film flip-chip package and / or to obtain backlight-related signals from the chip. The input pin of the thin-film flip-chip package receives the backlight control signal from the control circuit, and the output pin provides the backlight drive signal to the backlight circuit and / or provides the backlight related signal to the control circuit. The backlight drive signal is generated by the chip based on the backlight control signal.

14. The display device according to claim 13, further comprising: A connecting circuit board is used to connect the control circuit board to the backlight board for signal transmission between the control circuit board and the backlight board.

15. The display device according to claim 13 or 14, wherein, A bonding area is provided on the backlight board, and the input and output external pins of the thin-film flip-chip package are attached to the bonding area. The backlight control signal from the control circuit board is transmitted to the bonding area of ​​the backlight panel. The backlight control signal is provided to the input pin of the thin-film flip-chip package via the bonding area, and the backlight drive signal generated by the chip is provided to the backlight circuit on the backlight board via the output pin of the thin-film flip-chip package.

16. The display device according to claim 13 or 14, wherein, The control circuit board has a bonding area, and the input and output external pins of the thin-film flip-chip package are attached to the bonding area. The control circuit provides the backlight control signal to the input pin of the thin-film flip-chip package via the bonding region. The backlight drive signal generated by the chip based on the backlight control signal from the output pin of the thin-film flip-chip package is provided to the backlight circuit on the backlight board via the bonding area.

17. The display device according to claim 13 or 14, wherein, The control circuit board is vertically disposed below the backlight panel, and the lower surface of the control circuit board is in contact with the lower surface of the backlight panel. A bonding area is provided on the upper surface of the control circuit board, and the input and output external pins of the thin-film flip-chip package are attached to the bonding area. The control circuit provides the backlight control signal to the input pin of the thin-film flip-chip package via the bonding region. The backlight drive signal generated by the chip based on the backlight control signal from the output pin of the thin-film flip-chip package is provided to the backlight circuit on the backlight board via the bonding area.

18. A display device, comprising: Thin-film flip-chip packaging as described in any one of claims 1-12; The display panel has a display circuit installed on it; A control circuit board, on which control circuitry is provided, is used to provide display control signals to the display circuitry, and to provide display drive control signals to the chip in the thin-film flip-chip package and / or to obtain display-related signals from the chip. The input pin of the thin-film flip-chip package receives the display drive control signal from the control circuit, and the output pin provides the display drive signal to the display circuit and / or provides the display-related signal to the control circuit. The display drive signal is generated by the chip based on the display drive control signal.

19. The display device according to claim 18, further comprising: A connecting circuit board is used to connect the control circuit board to the display panel for signal transmission between the control circuit board and the display panel.

20. The display device according to claim 18 or 19, wherein, The display panel has a bonding area, and the input and output external pins of the thin-film flip-chip package are attached to the bonding area. The display drive control signal from the control circuit board is transmitted to the bonding area of ​​the display panel. The display drive control signal is provided to the input external pin of the thin-film flip-chip package via the bonding area, and the display drive signal generated by the chip based on the display drive control signal is provided to the display circuit on the display panel via the output external pin of the thin-film flip-chip package.

21. The display device according to claim 18 or 19, wherein, The control circuit board has a bonding area, and the input and output external pins of the thin-film flip-chip package are attached to the bonding area. The control circuit provides a display drive control signal to the input pin of the thin-film flip-chip package via the bonding area. The display drive signal generated by the chip based on the display drive control signal from the output external pin of the thin-film flip-chip package is provided to the display circuit on the display panel via the bonding area.

22. The display device according to claim 18 or 19, wherein, The control circuit board is vertically disposed below the display panel, and the lower surface of the control circuit board is in contact with the lower surface of the display panel. A bonding area is provided on the upper surface of the control circuit board, and the input and output external pins of the thin-film flip-chip package are attached to the bonding area. The control circuit provides a display drive control signal to the input pin of the thin-film flip-chip package via the bonding area. The display drive signal generated by the chip based on the display drive control signal from the output external pin of the thin-film flip-chip package is provided to the display circuit on the display panel via the bonding area.

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