Inter-integrated circuit (IIC) bus quantity expansion device
By using two independent expansion chips to control the SCL and SDA signals in the IIC bus system and switching channels via an external switch, the connection limitation problem caused by the fixed device address on the IIC bus is solved, achieving an exponential expansion of the number of devices and an improvement in system stability.
Patent Information
- Application Number
- CN202520455594.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2026-01-20
- Estimated Expiration
- 2035-03-17
AI Technical Summary
In existing IIC bus systems, the addresses of some devices are fixed and cannot be configured, which makes it impossible to connect multiple devices on the same IIC bus, increasing production costs and failing to meet device connectivity requirements.
Two independent IIC expansion chips are used to control the SCL and SDA signals respectively, and the channels are switched by an external switch to achieve exponential expansion of the number of devices. It supports different chip combinations, simplifies wiring design, improves system stability and reduces hardware costs.
It enables an exponential expansion of the number of IIC devices, reduces signal path cross-interference, simplifies wiring design, improves system stability, reduces hardware costs, and increases the ease of troubleshooting and maintenance.
Smart Images
Figure CN223815555U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to data transmission technical field, especially relate to a quantity expansion device of IIC bus. BACKGROUND
[0002] IIC (Inter-Integrated Circuit) bus is a widely used two-wire serial bus, mainly including two signal lines: SCL (clock signal line) and SDA (data signal line). Through the two signal lines, IIC bus can realize communication and data transmission between multiple devices. In IIC bus system, multiple IIC devices can be connected to a bus, as long as the addresses of these devices are different. IIC devices usually have 7-bit address lines, which means that theoretically, an IIC bus can connect up to 127 different devices. This design makes IIC bus have high flexibility and scalability in communication of multiple devices.
[0003] However, in practical applications, the addresses of some IIC devices are fixed and cannot be changed by configuration. For example, the IIC addresses of some optical modules are fixed. In this case, if multiple devices need to be connected to the same IIC bus, it is necessary to ensure that their addresses do not conflict. If the conflict cannot be avoided by configuring the address, only one device with a fixed address can be connected to an IIC bus. If multiple devices with fixed addresses need to be accessed, multiple IIC buses must be used, and only one device is connected to each bus, which not only increases production cost, but also leads to insufficient number of IIC buses to meet the demand, and cannot realize connection and management of more devices. UTILITY MODEL CONTENT
[0004] The utility model aims at providing a quantity expansion device of IIC bus to improve the above technical problems.
[0005] In order to realize the above utility model purpose, the utility model embodiment provides the following technical scheme:
[0006] A quantity expansion device of IIC bus, comprising a CPU module, a first IIC expansion chip, a second IIC expansion chip and an IIC device end; the SCL signal end of the CPU module is connected to the first signal input end of the first IIC expansion chip and the first signal input end of the second IIC expansion chip respectively; the SDA signal end of the CPU module is connected to the second signal input end of the first IIC expansion chip and the second signal input end of the second IIC expansion chip respectively; the signal output end of the first IIC expansion chip and the signal output end of the second IIC expansion chip are connected to the IIC device end.
[0007] Further, the IIC device end comprises a plurality of IIC devices; wherein, the maximum number of IIC devices of the IIC device end is the product of the number of channels of the first IIC expansion chip and the number of channels of the second IIC expansion chip.
[0008] Further, the first IIC expansion chip has 2N channels, and the second IIC expansion chip has 2M channels; wherein, each SDA channel of the first IIC expansion chip can be connected with at most M IIC devices, the SCL channel of the second IIC expansion chip can be connected with at most N IIC devices, each SCL channel of the first IIC expansion chip can be connected with at most M IIC devices, and each SDA channel of the second IIC expansion chip can be connected with at most N IIC devices.
[0009] Further, the channels of the first IIC expansion chip have 2N, wherein, N SCL channels and N SDA channels; the channels of the second IIC expansion chip have 2M, wherein, M SCL channels and M SDA channels; the SCL pin of each IIC device is connected with any SCL channel of the first IIC expansion chip, and the SDA pin is connected with any SDA channel of the second IIC expansion chip; or the SCL pin of each IIC device is connected with any SCL channel of the second IIC expansion chip, and the SDA pin is connected with any SDA channel of the first IIC expansion chip.
[0010] Further, the first IIC expansion chip and the second IIC expansion chip receive the instruction issued by the CPU through an external switch, select to open the corresponding SDA channel and close the corresponding SCL channel, or select to open the corresponding SCL channel and close the corresponding SDA channel; the external switch comprises a first control switch and a second control switch.
[0011] Further, the number of channels of the first IIC expansion chip is the same as the number of channels of the second IIC expansion chip.
[0012] Further, the number of channels of the first IIC expansion chip is different from the number of channels of the second IIC expansion chip.
[0013] Further, according to the position of each IIC device, the corresponding IIC device is accessed by switching the channels of the first IIC expansion chip and the second IIC expansion chip.
[0014] The beneficial effects of the utility model are as follows:
[0015] The utility model discloses two independent extension chip control corresponding SCL signal and SDA signal has realized the exponential extension of equipment quantity, has promoted single chip's extension ability greatly, and the most IIC equipment quantity that can connect is the product of first extension chip and second extension chip channel number, namely IIC equipment maximum quantity is NXM, through increasing external switch (first control switch, second control switch), the connection number of IIC equipment has improved again one time, namely IIC equipment maximum quantity is NXM2, through separating SCL and SDA signal to different extension chip, has reduced the cross and interference of signal path, has simplified the wiring design, has improved the stability and reliability of system simultaneously, supports the combination use of different specifications IIC extension chip, has reduced hardware cost and system complexity significantly, has increased the convenience of troubleshooting and maintenance. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical scheme of the embodiment of the utility model, the following will be needed to use the drawing in the embodiment briefly introduced, it should be understood, the following drawing only shows some certain embodiment of the utility model, therefore should not be seen as the limitation to the range, for the ordinary skill in the art person, under the premise of not paying the creative labor, can also obtain other relevant drawings according to these drawings.
[0017] Figure 1 It is the extension device structure diagram in the embodiment 1 of the utility model;
[0018] Figure 2 It is the extension device structure diagram in the embodiment 2 of the utility model;
[0019] Figure 3 It is the extension device structure diagram in the embodiment 3 of the utility model;
[0020] Figure 4 It is the extension device structure diagram under state 1 in the embodiment 4 of the utility model;
[0021] Figure 5 It is the extension device structure diagram under state 2 in the embodiment 4 of the utility model. DETAILED DESCRIPTION
[0022] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.
[0023] Embodiment 1
[0024] Please refer to Figure 1 The embodiment provides a quantity expansion device of an IIC bus, which comprises a CPU module, a first IIC expansion chip, a second IIC expansion chip and an IIC device end; a SCL signal end of the CPU module is connected with a first signal input end of the first IIC expansion chip and a first signal input end of the second IIC expansion chip respectively; an SDA signal end of the CPU module is connected with a second signal input end of the first IIC expansion chip and a second signal input end of the second IIC expansion chip respectively; and a signal output end of the first IIC expansion chip and a signal output end of the second IIC expansion chip are both connected with the IIC device end.
[0025] The IIC device end comprises a plurality of IIC devices; wherein a maximum value of the number of IIC devices of the IIC device end is a product of the number of channels of the first IIC expansion chip and the number of channels of the second IIC expansion chip.
[0026] The first IIC expansion chip has 2N channels, and the second IIC expansion chip has 2M channels; wherein each SDA channel of the first IIC expansion chip can be connected with at most M IIC devices, each SCL channel of the second IIC expansion chip can be connected with at most N IIC devices, each SCL channel of the first IIC expansion chip can be connected with at most M IIC devices, and each SDA channel of the second IIC expansion chip can be connected with at most N IIC devices.
[0027] The channel of the first IIC expansion chip has 2N, wherein N SCL channels, N SDA channels; the channel of the second IIC expansion chip has 2M, wherein M SCL channels, M SDA channels; the SCL pin of each IIC device is connected to any SCL channel of the first IIC expansion chip, and the SDA pin is connected to any SDA channel of the second IIC expansion chip; or the SCL pin of each IIC device is connected to any SCL channel of the second IIC expansion chip, and the SDA pin is connected to any SDA channel of the first IIC expansion chip.
[0028] The number of channels of the first IIC expansion chip is the same as the number of channels of the second IIC expansion chip.
[0029] The number of channels of the first IIC expansion chip is not the same as the number of channels of the second IIC expansion chip.
[0030] According to the position of each IIC device, the corresponding IIC device is accessed by switching the channels of the first IIC expansion chip and the second IIC expansion chip, that is, connecting the corresponding channel numbers of the two IIC expansion chips.
[0031] Embodiment 2:
[0032] As shown in Figure 2 The number expansion device of the embodiment includes a CPU module, a first IIC expansion chip, a second IIC expansion chip, and an IIC device end; the SCL signal end of the CPU module is connected to the first signal input end (SCL) of the first IIC expansion chip and the first signal input end (SCL) of the second IIC expansion chip respectively; the SDA signal end of the CPU module is connected to the second signal input end (SDA) of the first IIC expansion chip and the second signal input end (SDA) of the second IIC expansion chip respectively; the signal output end of the first IIC expansion chip and the signal output end of the second IIC expansion chip are connected to the IIC device end.
[0033] The internal structure of the first IIC expansion chip and the second IIC expansion chip is a one-to-many switch. The left side of the switch is connected to the CPU, and the right side is connected to multiple IIC devices. When the switch is switched to one of the paths, the CPU accesses the IIC device connected to this path.
[0034] The IIC device end includes multiple IIC devices; wherein the maximum number of IIC devices of the IIC device end is the product of the number of channels of the first IIC expansion chip and the number of channels of the second IIC expansion chip.
[0035] The first IIC expansion chip has 2N channels, and the second IIC expansion chip has 2M channels; wherein, each SDA channel of the first IIC expansion chip can be connected with at most M IIC devices, the SCL channel of the second IIC expansion chip can be connected with at most N IIC devices, each SCL channel of the first IIC expansion chip can be connected with at most M IIC devices, and each SDA channel of the second IIC expansion chip can be connected with at most N IIC devices.
[0036] The first IIC expansion chip has 2N channels, wherein, N SCL channels and N SDA channels; the second IIC expansion chip has 2M channels, wherein, M SCL channels and M SDA channels; the SCL pin of each IIC device is connected with any SCL channel of the first IIC expansion chip, and the SDA pin is connected with any SDA channel of the second IIC expansion chip.
[0037] The first IIC expansion chip and the second IIC expansion chip both control the switching of the built-in switch by receiving the instruction issued by the CPU, and switch the IIC signal of the CPU to the channel where the IIC device to be accessed is located.
[0038] The number of channels of the first IIC expansion chip is the same as that of the second IIC expansion chip, and both of them are 8 (4 SDA channels + 4 SCL channels) channel IIC expansion chips. Thus, the IIC device end includes 16 IIC devices, which are arranged in a matrix form as shown in Figure 2 .
[0039] According to the position of each IIC device, the corresponding IIC device is accessed by switching the channels of the first IIC expansion chip and the second IIC expansion chip.
[0040] The corresponding first switch instruction and second switch instruction are respectively issued to the first IIC expansion chip and the second IIC expansion chip by the CPU module; according to the first switch instruction, the first IIC expansion chip switches the SCL signal of the CPU to the channel to be accessed; according to the second switch instruction, the second IIC expansion chip switches the SDA signal of the CPU to the channel to be accessed; when the device 23 is accessed, the addresses of all IIC devices are 50, then the first IIC expansion chip with address 70 is switched to the corresponding channel 2 (SCL2), and the second IIC expansion chip with address 71 is switched to the corresponding channel 3 (SDA3), so that the device with address 50 is accessed, that is, the device 23 is accessed.
[0041] Example 2 demonstrates that, under the condition that the number of channels of the first IIC expansion chip is the same as the number of channels of the second IIC expansion chip, by controlling the corresponding SCL and SDA signals through two independent expansion chips, an exponential expansion of the number of devices can be achieved. Only two IIC expansion chips are needed to connect 16 IIC devices.
[0042] Example 3:
[0043] like Figure 3 As shown, the quantity expansion device in this embodiment includes a CPU module, a first IIC expansion chip, a second IIC expansion chip, and an IIC device terminal; the SCL signal terminal of the CPU module is connected to the first signal input terminal (SCL) of the first IIC expansion chip and the first signal input terminal (SCL) of the second IIC expansion chip respectively; the SDA signal terminal of the CPU module is connected to the second signal input terminal (SDA) of the first IIC expansion chip and the second signal input terminal (SDA) of the second IIC expansion chip respectively; the signal output terminals of the first IIC expansion chip and the second IIC expansion chip are both connected to the IIC device terminal.
[0044] The internal structure of the first and second IIC expansion chips is a one-to-many switch. The left side of the switch is connected to the CPU, and the right side is connected to multiple IIC devices. When the switch is switched to one of the channels, the IIC devices connected to that channel can be accessed.
[0045] The IIC device end includes multiple IIC devices; wherein, the maximum number of IIC devices on the IIC device end is the product of the number of channels of the first IIC expansion chip and the number of channels of the second IIC expansion chip.
[0046] The first IIC expansion chip has 2N channels, and the second IIC expansion chip has 2M channels. Each SDA channel of the first IIC expansion chip can connect to a maximum of M IIC devices, and each SCL channel of the second IIC expansion chip can connect to a maximum of N IIC devices.
[0047] The first IIC expansion chip has 2N channels, including N SCL channels and N SDA channels; the second IIC expansion chip has 2M channels, including M SCL channels and M SDA channels; the SCL pin of each IIC device is connected to any one of the SCL channels of the first IIC expansion chip, and the SDA pin is connected to any one of the SDA channels of the second IIC expansion chip.
[0048] The first IIC expansion chip and the second IIC expansion chip both control the switching of the built-in switch by receiving the instruction issued by the CPU, so as to switch the IIC signal of the CPU to the channel where the IIC device to be accessed is located.
[0049] The number of channels of the first IIC expansion chip is different from the number of channels of the second IIC expansion chip. The first IIC expansion chip adopts an IIC expansion chip with 8 channels (4 SDA channels + 4 SCL channels), and the second IIC expansion chip adopts an IIC expansion chip with 12 (6 SDA channels + 6 SCL channels) channels.
[0050] According to the location of each IIC device, the corresponding IIC device is accessed by switching the channels of the first IIC expansion chip and the second IIC expansion chip.
[0051] The corresponding first switch instruction and second switch instruction are respectively issued to the first IIC expansion chip and the second IIC expansion chip by the CPU module; according to the first switch instruction, the first IIC expansion chip switches the SCL signal of the CPU to the channel to be accessed; according to the second switch instruction, the second IIC expansion chip switches the SDA signal of the CPU to the channel to be accessed; when the device 46 needs to be accessed, the addresses of all the IIC devices are 50, the first IIC expansion chip with the address of 70 is switched to the corresponding channel 4 (SCL4), and then the second IIC expansion chip with the address of 71 is switched to the corresponding channel 6 (SDA6), so as to access the device with the address of 50, i.e. the device 46, by the CPU.
[0052] Embodiment 3 shows that under the condition that the number of channels of the first IIC expansion chip is different from the number of channels of the second IIC expansion chip, the corresponding SCL signal and SDA signal are controlled by two independent expansion chips, so as to realize exponential expansion of the number of devices, and only two IIC expansion chips are needed to realize connection of 24 IIC devices.
[0053] Embodiment 4:
[0054] The number expansion device of the embodiment comprises a CPU module, a first IIC expansion chip, a second IIC expansion chip and an IIC device end; the SCL signal end of the CPU module is connected to the first signal input end of the first IIC expansion chip and the first signal input end of the second IIC expansion chip respectively; the SDA signal end of the CPU module is connected to the second signal input end of the first IIC expansion chip and the second signal input end of the second IIC expansion chip respectively; the signal output end of the first IIC expansion chip and the signal output end of the second IIC expansion chip are both connected to the IIC device end.
[0055] The quantity expansion equipment further comprises two control switches, a first control switch connected with the first IIC expansion chip and the IIC device end respectively, and the on-off of the control switch is controlled by CPU instruction; a second control switch connected with the second IIC expansion chip and the IIC device end respectively, and the on-off of the control switch is controlled by CPU instruction. The first control switch and the second control switch are used for controlling the output of the first IIC expansion chip and the second IIC expansion chip.
[0056] The internal structure of the first IIC expansion chip and the second IIC expansion chip is a one-to-many switching switch. The input end of the first control switch is connected with the output end of the first IIC expansion chip, and the multiple output ends of the first control switch are connected with multiple IIC devices respectively; the input end of the second control switch is connected with the output end of the second IIC expansion chip, and the multiple output ends of the second control switch are connected with multiple IIC devices respectively.
[0057] In the case of no external switch (the first control switch and the second control switch) and only IIC expansion chip, the maximum number of IIC devices is NXM; after the external switch is added, the maximum number of IIC devices is NXMx2. By adding the external switch, the number of IIC device ends is further increased.
[0058] The first IIC expansion chip has 2N channels, and the second IIC expansion chip has 2M channels; wherein, each SDA channel of the first IIC expansion chip can be connected with M IIC devices at most, the SCL channel of the second IIC expansion chip can be connected with N IIC devices at most, each SCL channel of the first IIC expansion chip can be connected with M IIC devices at most, and each SDA channel of the second IIC expansion chip can be connected with N IIC devices at most.
[0059] The channels of the first IIC expansion chip have 2N, wherein, N SCL channels and N SDA channels; the channels of the second IIC expansion chip have 2M, wherein, M SCL channels and M SDA channels; the SCL pin of each IIC device is connected with any output end of the first control switch, and the SCL pin of the first control switch is connected with any SCL channel of the first IIC expansion chip; the SDA pin of each IIC device is connected with any output end of the second control switch, and the SDA pin of the second control switch is connected with any SDA channel of the second IIC expansion chip.
[0060] The number of channels in the first IIC expansion chip is different from the number of channels in the second IIC expansion chip. The first IIC expansion chip is a 12-channel IIC expansion chip (6 SDA channels + 6 SCL channels), and the second IIC expansion chip is an 8-channel IIC expansion chip (4 SDA channels + 4 SCL channels).
[0061] Based on the connection relationship between each IIC device and two expansion chips and two control switches, the corresponding IIC device can be accessed by controlling the on or off state of the first and second control switches and by controlling the channel switching position of the first and second IIC expansion chips.
[0062] like Figure 4 As shown, in state 1, the CPU module sends corresponding first and second switch instructions to the first and second IIC expansion chips respectively, and transmits the SCL signal to the first IIC expansion chip and the SDA signal to the second IIC expansion chip. The CPU module also sends a switching instruction to the first control switch, which selects to output only the SCL signal, thus enabling the corresponding SCL channel (mode A) and disabling the corresponding SDA channel. Similarly, the CPU module sends a switching instruction to the second control switch, which outputs only the SDA signal, thus enabling the corresponding SDA channel (mode A) and disabling the corresponding SCL channel. When accessing device A64 is required, since the address of all IIC devices is currently 50, the external switch's mode A is first determined. Then, the first IIC expansion chip with address 70 is switched to the corresponding channel 6 (A6), and the second IIC expansion chip with address 71 is switched to the corresponding channel 4 (A4). The CPU then accesses the device with address 50, i.e., accesses device A64. Figure 5As shown, in the state 2, the CPU module issues the corresponding first switch instruction and the second switch instruction to the first IIC expansion chip and the second IIC expansion chip respectively, and transmits the SDA signal to the first IIC expansion chip and the SCL signal to the second IIC expansion chip; the CPU module issues the switching instruction to the first control switch, the first control switch selects to output only the SDA signal, thereby opening the corresponding SDA channel (mode B) and closing the corresponding SCL channel; the CPU module issues the switching instruction to the second control switch, the second control switch outputs only the SCL signal, thereby selecting to open the corresponding SCL channel (mode B) and close the corresponding SDA channel; when the device B64 needs to be accessed, the addresses of all the IIC devices are 50, then the mode B of the external switch is determined first, the first IIC expansion chip with the address of 70 is switched to the corresponding channel 6 (B6), the second IIC expansion chip with the address of 71 is switched to the corresponding channel 4 (B4), and the device with the address of 50 is accessed through the CPU, that is, the device B64 is accessed.
[0063] The embodiment 4 shows that under the condition that the number of channels of the first IIC expansion chip is different from the number of channels of the second IIC expansion chip, the corresponding SCL signal and SDA signal are controlled through two independent expansion chips, the exponential expansion of the number of devices is realized, 24 IIC devices can be connected, and through the switching of the first control switch and the second control switch, the number of IIC devices is doubled again, and 48 IIC devices can be connected.
[0064] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited to this, any skilled person in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be the protection scope of the claims.
Claims
1. A quantity expansion device of an IIC bus, characterized by, The CPU module, the first IIC expansion chip, the second IIC expansion chip and the IIC device end are included; the SCL signal end of the CPU module is connected with the first signal input end of the first IIC expansion chip and the first signal input end of the second IIC expansion chip respectively; the SDA signal end of the CPU module is connected with the second signal input end of the first IIC expansion chip and the second signal input end of the second IIC expansion chip respectively; the signal output end of the first IIC expansion chip and the signal output end of the second IIC expansion chip are connected with the IIC device end.
2. The quantity expansion apparatus of the IIC bus according to claim 1, wherein, The IIC device end includes a plurality of IIC devices; wherein the maximum number of IIC devices of the IIC device end is the product of the number of channels of the first IIC expansion chip and the number of channels of the second IIC expansion chip.
3. The quantity expansion apparatus of the IIC bus according to claim 2, wherein, The first IIC expansion chip has 2N channels, and the second IIC expansion chip has 2M channels; wherein each SDA channel of the first IIC expansion chip can be connected with at most M IIC devices, the SCL channel of the second IIC expansion chip can be connected with at most N IIC devices, each SCL channel of the first IIC expansion chip can be connected with at most M IIC devices, and each SDA channel of the second IIC expansion chip can be connected with at most N IIC devices.
4. The quantity expansion apparatus of the IIC bus according to claim 2, wherein, The channels of the first IIC expansion chip have 2N, wherein N SCL channels and N SDA channels; the channels of the second IIC expansion chip have 2M, wherein M SCL channels and M SDA channels; the SCL pin of each IIC device is connected with any SCL channel of the first IIC expansion chip, and the SDA pin is connected with any SDA channel of the second IIC expansion chip; or the SCL pin of each IIC device is connected with any SCL channel of the second IIC expansion chip, and the SDA pin is connected with any SDA channel of the first IIC expansion chip.
5. The quantity expansion apparatus of the IIC bus according to claim 1, wherein, The first IIC expansion chip and the second IIC expansion chip receive the instructions issued by the CPU through external switches, select to open the corresponding SDA channel and close the corresponding SCL channel, or select to open the corresponding SCL channel and close the corresponding SDA channel; the external switches include a first control switch and a second control switch.
6. The quantity expansion apparatus of the IIC bus according to claim 1, wherein, The number of channels of the first IIC expansion chip is the same as the number of channels of the second IIC expansion chip.
7. The quantity expansion apparatus of the IIC bus according to claim 1, wherein The number of channels of the first IIC expansion chip is not the same as the number of channels of the second IIC expansion chip.
8. The quantity expansion apparatus of the IIC bus according to claim 2, wherein, According to the position of each IIC device, the corresponding IIC device is accessed by switching the channels of the first IIC expansion chip and the second IIC expansion chip.