Display device and mobile electronic device

Abstract

The utility model relates to a display device and a mobile electronic device. The display device includes: a pixel driving circuit including a plurality of pixel transistors; the scanning driver comprises a first transistor group and a second transistor group; and a display panel including a semiconductor substrate, a complementary metal oxide semiconductor (CMOS) layer on the semiconductor substrate, and an emission material layer on the CMOS layer, in which the CMOS layer includes a first well region doped with a first type of impurity and a second well region doped with a second type of impurity, the first well region and the second well region are in a display region of the display panel, and wherein the plurality of pixel transistors and the first transistor group are in the first well region, and the second transistor group is in the second well region.

Description

Technical Field

[0001] This disclosure relates to display devices and mobile electronic devices. Background Technology

[0002] Currently, wearable devices in the form of glasses or helmets are being developed. These devices are able to focus at a position close to the user's eyes. For example, wearable devices can be head-mounted display (HMD) devices or AR glasses. Such wearable devices provide users with augmented reality (hereinafter referred to as "AR") or virtual reality (hereinafter referred to as "VR") visuals.

[0003] Wearable devices such as HMD devices and AR glasses require a display specification of at least 2000 PPI (pixels per inch) to allow users to use them for extended periods without experiencing dizziness. For this purpose, organic light-emitting diode-on-silicon (OLEDoS) technology has emerged, enabling the creation of high-resolution, small-sized organic light-emitting element display devices. OLEDoS is a technology that deposits organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which complementary metal-oxide-semiconductor (CMOS) elements are disposed.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the background technology of this disclosure, and therefore may contain information that does not constitute prior art. Utility Model Content

[0005] This disclosure relates to a display device that can increase the size of the display screen by reducing the non-display area, and a mobile electronic device including the display device.

[0006] According to some embodiments of this disclosure, a display device is provided, comprising: a pixel driving circuit including a plurality of pixel transistors; a scan driver including a first transistor group and a second transistor group; and a display panel including a semiconductor substrate, a complementary metal-oxide-semiconductor (CMOS) layer on the semiconductor substrate, and an emitter material layer on the CMOS layer, wherein the CMOS layer includes a first well region doped with a first type of impurity and a second well region doped with a second type of impurity, the first well region and the second well region being in a display area of ​​the display panel, and wherein the plurality of pixel transistors and the first transistor group are in the first well region, and the second transistor group is in the second well region.

[0007] In some implementations, the multiple pixel transistors include p-type MOSFETs.

[0008] In some implementations, the first transistor group includes a p-type MOSFET, and the second transistor group includes an n-type MOSFET.

[0009] In some implementations, the first type of impurity is an n-type impurity, and the second type of impurity is a p-type impurity.

[0010] In some implementations, the multiple pixel transistors include n-type MOSFETs.

[0011] In some implementations, the first transistor group includes an n-type MOSFET, and the second transistor group includes a p-type MOSFET.

[0012] In some implementations, the first type of impurity is a p-type impurity, and the second type of impurity is an n-type impurity.

[0013] In some implementations, the first well region and the second well region are adjacent to each other to form a double well region, and a plurality of double well regions including the double well region are arranged in a matrix pattern in the display area.

[0014] In some implementations, the first well region and the second well region correspond to four sub-pixels of the display panel arranged in a 2×2 matrix, and the first well region surrounds the second well region.

[0015] In some implementations, the first well region includes a pair of first well regions, the pair of first well regions and the second well region corresponding to four sub-pixels of the display panel arranged in a 2×2 matrix, and the second well region is located between the pair of first well regions.

[0016] According to some embodiments of the present disclosure, a mobile electronic device is provided, comprising: a display panel including a semiconductor substrate, a complementary metal-oxide-semiconductor (CMOS) layer on the semiconductor substrate, and an emitter material layer on the CMOS layer, wherein the CMOS layer includes a first well region doped with a first type of impurity and a second well region doped with a second type of impurity, the first well region and the second well region being in a display area of ​​the display panel, and wherein a plurality of pixel transistors of a pixel driving circuit and a first transistor group of a scan driver are in the first well region, and a second transistor group of the scan driver is in the second well region.

[0017] In some implementations, the multiple pixel transistors include p-type MOSFETs.

[0018] In some implementations, the first transistor group includes a p-type MOSFET, and the second transistor group includes an n-type MOSFET.

[0019] In some implementations, the first type of impurity is an n-type impurity, and the second type of impurity is a p-type impurity.

[0020] In some implementations, the multiple pixel transistors include n-type MOSFETs.

[0021] In some implementations, the first transistor group includes an n-type MOSFET, and the second transistor group includes a p-type MOSFET.

[0022] In some implementations, the first type of impurity is a p-type impurity, and the second type of impurity is an n-type impurity.

[0023] In some implementations, the first well region and the second well region are adjacent to each other to form a double well region, and a plurality of double well regions including the double well region are arranged in a matrix pattern in the display area.

[0024] In some implementations, the first well region and the second well region correspond to four sub-pixels of the display panel arranged in a 2×2 matrix, and the first well region surrounds the second well region.

[0025] In some implementations, the first well region includes a pair of first well regions, the pair of first well regions and the second well region corresponding to four sub-pixels arranged in a 2×2 matrix, and the second well region is located between the pair of first well regions.

[0026] In the display device according to the embodiment and the mobile electronic device including the display device, the size of the display screen can be expanded by reducing the non-display area. Attached Figure Description

[0027] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0028] Figure 1 This is a perspective view of a head-mounted display device according to some embodiments of the present disclosure.

[0029] Figure 2 This is based on some embodiments of the present disclosure. Figure 1 An exploded perspective view of a head-mounted display device.

[0030] Figure 3 This is a perspective view of a head-mounted display device according to some embodiments of the present disclosure.

[0031] Figure 4 This is an exploded perspective view showing a display device according to some embodiments of the present disclosure.

[0032] Figure 5 This is a view showing the layout of the display panel according to the comparative example.

[0033] Figure 6 This illustrates some embodiments according to the present disclosure. Figure 4 A view of the layout of the display panel.

[0034] Figure 7 This is a block diagram illustrating a display device according to some embodiments of the present disclosure.

[0035] Figure 8 This is an equivalent circuit diagram of the first sub-pixel according to some embodiments of the present disclosure.

[0036] Figure 9 This is an equivalent circuit diagram of a scan driver according to some embodiments of the present disclosure.

[0037] Figure 10 This is a cross-sectional view showing an example of a display panel according to some embodiments of the present disclosure.

[0038] Figure 11 This is a view showing the layout of the first sub-pixel according to some embodiments of this disclosure.

[0039] Figure 12 This is a view showing the layout of pixel groups according to some embodiments of this disclosure.

[0040] Figure 13 This is an equivalent circuit diagram of the first sub-pixel according to some embodiments of the present disclosure.

[0041] Figure 14 This is a view showing the layout of pixel groups according to some embodiments of this disclosure. Detailed Implementation

[0042] This disclosure will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the disclosure are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0043] Features of each of the various embodiments of this disclosure may be combined partially or completely with each other, and may be technically different from each other in their cooperation. Furthermore, the various embodiments may be implemented independently of each other or may be implemented in conjunction with each other.

[0044] In the following description, some specific embodiments will be described with reference to the accompanying drawings.

[0045] Figure 1 This is a perspective view of a head-mounted display device according to some embodiments of the present disclosure. Figure 2 This is based on some embodiments of the present disclosure. Figure 1 An exploded perspective view of a head-mounted display device.

[0046] refer to Figure 1 and Figure 2According to some embodiments, the head-mounted display device 1 includes a first display device 10_1, a second display device 10_2, a display device housing 110 and a housing cover 120, a first eyepiece 131, a second eyepiece 132, a headband 140, a middle frame 160, a first optical component 151, a second optical component 152, a control circuit board 170, and a connector.

[0047] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. Each of the first display device 10_1 and the second display device 10_2 is associated with a reference. Figures 4 to 14 The described display devices 10 are the same or substantially the same. Therefore, for the description of the first display device 10_1 and the second display device 10_2, please refer to... Figures 4 to 14 The description.

[0048] The first optical component 151 may be disposed between the first display device 10_1 and the first eyepiece 131. The second optical component 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical component 151 and the second optical component 152 may include at least one convex lens.

[0049] The intermediate frame 160 can be disposed between the first display device 10_1 and the control circuit board 170, and can also be disposed between the second display device 10_2 and the control circuit board 170. The intermediate frame 160 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0050] The control circuit board 170 can be disposed between the intermediate frame 160 and the display device housing 110. The control circuit board 170 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 170 can convert externally input images into digital video data (DATA), and can transmit the digital video data (DATA) to the first display device 10_1 and the second display device 10_2 via connectors.

[0051] The control circuit board 170 can transmit digital video data (DATA) related to a left-eye image configured (e.g., optimized) for the user's left eye to the first display device 10_1, and can transmit digital video data (DATA) related to a right-eye image configured (e.g., optimized) for the user's right eye to the second display device 10_2. In some examples, the control circuit board 170 can transmit the same digital video data (DATA) to both the first display device 10_1 and the second display device 10_2.

[0052] The display device housing 110 houses a first display device 10_1, a second display device 10_2, a middle frame 160, a first optical component 151, a second optical component 152, a control circuit board 170, and a connector. A housing cover 120 is configured to cover the opening of the display device housing 110. The housing cover 120 may include a first eyepiece 131 for the user's left eye and a second eyepiece 132 for the user's right eye. Although the first eyepiece 131 and the second eyepiece 132 are located in... Figure 1 and Figure 2 The examples shown are configured separately, but embodiments of this disclosure are not limited thereto. The first eyepiece 131 and the second eyepiece 132 can be combined into a single element.

[0053] The first eyepiece 131 can be aligned with the first display device 10_1 and the first optical component 151, and the second eyepiece 132 can be aligned with the second display device 10_2 and the second optical component 152. Therefore, a user can see a virtual image on the first display device 10_1 magnified by the first optical component 151 through the first eyepiece 131, and a virtual image on the second display device 10_2 magnified by the second optical component 152 through the second eyepiece 132. Here, the term "virtual image" refers to an artificial image generated and displayed by the head-mounted display device 1.

[0054] The headband 140 secures the display device housing 110 to the user's head, such that the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 are aligned with the user's left and right eyes, respectively. By achieving a lightweight and small display device housing 110, the head-mounted display device 1 can include, for example... Figure 3 The eyeglass frame shown is used instead of the headband 140.

[0055] In addition, the head-mounted display device 1 may also include a battery for power supply, an external memory slot for inserting external memory, an external connection port, and a wireless communication module for receiving images. The external connection port may be a USB (Universal Serial Bus) terminal, a display port, or an HDMI (High-Definition Multimedia Interface) terminal. The wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0056] Figure 3 This is a perspective view of a head-mounted display device according to some embodiments of the present disclosure.

[0057] refer to Figure 3According to some embodiments, the head-mounted display device 1_1 can be an eyeglass-type display device with a lightweight and small display device housing 120_1. According to some embodiments, the head-mounted display device 1_1 may include a display device 10_3, a left eye lens 311, a right eye lens 312, a support frame 350, temples 341 and 342, an optical component 320, a light path conversion component 330, and the display device housing 120_1.

[0058] Figure 3 The display device 10_3 shown is related to the reference. Figures 4 to 14 The described display device 10 is the same as or substantially the same. Therefore, for the description of display device 10_3, please refer to... Figures 4 to 14 The description.

[0059] The display device housing 120_1 can accommodate the display device 10_3, the optical component 320, and the light path conversion component 330. The image displayed on the display device 10_3 can be magnified by the optical component 320, and the light path of the image is converted by the light path conversion component 330 to be provided to the user's right eye through the right eye lens 312. Therefore, the user can see an augmented reality image with their right eye, which combines a virtual image generated by and displayed on the display device 10_3 with a real-world image seen through the right eye lens 312.

[0060] Despite Figure 3 In the example shown, the display device housing 120_1 is located at the right end of the support frame 350, but the embodiments of this disclosure are not limited thereto. For example, the display device housing 120_1 may be located at the left end of the support frame 350. In this case, the image displayed on the display device 10_3 can be provided to the user's left eye. In some examples, the display device housing 120_1 may be located at both the left and right ends of the support frame 350. In this case, the user can view the image displayed on the display device 10_3 through both the left and right eyes.

[0061] Figure 4 This is an exploded perspective view showing a display device according to some embodiments of the present disclosure. Figure 5 This is a view showing the layout of the display panel according to the comparative example. Figure 6 This illustrates some embodiments according to the present disclosure. Figure 4 A view of the layout of the display panel. Figure 7 This is a block diagram illustrating a display device according to some embodiments of the present disclosure.

[0062] refer to Figure 4 and Figure 5The display device 10 can display moving and still images. According to some embodiments, the display device 10 can be employed by portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be used as a display unit for televisions, laptop computers, monitors, electronic billboards, or Internet of Things (IoT) devices. In some examples, the display device 10 can be applied to smartwatches, smartwatch phones, or head-mounted displays (HMDs) for implementing virtual and augmented reality.

[0063] According to some embodiments, the display device 10 includes a display panel 410, a heat dissipation layer 420, a circuit board 430, and a driver circuit 440.

[0064] When viewed from above, the display panel 410 may have a shape similar to a rectangle. For example, when viewed from above, the display panel 410 may have a shape similar to a rectangle having a shorter side in a first direction DR1 and a longer side in a second direction DR2 that intersects the first direction DR1. In the display panel 410, the corner where the shorter side in the first direction DR1 intersects the longer side in the second direction DR2 may be a rounded corner with a set or predetermined curvature or may form a right angle. When viewed from above, the shape of the display panel 410 is not limited to a rectangular shape, but may be formed into a shape similar to other polygonal shapes, circular shapes, or elliptical shapes. When viewed from above, the shape of the display device 10 may follow the shape of the display panel 410, but embodiments of this disclosure are not limited thereto.

[0065] The display panel 410 may include a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0066] The display area DAA includes multiple sub-pixels SP, multiple scan lines SL, multiple emission control lines EL, and multiple data lines DL.

[0067] Subpixels SP include light-emitting elements LE (see...) Figure 8 Subpixels SP can be arranged in a matrix on the first direction DR1 and the second direction DR2. Scan lines SL and emission control lines EL can extend on the first direction DR1 and can be arranged on the second direction DR2. Data lines DL can extend on the second direction DR2 and can be arranged on the first direction DR1.

[0068] The multiple scan lines SL include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines EBL. The multiple emit control lines EL include multiple first emit control lines EL1 and multiple second emit control lines EL2.

[0069] As will be referred to later Figure 10 As described, multiple sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For example... Figure 8 As shown, each of the plurality of sub-pixels SP1, SP2, and SP3 includes a plurality of pixel transistors T1, T2, T3, T4, T5, and T6. The plurality of pixel transistors T1, T2, T3, T4, T5, and T6 (see, for example, [reference needed]). Figure 8 It can be formed through semiconductor processes and can be placed on a semiconductor substrate SSUB (e.g., see...). Figure 10 On. For example, multiple pixel transistors T1, T2, T3, T4, T5, and T6 (see, for example, see...) Figure 8 It can be formed from complementary metal-oxide-semiconductor (CMOS).

[0070] Each of a plurality of sub-pixels SP (e.g., sub-pixels SP1, SP2, or SP3) may be connected to one of the write scan lines GWL, one of the control scan lines GCL, one of the bias scan lines EBL, one of the first emitt control lines EL1, one of the second emitt control lines EL2, and one of the data lines DL. Each of sub-pixels SP1, SP2, and SP3 may receive a data voltage from the data line DL according to the write scan signal from the write scan line GWL, and may allow the light-emitting element LE (see...) Figure 8 It emits light based on the data voltage.

[0071] according to Figure 5 In the comparative example shown, the non-display area NDA of the display panel 410 includes a scan driving area SDA, a data driving area DDA, and a pad area PDA.

[0072] The scan driver region SDA is equipped with a scan driver 510 and a transmit driver 520.

[0073] Scan driver 510 includes a plurality of scan transistors, and emitter driver 520 includes a plurality of light-emitting transistors. The plurality of scan transistors and the plurality of light-emitting transistors are formed via semiconductor processes and can be formed on a semiconductor substrate SSUB (e.g., see...). Figure 10 For example, multiple scanning transistors and multiple light-emitting transistors can be formed using CMOS.

[0074] refer to Figure 7The scan driver 510 may include a write scan signal output unit 511, a control scan signal output unit 512, and a bias scan signal output unit 513. Each of the write scan signal output unit 511, the control scan signal output unit 512, and the bias scan signal output unit 513 may receive a scan timing control signal SCS from a timing control circuit (also called a timing controller) 610. The write scan signal output unit 511 can generate a write scan signal based on the scan timing control signal SCS from the timing control circuit 610, and sequentially outputs the write scan signal to the write scan line GWL. The control scan signal output unit 512 can generate a control scan signal based on the scan timing control signal SCS, and sequentially outputs the control scan signal to the control scan line GCL. The bias scan signal output unit 513 can generate a bias scan signal based on the scan timing control signal SCS, and sequentially outputs the bias scan signal to the bias scan line EBL.

[0075] refer to Figure 7 The transmit driver 520 includes a first transmit control driver 521 and a second transmit control driver 522. Each of the first transmit control driver 521 and the second transmit control driver 522 can receive a transmit timing control signal ECS from the timing control circuit 610. The first transmit control driver 521 can generate a first transmit control signal according to the transmit timing control signal ECS and sequentially outputs the first transmit control signal to the first transmit control line EL1. The second transmit control driver 522 can generate a second transmit control signal according to the transmit timing control signal ECS and sequentially outputs the second transmit control signal to the second transmit control line EL2.

[0076] In the data driving region (DDA), a data driver 530 may be provided. The data driver 530 may include a plurality of data transistors, and the plurality of data transistors may be formed via a semiconductor process and may be formed on a semiconductor substrate SSUB (e.g., see...). Figure 10 For example, multiple data transistors can be formed using CMOS.

[0077] The data driver 530 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 610. The data driver 530 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. Thus, sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 510, and the data voltage can be applied to the selected sub-pixels SP1, SP2, and SP3.

[0078] The pad area PDA includes multiple pads PD arranged on the first direction DR1. Each of the multiple pads PD can be exposed without being covered by the overlay and polarizer.

[0079] The heat dissipation layer 420 may overlap with the display panel 410 on a third direction DR3, which is the thickness direction of the display panel 410. The heat dissipation layer 420 may be disposed on one surface of the display panel 410, for example, on the rear surface. The heat dissipation layer 420 is used to dissipate heat generated in the display panel 410. The heat dissipation layer 420 may include a metal layer with high thermal conductivity, such as graphite, silver (Ag), copper (Cu), and aluminum (Al).

[0080] Circuit board 430 can be electrically connected to multiple pads PD in the pad area of ​​display panel 410 PDA using conductive adhesive components such as anisotropic conductive film. Circuit board 430 can be a flexible printed circuit board or flexible film made of flexible material. Although in Figure 4 The circuit board 430 is unfolded, but it can be bent. When the circuit board 430 is bent, one end of the circuit board 430 can be positioned on the rear surface of the display panel 410. One end of the circuit board 430 can be opposite to the opposite end of the circuit board 430 which is attached (e.g., adhered to) the pad area PDA of the display panel 410 using conductive adhesive components.

[0081] The timing control circuit 610 can receive digital video data DATA and timing signals from an external source (e.g., from outside the display device 10). The timing control circuit 610 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 410 in response to the timing signals. The timing control circuit 610 can output the scan timing control signal SCS to the scan driver 510 and the transmit timing control signal ECS to the transmit driver 520. The timing control circuit 610 can output the digital video data DATA and the data timing control signal DCS to the data driver 530.

[0082] The power supply circuit 450 can generate multiple panel drive voltages in response to an external power supply voltage. For example, the power supply circuit 450 can generate a first power supply voltage VSS, a second power supply voltage VDD, and a third power supply voltage VINT to apply to the display panel 410.

[0083] Each of the timing control circuit 610 and the power supply circuit 450 can be implemented as an integrated circuit (IC) and attached to the surface of the circuit board 430. Scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS from the timing control circuit 610 can be provided to the display panel 410 via the circuit board 430. The first power supply voltage VSS, the second power supply voltage VDD, and the third power supply voltage VINT of the power supply circuit 450 can be provided to the display panel 410 via the circuit board 430.

[0084] It should be noted that, with Figure 5 The comparative examples shown are different, according to Figure 6 In some embodiments shown, the non-display area NDA of the display panel 410 may not include the scan drive area SDA. For example, the above reference Figure 5 The scan driver 510 and emitter driver 520 of the described scan driving area SDA can be disposed in the display area DAA. Multiple scan transistors and multiple light-emitting transistors can be formed by CMOS, and they can be configured with multiple pixel transistors T1, T2, T3, T4, T5, and T6 (see, for example, [reference needed]). Figure 8 (Adjacent)

[0085] and Figure 5 Compared to the comparative examples shown, according to Figure 6 The display panel 410 of the embodiment shown can reduce the non-display area NDA. Therefore, the display panel 410 according to some embodiments can reduce the border area (or dead zone area) where no image is displayed. For example, according to... Figure 5 In the comparative example shown, the scan driver 510 and the transmit driver 520 are disposed in the scan drive area SDA outside the display area DAA; however, according to Figure 6 In the embodiment shown, the scan driving area SDA is removed, and therefore the non-display area NDA can be reduced.

[0086] Figure 8 This is an equivalent circuit diagram of the first sub-pixel according to some exemplary embodiments of this disclosure.

[0087] refer to Figure 8The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emit control line EL1, the second emit control line EL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to a first power supply voltage line VSL that is applied with a first power supply voltage VSS equal to a low level voltage, a second power supply voltage line VDL that is applied with a second power supply voltage VDD equal to a high level voltage, and a third power supply voltage line VIL that is applied with a third power supply voltage VINT equal to the initialization voltage. In other words, the first power supply voltage line VSL can be a low-level voltage line, the second power supply voltage line VDL can be a high-level voltage line, and the third power supply voltage line VIL can be an initialization voltage line. The first power supply voltage VSS can be lower than the third power supply voltage VINT. The second power supply voltage VDD can be higher than the third power supply voltage VINT.

[0088] The first sub-pixel SP1 includes a light-emitting element LE and a pixel driving circuit PC connected to the light-emitting element LE. The pixel driving circuit PC includes multiple transistors T1, T2, T3, T4, T5 and T6, a first capacitor C1 and a second capacitor C2.

[0089] The light-emitting element LE emits light according to the driving current Ids flowing in the channel of the first transistor T1. The amount of light emitted from the light-emitting element LE can be proportional to the driving current Ids. The light-emitting element LE can be disposed between the fourth transistor T4 and the first power supply voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and its second electrode can be connected to the first power supply voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode (or pixel electrode), and the second electrode of the light-emitting element LE can be a cathode electrode (or common electrode). The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode. However, it should be understood that this disclosure is not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In such examples, the light-emitting element LE can be a micro light-emitting diode.

[0090] The first transistor T1 may be a drive transistor for controlling the source-drain current Ids (also called "drive current") flowing between the source and drain electrodes according to the voltage applied to the gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to the drain electrode of a sixth transistor T6, and a drain electrode connected to a second node N2.

[0091] A second transistor T2 can be disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on (e.g., activated) by a write scan signal from the write scan line GWL, and connects one electrode of the first capacitor C1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0092] A third transistor T3 can be connected between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal from the control scan line GCL, and connects the first node N1 to the second node N2. Therefore, the gate and source electrodes of the first transistor T1 are connected to each other, and thus the first transistor T1 can operate like a diode when the control scan signal is applied. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0093] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emitter control signal on the first emitter control line EL1, and connects the second node N2 to the third node N3. Therefore, the drive current Ids of the first transistor T1 can be provided to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0094] A fifth transistor T5 can be disposed between the third node N3 and the third power supply voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line EBL and connects the third node N3 to the third power supply voltage line VIL. Therefore, the third power supply voltage VINT of the third power supply voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third power supply voltage line VIL.

[0095] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second power supply voltage line VDL. The sixth transistor T6 is turned on by a second emitter control signal on the second emitter control line EL2, and connects the source electrode of the first transistor T1 to the second power supply voltage line VDL. Therefore, the second power supply voltage VDD of the second power supply voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second power supply voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0096] A first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes a first electrode connected to the drain electrode of the second transistor T2 and a second electrode connected to the first node N1.

[0097] A second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second power supply voltage line VDL. The second capacitor C2 includes a first electrode connected to the gate electrode of the first transistor T1 and a second electrode connected to the second power supply voltage line VDL.

[0098] The first node N1 is the contact point where the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the second electrode of the first capacitor C1, and the first electrode of the second capacitor C2 intersect. The second node N2 is the contact point where the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4 intersect. The third node N3 is the contact point where the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE intersect.

[0099] Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be, but is not limited to, a p-type MOSFET. For example, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be an n-type MOSFET. In some examples, some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be p-type MOSFETs, and the remaining transistors can be n-type MOSFETs.

[0100] Despite Figure 8In the example shown, the first sub-pixel SP1 includes six transistors T1, T2, T3, T4, T5, and T6, and two capacitors C1 and C2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 8 The circuit diagram shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 8 Those shown in the image.

[0101] Furthermore, the equivalent circuit diagrams for the second sub-pixel SP2 and the third sub-pixel SP3 can be referenced above. Figure 8 The equivalent circuit diagram of the first sub-pixel SP1 described is the same or substantially the same, and therefore, for the sake of brevity, its description is not repeated.

[0102] Figure 9 This is an equivalent circuit diagram of a scan driver 510 according to some embodiments of the present disclosure.

[0103] refer to Figure 9 The scan driver 510 outputs a scan signal in pulse form by outputting a high-level voltage or a low-level voltage according to the potentials of the Q node and QB node. For this purpose, the scan driver 510 includes multiple scan transistors.

[0104] like Figure 9 As shown, the multiple scanning transistors may include, but are not limited to, the first scanning transistor M1, the second scanning transistor M2, the third scanning transistor M3, the fourth scanning transistor M4, the fifth scanning transistor M5, the sixth scanning transistor M6, the seventh scanning transistor M7, the eighth scanning transistor M8, the ninth scanning transistor M9, and the tenth scanning transistor M10.

[0105] The first scanning transistor M1 receives the carry signal Carry[n-1] through the ninth scanning transistor M9 or the tenth scanning transistor M10, and charges the Q node Q in response to the carry signal Carry[n-1]. In some examples, the first scanning transistor M1 and the ninth scanning transistor M9 can be p-type MOSFETs, while the tenth scanning transistor M10 can be an n-type MOSFET. The conduction of the first scanning transistor M1 is controlled by the first clock signal CLK1. The conduction of the ninth scanning transistor M9 and the tenth scanning transistor M10 is controlled by the FLM signal FLM.

[0106] The second scanning transistor M2 and the third scanning transistor M3 charge the QB node QB according to the voltage level of the Q node Q. The second scanning transistor M2 can be a p-type MOSFET, and the third scanning transistor M3 can be an n-type MOSFET. A pulsed clock signal CLK2 can be input to the drain electrode of the third scanning transistor M3.

[0107] When node Q is charged to a high level, the fourth scan transistor M4, the fifth scan transistor M5, the sixth scan transistor M6, the seventh scan transistor M7, and the eighth scan transistor M8 output a high-level voltage VGH at the output terminal of the scan driver 510 as the scan signal SCAN[N]. Similarly, when node QB is charged to a high level, they output a low-level voltage VGL at the output terminal of the scan driver 510 as the scan signal SCAN[N]. The fourth scan transistor M4 and the seventh scan transistor M7 are p-type MOSFETs, while the fifth scan transistor M5, the sixth scan transistor M6, and the eighth scan transistor M8 can be n-type MOSFETs. The seventh scan transistor M7 and the eighth scan transistor M8 receive the carry signal Carry[N].

[0108] As described above, the scan driver 510 includes a plurality of scan transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10, and some of the scan transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10 may be n-type MOSFETs, while others may be p-type MOSFETs. For example, the first scan transistor M1, the second scan transistor M2, the fourth scan transistor M4, the seventh scan transistor M7, and the ninth scan transistor M9 may be p-type MOSFETs, and these transistors may be referred to as the first transistor group. For example, the third scan transistor M3, the fifth scan transistor M5, the sixth scan transistor M6, the eighth scan transistor M8, and the tenth scan transistor M10 may be n-type MOSFETs, and these transistors may be referred to as the second transistor group. However, embodiments of this disclosure are not limited thereto. For example, the transistors in the first transistor group may be n-type MOSFETs, and the transistors in the second transistor group may be p-type MOSFETs (assuming the corresponding gate control signals are inverted).

[0109] According to some embodiments, some of the multiple scan transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10 of the scan driver 510 may be disposed in a pixel transistor PTR (see [link to relevant documentation]). Figure 10 The display area of ​​the DAA is in the well region. For example, the first well region NW doped with a first type of impurity (see...). Figure 11 ) and the second well region PW doped with type II impurities (see Figure 11 The display area DAA of the display panel 410 is located in the CMOS layer. A first transistor group including multiple pixel transistors in the pixel driving circuit and the scan driver 510 is disposed in the first well region NW, and a second transistor group of the scan driver 510 is disposed in the second well region PW. The CMOS layer may refer to the semiconductor backplane SBP (see [reference]). Figure 10 (This will be referenced later) Figure 10 This will be described.

[0110] Figure 10 This is a cross-sectional view showing an example of a display panel according to some embodiments of the present disclosure.

[0111] refer to Figure 10 The display panel 410 includes a semiconductor backplane (SBP), an emissive material backplane (EBP), an emissive material layer (EML), an encapsulation layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizer.

[0112] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) having multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be a reference. Figure 8 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are described.

[0113] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions can be located on the upper surface of the semiconductor substrate SSUB. The multiple well regions can include regions doped with the first type of impurity and regions doped with a second type of impurity. The second type of impurity can be different from the first type of impurity. For example, when the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. In some examples, when the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0114] Each of the well regions includes a source region SA associated with the source electrode of the pixel transistor PTR, a drain region DA associated with its drain electrode, and a channel region CH between the source region SA and the drain region DA.

[0115] Each of the source region SA and drain region DA may be doped with type I impurities. The gate electrode GE of the pixel transistor PTR may overlap with the well region on the third-direction DR3. The channel region CH may overlap with the gate electrode GE on the third-direction DR3. The source region SA may be located on one side of the gate electrode GE, and the drain region DA may be located on the opposite side of the gate electrode GE.

[0116] Each of the plurality of well regions may further include a first low-concentration impurity region disposed between the channel region CH and the source region SA, and a second low-concentration impurity region disposed between the channel region CH and the drain region DA. The first low-concentration impurity region may have a lower impurity concentration than the source region SA. The second low-concentration impurity region may have a lower impurity concentration than the drain region DA. The distance between the source region SA and the drain region DA may be increased by the first low-concentration impurity region and the second low-concentration impurity region. Therefore, the length of the channel region CH of each of the pixel transistors PTRs can be increased, and thus punch-through and hot carrier phenomena caused by short channels can be prevented or substantially reduced.

[0117] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be made of (but is not limited to) silicon carbide (SiCN) or based on silicon oxide (SiO2). x Inorganic membrane formation.

[0118] The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be made of silicon oxide (SiO2) x The inorganic membrane is formed, but the embodiments of this disclosure are not limited thereto, and any suitable material can be used.

[0119] Multiple contact terminals (CTEs) can be disposed on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through holes passing through the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The contact terminals (CTEs) can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or alloys thereof.

[0120] A third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the contact terminals (CTEs). The upper surface of each of the contact terminals (CTEs) may not be covered by the third semiconductor insulating film (SINS3) and can be exposed. The third semiconductor insulating film (SINS3) can be made of silicon oxide (SiO2). x The inorganic membrane is formed, but the embodiments of this disclosure are not limited thereto.

[0121] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate (such as polyimide). In such examples, the thin-film transistor can be disposed on either the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, while the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0122] The emissive material backplane (EBP) includes first metal layers ML1 to eighth metal layers ML8, reflective metal layers RL1 to RL4, multiple vias VA1 to VA10, and a stepped layer STPL. Furthermore, the EBP includes multiple interlayer insulating films INS1 to INS10 disposed between the first metal layers ML1 to the sixth metal layers ML6.

[0123] The first metal layers ML1 to the eighth metal layers ML8 are used to achieve this by connecting multiple contact terminals CTE exposed from the semiconductor backplane SBP. Figure 8 The circuitry for the first sub-pixel SP1 is shown. Specifically, the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 are formed only in the semiconductor backplane SBP, and the connections between the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6, as well as the first capacitor C1 and the second capacitor C2, are formed through the first metal layer ML1 to the eighth metal layer ML8. Furthermore, the connections between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE are also formed through the first metal layer ML1 to the eighth metal layer ML8.

[0124] A first interlayer insulating film INS1 may be disposed on the semiconductor backplane SBP. Each of the first vias VA1 may pass through the first interlayer insulating film INS1 and may be connected to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first metal layers ML1 may be disposed on the first interlayer insulating film INS1 and may be connected to the first via VA1.

[0125] A second interlayer insulating film INS2 may be disposed on the first interlayer insulating film INS1 and the first metal layer ML1. Each of the second vias VA2 may pass through the second interlayer insulating film INS2 to connect to the exposed first metal layer ML1. Each of the second metal layers ML2 may be disposed on the second interlayer insulating film INS2 and may connect to the second via VA2.

[0126] A third interlayer insulating film INS3 may be disposed on the second interlayer insulating film INS2 and the second metal layer ML2. Each of the third vias VA3 may pass through the third interlayer insulating film INS3 to connect to the exposed second metal layer ML2. Each of the third metal layers ML3 may be disposed on the third interlayer insulating film INS3 and may be connected to the third via VA3.

[0127] A fourth interlayer insulating film INS4 may be disposed on the third interlayer insulating film INS3 and the third metal layer ML3. Each of the fourth vias VA4 may pass through the fourth interlayer insulating film INS4 to connect to the exposed third metal layer ML3. Each of the fourth metal layers ML4 may be disposed on the fourth interlayer insulating film INS4 and may connect to the fourth via VA4.

[0128] A fifth interlayer insulating film INS5 may be disposed on the fourth interlayer insulating film INS4 and the fourth metal layer ML4. Each of the fifth vias VA5 may pass through the fifth interlayer insulating film INS5 to connect to the exposed fourth metal layer ML4. Each of the fifth metal layers ML5 may be disposed on the fifth interlayer insulating film INS5 and may connect to the fifth via VA5.

[0129] A sixth interlayer insulating film INS6 may be disposed on the fifth interlayer insulating film INS5 and the fifth metal layer ML5. Each of the sixth vias VA6 may pass through the sixth interlayer insulating film INS6 to connect to the exposed fifth metal layer ML5. Each of the sixth metal layers ML6 may be disposed on the sixth interlayer insulating film INS6 and may connect to the sixth via VA6.

[0130] A seventh interlayer insulating film INS7 can be disposed on the sixth interlayer insulating film INS6 and the sixth metal layer ML6. Each of the seventh vias VA7 can pass through the seventh interlayer insulating film INS7 to connect to the exposed sixth metal layer ML6. Each of the seventh metal layers ML7 can be disposed on the seventh interlayer insulating film INS7 and can be connected to the seventh via VA7.

[0131] An eighth interlayer insulating film INS8 may be disposed on the seventh interlayer insulating film INS7 and the seventh metal layer ML7. Each of the eighth vias VA8 may pass through the eighth interlayer insulating film INS8 to connect to the exposed seventh metal layer ML7. Each of the eighth metal layers ML8 may be disposed on the eighth interlayer insulating film INS8 and may connect to the eighth via VA8.

[0132] The first metal layers ML1 to ML8 and the first through-holes VA1 to VA8 can be made of the same or substantially the same material. The first metal layers ML1 to ML8 and the first through-holes VA1 to VA8 can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or alloys thereof. The first through-holes VA1 to VA8 can be made of the same or substantially the same material. The first interlayer insulating film INS1 to the eighth interlayer insulating film INS8 can be made of silicon oxide (SiO2) based material. xInorganic membranes, etc., are formed, but the embodiments described in this specification are not limited to this.

[0133] The ninth interlayer insulating film INS9 can be disposed on the eighth interlayer insulating film INS8 and the eighth metal layer ML8. The ninth interlayer insulating film INS9 can be made of silicon oxide (SiO2). x Inorganic membranes, etc., are formed, but the embodiments disclosed herein are not limited thereto.

[0134] Each of the ninth through-holes VA9 can pass through the ninth interlayer insulating film INS9 to connect to the exposed eighth metal layer ML8. The ninth through-holes VA9 can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or alloys thereof.

[0135] The first reflective electrode RL1 can be disposed on the ninth interlayer insulating film INS9 and can be connected to the ninth through hole VA9. The first reflective electrode RL1 can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) or alloys thereof.

[0136] The second reflective electrode RL2 can be disposed on the first reflective electrode RL1. The second reflective electrode RL2 can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or alloys thereof. For example, the second reflective electrode RL2 can be titanium nitride (TiN).

[0137] In the first sub-pixel SP1, a stepped layer STPL can be disposed on the second reflective electrode RL2. In each of the second sub-pixels SP2 and the third sub-pixel SP3, a stepped layer STPL may not be disposed. The thickness of the stepped layer STPL can be determined based on the wavelength of the first color light and the distance from the emitting material layer EML to the fourth reflective electrode RL4, such that the first color light emitted from the intermediate layer IL of the first sub-pixel SP1 is advantageously reflected. The stepped layer STPL can be made of (but is not limited to) silicon carbide (SiCN) or based on silicon oxide (SiO2). x Inorganic membrane formation.

[0138] In the first sub-pixel SP1, the third reflective electrode RL3 can be disposed on the second reflective electrode RL2 and the stepped layer STPL. In the second sub-pixel SP2 and the third sub-pixel SP3, the third reflective electrode RL3 can be disposed on the second reflective electrode RL2. The third reflective electrode RL3 can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or alloys thereof.

[0139] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 can be removed.

[0140] A fourth reflective electrode RL4 can be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 can reflect light from the intermediate layer IL of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The fourth reflective electrode RL4 can include a metal with high reflectivity to facilitate light reflection. The fourth reflective electrode RL4 can be made of (but is not limited to) aluminum (Al), a stack of aluminum and titanium (Ti / Al / Ti), a stack of aluminum and ITO (ITO / Al / ITO), an APC alloy as an alloy of silver (Ag), palladium (Pd), and copper (Cu), or a stack of APC alloy and ITO (ITO / APC / ITO), etc.

[0141] The tenth interlayer insulating film INS10 can be disposed on the ninth interlayer insulating film INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating film INS10 can be made of silicon oxide (SiO2) based material. x The inorganic membrane is formed, but the embodiments of this disclosure are not limited thereto.

[0142] Each of the tenth vias VA10 can pass through the tenth interlayer insulating film INS10 to connect to the exposed fourth reflective electrode RL4. The tenth vias VA10 can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or alloys thereof. Due to the stepped layer STPL, the thickness of the tenth via VA10 in the first sub-pixel SP1 can be less than the thickness of the tenth via VA10 in each of the second sub-pixels SP2 and the third sub-pixel SP3.

[0143] The emitting material layer (EML) can be disposed on the emitting material backplane (EBP). The emitting material layer (EML) may include a light-emitting element (LE) (see [link]). Figure 8 The light-emitting element (LE) includes a first electrode AND, an intermediate layer IL, and a second electrode CAT.

[0144] The first electrode AND of each of the light-emitting elements LE can be disposed on the tenth interlayer insulating film INS10 and can be connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the first reflective electrodes RL1 to the fourth reflective electrodes RL4, the first via VA1 to the ninth via VA9, the first metal layer ML1 to the eighth metal layer ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or alloys thereof. For example, the first electrode AND of each of the light-emitting elements LE can be titanium nitride (TiN).

[0145] A pixel-defining film (PDL) can be partially disposed on the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL is used to separate the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3.

[0146] The first emission region EA1 can be defined as a region within the first sub-pixel SP1, wherein the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked to emit light. The second emission region EA2 can be defined as a region within the second sub-pixel SP2, wherein the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked to emit light. The third emission region EA3 can be defined as a region within the third sub-pixel SP3, wherein the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked to emit light.

[0147] The pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be disposed on the edge of the first electrode AND of each of the light-emitting elements (LEs), the second pixel-defining film (PDL2) may be disposed on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be disposed on the second pixel-defining film (PDL2). The first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may be made of silicon oxide (SiO2). x The inorganic membrane is formed, but the embodiments of this disclosure are not limited thereto.

[0148] The intermediate layer IL can include a first intermediate layer IL1, a second intermediate layer IL2, and a third intermediate layer IL3.

[0149] The intermediate layer IL can have a columnar structure comprising multiple intermediate layers IL1, IL2, and IL3 that emit different colors of light. For example, the intermediate layer IL can include a first intermediate layer IL1 that emits light of a first color, a second intermediate layer IL2 that emits light of a second color, and a third intermediate layer IL3 that emits light of a third color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 can be stacked sequentially on top of each other.

[0150] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic emission layer emitting light of a first color, and a first electron transport layer are stacked sequentially on top of each other. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic emission layer emitting light of a second color, and a second electron transport layer are stacked sequentially on top of each other. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic emission layer emitting light of a third color, and a third electron transport layer are stacked sequentially on top of each other.

[0151] The number of intermediate layers IL1, IL2, and IL3 that emit different lights is not limited to... Figure 10 The quantities shown are as indicated. For example, the intermediate layer IL may include two intermediate layers. In such an example, one of the two intermediate layers is substantially identical to the first intermediate layer IL1, and the other may include a second hole transport layer, a second organic emission layer, a third organic emission layer, and a second electron transport layer. In such an example, a charge generation layer may be disposed between the two intermediate layers to provide electrons to one intermediate layer and charge to the other intermediate layer.

[0152] Furthermore, although the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 are all set in Figure 10 The first emission region EA1, the second emission region EA2, and the third emission region EA3 are used in the optical layer OPL, but the embodiments disclosed herein are not limited to this. For example, the first intermediate layer IL1 may be disposed in the first emission region EA1, but not in the second emission region EA2 and the third emission region EA3. Furthermore, the second intermediate layer IL2 may be disposed in the second emission region EA2, but not in the first emission region EA1 and the third emission region EA3. Furthermore, the third intermediate layer IL3 may be disposed in the third emission region EA3, but not in the first emission region EA1 and the second emission region EA2. In such examples, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be removed.

[0153] The second electrode CAT can be disposed on the third intermediate layer IL3. The second electrode CAT can be disposed on the third intermediate layer IL3 in each of the multiple trenches. The second electrode CAT can be formed of a transparent conductive material (TCP) that can transmit light (such as ITO and IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), alloys of magnesium (Mg) and silver (Ag), etc.). When the second electrode CAT is formed of a semi-transmissive conductive material, the light extraction efficiency can be improved by using a microcavity in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0154] An encapsulation layer TFE can be disposed on the emissive material layer EML. The encapsulation layer TFE may include one or more inorganic encapsulation films TFE1 and TFE3 to prevent or substantially reduce the penetration of oxygen or moisture into the emissive material layer EML. Furthermore, the encapsulation layer TFE may include at least one organic encapsulation film TFE2 to protect the emissive material layer EML from particles such as dust. For example, the encapsulation layer TFE may include a first inorganic encapsulation film TFE1, an organic encapsulation film TFE2, and a second inorganic encapsulation film TFE3.

[0155] A first inorganic encapsulation film TFE1 can be disposed on the second electrode CAT, an organic encapsulation film TFE2 can be disposed on the first inorganic encapsulation film TFE1, and a second inorganic encapsulation film TFE3 can be disposed on the organic encapsulation film TFE2. The first inorganic encapsulation film TFE1 and the second inorganic encapsulation film TFE3 can be composed of multiple layers, wherein the silicon nitride layer (SiN) is included. x ), silicon oxynitride (SiON), silicon oxide (SiO) layer x ), titanium oxide layer (TiO) x ) and aluminum oxide layer (AlO) x One or more inorganic layers in the encapsulation film TFE2 are stacked alternately on top of each other. The organic encapsulation film TFE2 can be a monomer. In some examples, the organic encapsulation film TFE2 can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0156] The adhesive layer (ADL) can adhere the encapsulation layer (TFE) to the optical layer (OPL). The adhesive layer (ADL) can be a double-sided adhesive component. Alternatively, the adhesive layer (ADL) can be a transparent adhesive component, such as a transparent adhesive or a transparent adhesive resin.

[0157] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL.

[0158] The first color filter CF1 can be aligned with the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of a first color, for example, light in the blue wavelength range. The blue wavelength range can be from about 370 nm to about 460 nm. Therefore, the first color filter CF1 can transmit light of the first color emitted from the first emission region EA1.

[0159] The second color filter CF2 can be aligned with the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color, for example, light in the green wavelength range. The green wavelength range can be from approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emission region EA2.

[0160] The third color filter CF3 can be aligned with the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of a third color, such as light in the red wavelength range. The red wavelength range can be from approximately 600 nm to approximately 750 nm. Therefore, the third color filter CF3 can transmit light of a third color emitted from the third emission region EA3.

[0161] Lenses LNS can be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the lenses LNS can be a structure for increasing the proportion of light guided to the front side of the display device 10. Each of the lenses LNS can have an upwardly convex cross-sectional shape.

[0162] A filler layer (FIL) can be disposed on multiple lens lenses (LNS). The filler layer FIL can have a set or predetermined refractive index, such that light travels in the third-direction DR3 at the interface between the multiple lens lenses (LNS) and the filler layer FIL. Furthermore, the filler layer FIL can be a planarization layer. The filler layer FIL can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0163] A capping layer CVL can be disposed on a filler layer FIL. The capping layer CVL can be a glass substrate or a polymeric resin such as a resin. If the capping layer CVL is a glass substrate, it can be attached to the filler layer FIL. In such examples, the filler layer FIL can adhere the capping layer CVL. If the capping layer CVL is a glass substrate, it can be used as an encapsulation substrate. If the capping layer CVL is a polymeric resin such as a resin, it can be applied directly to the filler layer FIL.

[0164] Polarizers can be disposed on the surface of the CVL cover layer. Polarizers can be structures used to prevent or substantially reduce visibility degradation due to reflection of external light. Polarizers can include linear polarizers and retardation films. For example, the retardation film can be a λ / 4 plate (quarter-wave plate), but embodiments of this disclosure are not limited thereto. Polarizers can be removed if visibility is sufficiently improved by the first color filter CF1, the second color filter CF2, and the third color filter CF3 without being affected by reflection of external light.

[0165] Figure 11 This is a view showing the layout of the first sub-pixel according to some embodiments of this disclosure.

[0166] refer to Figure 11 The first well region NW, doped with a first type of impurity, and the second well region PW, doped with a second type of impurity, are located in the display area DAA of the display panel 410.

[0167] In the first well region NW, a plurality of pixel transistors (e.g., included in the pixel driving circuit PC) are disposed. Figure 8 Transistors T1 to T6 in the transistors) and the first group of transistors in the scan driver 510 (e.g., Figure 9 Transistors M1, M2, M4, M7, and M9 in the transistors. For example, the first well region NW includes a first sub-region NW1 and a second sub-region NW2, and multiple pixel transistors (e.g., those included in the pixel driving circuit PC) are disposed in the first sub-region NW1. Figure 8 Transistors T1 to T6 in the first group of transistors of the scan driver 510 are provided in the second sub-region NW2 (e.g., transistors T1 to T6 in the second group of transistors). Figure 9 (Transistors M1, M2, M4, M7, and M9 in the transistor).

[0168] The second transistor group of the scan driver 510 (e.g., Figure 9 Transistors M3, M5, M6, M8, and M10 are disposed in the second well region PW. The second well region PW can be arranged parallel to the second sub-region NW2 of the first well region NW.

[0169] As referenced above Figure 8 As described, the pixel transistor disposed in the first well region NW (e.g., Figure 8 The transistors (T1 to T6) include p-type MOSFETs.

[0170] The first transistor group of the scan driver 510 (e.g., Figure 9 Transistors M1, M2, M4, M7, and M9 in the transistor group include p-type MOSFETs, and the second transistor group of the scan driver 510 (e.g., Figure 9Transistors M3, M5, M6, M8, and M10 in the diagram include n-type MOSFETs. For example, a p-type MOSFET, such as the second scan transistor M2, can be disposed in a second sub-region NW2 of the first well region NW. Furthermore, an n-type MOSFET, such as the third scan transistor M3, can be disposed in the second well region PW.

[0171] The first type of impurity is an n-type impurity, and the second type of impurity is a p-type impurity.

[0172] In some embodiments, the first well region NW may have an L-shape, and the second well region PW may be located in the space defined by the two extensions of the L-shaped first well region NW.

[0173] According to some embodiments of this disclosure, a first well region NW and a second well region PW can be arranged adjacent to each other to form a double-well region, and the double-well regions can be arranged in a matrix in the display area DAA. That is, a first well region NW and a second well region PW can be arranged adjacent to each other and regularly. In other words, multiple double-well regions, including the double-well region, are arranged in the display area DAA in the form of a repeating matrix pattern.

[0174] Figure 12 This is a view showing the layout of pixel groups according to some embodiments of this disclosure.

[0175] refer to Figure 12 Four sub-pixels SP1, SP2, and SP3, arranged in a 2×2 matrix, form a pixel group GR, where "×" represents the multiplication sign. For example, the first sub-pixel SP1 can be placed in the first row and first column of the 2×2 matrix, the third sub-pixel SP3 can be placed in the first row and second column of the 2×2 matrix, another third sub-pixel SP3 can be placed in the second row and first column of the 2×2 matrix, and the second sub-pixel SP2 can be placed in the second row and second column of the 2×2 matrix. That is, in the 2×2 matrix, the first sub-pixel SP1 and the second sub-pixel SP2 can face each other diagonally, and the two third sub-pixels SP3 can face each other diagonally. However, Figure 12 The layout of pixel group GR shown is merely an example, and this disclosure is not limited thereto.

[0176] Thus, a first well region NW and a second well region PW correspond to four sub-pixels SP1, SP2, and SP3 arranged in a 2×2 matrix (e.g., located within four sub-pixels SP1, SP2, and SP3 arranged in a 2×2 matrix). In each pixel group GR, a first well region NW can be arranged around a second well region PW.

[0177] exist Figure 12In the middle, the dashed lines VL and HL divide and arrange the four sub-pixels SP1, SP2 and SP3 into a 2×2 matrix.

[0178] according to Figure 12 In one embodiment, the first well region NW is doped with an n-type impurity, and the second well region PW is doped with a p-type impurity. However, it should be understood that this disclosure is not limited thereto. For example, the pixel transistor includes an n-type MOSFET. In such examples, the first transistor group includes an n-type MOSFET, and the second transistor group includes a p-type MOSFET. Furthermore, the first type of impurity is a p-type impurity, and the second type of impurity is an n-type impurity.

[0179] Figure 13 This is an equivalent circuit diagram of the first sub-pixel according to some embodiments of the present disclosure. Figure 14 This is a view showing the layout of pixel groups according to some embodiments of this disclosure.

[0180] Figure 13 Implementation methods and Figure 8 The difference in the implementation is that the second transistor T2 and the third transistor T3 are n-type MOSFETs. For example, refer to... Figure 13 According to some embodiments, the first sub-pixel SP1 includes a plurality of pixel transistors T1 to T6. Some of the pixel transistors T1 to T6 may be n-type MOSFETs, while the others may be p-type MOSFETs. Figure 13 The equivalent circuit diagram shown is merely an example, and this disclosure is not limited thereto.

[0181] refer to Figure 13 and Figure 14 Four sub-pixels SP1, SP2, and SP3, arranged in a 2×2 matrix, form pixel group GR. For example, the first sub-pixel SP1 can be set in the first row and the first column, the third sub-pixel SP3 can be set in the first row and the second column, and the second row and the first column, and the second sub-pixel SP2 can be set in the second row and the second column. Figure 12 The layout of pixel group GR shown is merely an example, and this disclosure is not limited thereto.

[0182] Thus, for reference Figure 14 A pair of first well regions NW and a second well region PW correspond to four sub-pixels SP1, SP2, and SP3 arranged in a 2×2 matrix (e.g., located within four sub-pixels SP1, SP2, and SP3 arranged in a 2×2 matrix). For example, in a 2×2 matrix, the first sub-pixels SP1 and SP2 may face each other diagonally, while the two third sub-pixels SP3 may face each other diagonally. A second well region PW is disposed between the pair of first well regions NW.

[0183] In some implementations, each of the first well regions NW can be U-shaped and face inward toward the center of the 2×2 matrix, and the second well region PW can be cross-shaped and located in the space defined by the inwardly facing U-shaped first well regions NW.

[0184] exist Figure 14 In the middle, the dashed lines VL and HL divide and arrange the four sub-pixels into a 2×2 matrix.

[0185] according to Figure 14 In one embodiment, the first well region NW is doped with an n-type impurity, and the second well region PW is doped with a p-type impurity. However, it should be understood that this disclosure is not limited thereto. For example, the pixel transistor includes an n-type MOSFET. In such examples, the first transistor group includes an n-type MOSFET, and the second transistor group includes a p-type MOSFET. Furthermore, the first type of impurity is a p-type impurity, and the second type of impurity is an n-type impurity.

[0186] Although the scan transistor of the scan driver 510 shares a well region with the pixel transistor in the above description, the plurality of light-emitting transistors of the emitter driver 520 may also share a well region with the pixel transistor. For example, a first well region NW doped with a first type of impurity and a second well region PW doped with a second type of impurity are located in the CMOS layer of the display area DAA of the display panel 410. The plurality of pixel transistors T1 to T6 in the pixel driving circuit PC and the first transistor group of the emitter driver 520 are disposed in the first well region NW, and the second transistor group of the emitter driver 520 is disposed in the second well region PW. The first transistor group includes a p-type MOSFET, and the second transistor group includes an n-type MOSFET.

[0187] In the display device and mobile electronic device according to the embodiments, the area of ​​the display screen can be expanded by reducing the non-display area.

[0188] According to the display device and mobile electronic device according to the embodiments, manufacturing costs can be reduced by decreasing the size of each unit (e.g., net die) in the wafer in which the semiconductor substrate is produced.

[0189] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or segment from another element, component, region, layer, or segment. Therefore, without departing from the scope of this disclosure, the first element, first component, first region, first layer, or first segment discussed below may be referred to as a second element, second component, second region, second layer, or second segment.

[0190] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit this disclosure. As used herein, the singular forms “a” and “an” are intended to also include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “include,” “inlcuding,” “comprises,” “comprising,” “has,” “have,” and “having” designate the presence of the described feature, integral, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0191] As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items. For example, the expression “A and / or B” means A, B, or A and B. When following an element in a list, expressions such as “one or more of…” and “at least one of…” modify the elements of the entire list without modifying any individual element in the list. For example, the expressions “one or more of A, B, and C,” “at least one of A, B, and C,” and “at least one selected from the group consisting of A, B, and C” mean only A, only B, only C, both A and B, both A and C, both B and C, or all of A, B, and C.

[0192] Furthermore, when describing embodiments of this disclosure, the use of "may" refers to "one or more embodiments of this disclosure." Additionally, the term "exemplary" is intended to indicate an example or illustration.

[0193] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “linked to,” or “adjacent to” another element or layer, it can be directly on, directly connected to, directly linked to, or directly adjacent to the other element or layer, or one or more intermediary elements or layers may exist. When an element or layer is referred to as being “directly” on, directly connected to, directly linked to, “in contact with,” “in direct contact with,” or “directly adjacent to” another element or layer, no intermediary element or layer exists.

[0194] As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than terms of degree, and are intended to allow for inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art. Furthermore, if the term “substantially” is used in combination with a feature that can be expressed numerically, the term “substantially” indicates a range of + / - 5% of the value centered on that value. Additionally, the specific quantities or ranges set forth in this written description or claims may also include inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art.

[0195] As used herein, the terms “use,” “using,” and “used” can be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

[0196] When one or more implementation methods can be carried out differently, a particular process sequence may be performed differently from the stated sequence. For example, (i) the operation of the disclosed process is merely an example and may involve various additional operations not explicitly covered, and (ii) the timing order of operations may be changed.

[0197] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the relevant field and / or in the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0198] Furthermore, any numerical range described herein is intended to include all subranges with the same numerical precision contained within the stated range. For example, the range “1.0 to 10.0” is intended to include all subranges between (and inclusive of) the minimum value of 1.0 and the maximum value of 10.0, i.e., a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly describe any subranges contained within the range expressly described herein. All such ranges are intended to be inherently described in this specification.

[0199] The display devices and / or any other related devices or components described herein according to embodiments of this disclosure can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a suitable combination of software, firmware, and hardware. For example, various components of the display device can be formed on a single integrated circuit (IC) chip or on separate IC chips. Additionally, various components of the display device can be implemented on a flexible printed circuit film, a tape-on-a-chip (TCP), a printed circuit board (PCB), or formed on the same substrate. Furthermore, various components of the display device can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions, and interacting with other system components for performing the various functions described herein. The computer program instructions are stored in memory implemented in the computing device using standard storage devices, such as, for example, random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as, for example, CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that, without departing from the scope of the exemplary embodiments of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0200] It should be understood that the embodiments described herein are to be considered descriptive and not for limiting purposes. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the scope defined by the appended claims and their equivalents.

Claims

1. A display device, characterized in that, The display device includes: Pixel driving circuit, including multiple pixel transistors; A scan driver, comprising a first transistor group and a second transistor group; and The display panel includes a semiconductor substrate, a complementary metal-oxide-semiconductor layer on the semiconductor substrate, and an emissive material layer on the complementary metal-oxide-semiconductor layer. The complementary metal-oxide-semiconductor layer includes a first well region doped with a first type of impurity and a second well region doped with a second type of impurity. The first well region and the second well region are located in the display area of ​​the display panel. The plurality of pixel transistors and the first transistor group are located in the first well region, and the second transistor group is located in the second well region.

2. The display device according to claim 1, characterized in that, The plurality of pixel transistors include p-type MOSFETs, and The first transistor group includes a p-type MOSFET, and the second transistor group includes an n-type MOSFET.

3. The display device according to claim 2, characterized in that, The first type of impurity is an n-type impurity, and The second type of impurity is a p-type impurity.

4. The display device according to claim 1, characterized in that, The plurality of pixel transistors include n-type MOSFETs, and The first transistor group includes an n-type MOSFET, and the second transistor group includes a p-type MOSFET.

5. The display device according to claim 4, characterized in that, The first type of impurity is a p-type impurity, and The second type of impurity is an n-type impurity.

6. The display device according to claim 1, characterized in that, The first well region and the second well region are adjacent to each other to form a double-well region, and The multiple double-well regions, including the double-well region, are arranged in a matrix pattern in the display area.

7. The display device according to claim 1, wherein, The first well region and the second well region correspond to the four sub-pixels of the display panel arranged in a 2×2 matrix, and The first well region surrounds the second well region.

8. The display device according to claim 1, characterized in that, The first well region includes a pair of first well regions, the pair of first well regions and the second well region corresponding to four sub-pixels arranged in a 2×2 matrix on the display panel, and The second well region is located between the pair of first well regions.

9. A mobile electronic device, characterized in that, The mobile electronic device includes: The display panel includes a semiconductor substrate, a complementary metal-oxide-semiconductor layer on the semiconductor substrate, and an emissive material layer on the complementary metal-oxide-semiconductor layer. The complementary metal-oxide-semiconductor layer includes a first well region doped with a first type of impurity and a second well region doped with a second type of impurity. The first well region and the second well region are located in the display area of ​​the display panel. In this configuration, a plurality of pixel transistors of the pixel driving circuit and a first transistor group of the scan driver are located in the first well region, and a second transistor group of the scan driver is located in the second well region.

10. The mobile electronic device according to claim 9, characterized in that, The first well region and the second well region are adjacent to each other to form a double-well region, and The multiple double-well regions, including the double-well region, are arranged in a matrix pattern in the display area.

Images