Display panel and display device
By setting up an energy storage unit in the display panel and connecting it to the data signal line, the problem of uneven pixel illumination caused by unconnected data signal lines is solved, achieving a more uniform display effect.
Patent Information
- Application Number
- CN202520336816.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2026-01-23
- Estimated Expiration
- 2035-02-27
AI Technical Summary
In display products, a mismatch between the number of data signal lines and the number of sub-pixels can cause some data signal lines to be unconnected, affecting the voltage of other data signal lines and consequently affecting the normal emission of pixels, especially under low brightness conditions.
By incorporating energy storage units, such as capacitors, into the data signal lines and connecting them to a portion of the data signal lines, we can prevent unconnected data signal lines, reduce interference, and ensure the normal operation of the data signal lines.
It effectively prevents data signal lines from being disconnected, ensures that pixels emit light normally, improves display uniformity, and reduces uneven brightness.
Smart Images
Figure CN223829699U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of display technology, and in particular to a display panel and a display device. Background Technology
[0002] In display products, to reduce wiring density, a 1:k MUX technique is often used to reduce the number of source drive signal lines (1:k means one source drive signal line is connected to k data signal lines, where k is greater than 1). However, this setup can lead to a mismatch between the number of data signal lines and the number of pixels in some cases, resulting in some data signal lines being unconnected and affecting other data signal lines connected to the same source drive signal line. Utility Model Content
[0003] The purpose of this application is to provide a display panel and display device with good display uniformity.
[0004] This application discloses a display panel, which includes:
[0005] Several source signal lines are configured to provide source signals;
[0006] A plurality of data signal line groups, wherein each data signal line group includes a plurality of data signal lines, wherein the data signal lines in the same group are connected to the same source signal line, and the data signal lines in different groups are connected to different source signal lines; the data signal lines are configured to receive source signals and provide data signals according to the source signals.
[0007] Several sub-pixels, connected to the data signal line, are configured to receive the data signal and emit light according to the data signal;
[0008] Several energy storage units are connected to the data signal line and are configured to receive and store the data signal;
[0009] Some of the data signal lines are connected to the sub-pixel, and at least one of the other data signal lines is connected to the energy storage unit.
[0010] Optionally, the number of the plurality of source signal lines is n, the number of the plurality of data signal line groups is n, a group of the data signal line groups includes k data signal lines, and the plurality of sub-pixels are arranged along the first direction to form p columns of sub-pixels;
[0011] Among them, p root data signal lines are connected to p column sub-pixels, and n*kp root data signal lines are connected to a plurality of energy storage units; p < n*k, n*kp < k.
[0012] Optionally, the data signal lines connected to the energy storage unit by the n*kp roots are located at the edge of the display panel.
[0013] Optionally, of the n*kp data signal lines connected to the energy storage unit, (n*kp) / 2 lines are located on one side edge of the display panel, and the other (n*kp) / 2 lines are located on the opposite side edge of the display panel.
[0014] Optionally, k = 9, n*kp = 6; 3 of the 6 data signal lines connected to the energy storage unit are located on one side edge of the display panel, and the other 3 are located on the opposite side edge of the display panel.
[0015] Optionally, the display panel further includes:
[0016] Base;
[0017] An active layer is disposed on one side of the substrate;
[0018] The first gate layer is located on the side of the active layer away from the substrate;
[0019] The second gate layer is located on the side of the first gate layer away from the active layer;
[0020] The first source / drain metal layer is located on the side of the second gate layer away from the first gate layer;
[0021] The second source / drain metal layer is located on the side of the first source / drain metal layer away from the active layer;
[0022] The energy storage unit is a capacitor. The first electrode of the capacitor is located in one of the active layer, the first gate layer, the second gate layer, the first source-drain metal layer, and the second source-drain metal layer. The second electrode of the capacitor is located in the other layer of the active layer, the first gate layer, the second gate layer, the first source-drain metal layer, and the second source-drain metal layer.
[0023] Optionally, the n*kp data signal lines are connected to the n*kp capacitors, and one data signal line is connected to one capacitor; the value of one capacitor is equivalent to the parasitic capacitance value of a column of sub-pixels.
[0024] Optionally, the display panel further includes n*k source drive transistors; one source drive signal line is connected to k data signal lines through the k source drive transistors respectively.
[0025] Optionally, the display panel further includes a power signal line and a reset signal line, the power signal line and the reset signal line being configured to provide a constant voltage signal; the first terminal of the capacitor is connected to the source signal line, and the second terminal is connected to the power signal line or the reset signal line.
[0026] Optionally, the energy storage unit is located on the side of the data signal line near the edge of the display panel.
[0027] Optionally, the display panel further includes:
[0028] Base;
[0029] An active layer is disposed on one side of the substrate;
[0030] The first gate layer is located on the side of the active layer away from the substrate;
[0031] The second gate layer is located on the side of the first gate layer away from the active layer;
[0032] The third gate layer is located on the side of the second gate layer away from the first gate layer.
[0033] The first source / drain metal layer is located on the side of the third gate layer away from the second gate layer;
[0034] The second source / drain metal layer is located on the side of the first source / drain metal layer away from the active layer;
[0035] The energy storage unit is a capacitor. The first electrode of the capacitor is located in one of the active layer, the first gate layer, the second gate layer, the third gate layer, the first source / drain metal layer, and the second source / drain metal layer. The second electrode of the capacitor is located in the other layer of the active layer, the first gate layer, the second gate layer, the third gate layer, the first source / drain metal layer, and the second source / drain metal layer.
[0036] This application also discloses a display device, which includes the display panel described above.
[0037] Compared with related technologies, this application prevents the data signal line from being disconnected by setting the energy storage unit to be connected to the data signal line, thereby preventing the data signal line connected to the sub-pixel from being interfered with and affecting the normal light emission of the pixel.
[0038] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description
[0039] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.
[0040] Figure 1 This is a schematic diagram of a partial circuit structure of a display panel in related technologies.
[0041] Figure 2 This is a schematic diagram of a partial circuit structure of the display panel of this application in one embodiment.
[0042] Figure 3 This is a schematic diagram of the structure of the display panel of this application in one embodiment.
[0043] Figure 4 This is a schematic diagram of the circuit structure of the pixel driving circuit of this application in one embodiment.
[0044] Figure 5 This is a schematic diagram of the hierarchical structure of the display panel of this application in one embodiment.
[0045] Figure 6 This is a partial schematic diagram of the active layer of the display panel in one embodiment of the present application.
[0046] Figure 7 This is a partial schematic diagram of the first gate layer of the display panel of this application in one embodiment.
[0047] Figure 8 This is a partial schematic diagram of the second gate layer of the display panel of this application in one embodiment.
[0048] Figure 9 This is a partial schematic diagram of the first source / drain metal layer of the display panel in one embodiment of the present application.
[0049] Figure 10 for Figures 6 to 9 A schematic diagram showing the superimposed layers. Detailed Implementation
[0050] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.
[0051] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movements between components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.
[0052] In related technologies, to reduce wiring density, a MUX1:k multiplexing circuit scheme is typically used to reduce the number of source drive signal lines. One source drive signal line is connected to k data signal lines, where one data signal line is connected to one column of sub-pixels to transmit data signals to the sub-pixels. This significantly reduces the number of source drive signal lines. However, in products, a mismatch often occurs between the number of sub-pixel columns and the number of data signal lines. For example... Figure 1 As shown, taking a 466*466 resolution display product paired with a 1:9 MUX as an example, there will be a situation where 1398 sub-pixels are matched with 468 data signal lines. This results in 6 data signal lines being unconnected. Unconnected data signal lines will affect the voltage of other data signal lines connected to the same source drive signal line, thus affecting the normal illumination of some pixels. This effect is particularly severe at low brightness levels.
[0053] like Figure 2 As shown, in order to solve the above problems, this application provides a display panel, which includes a plurality of source signal lines 10, a plurality of data signal line groups, a plurality of sub-pixels 40 and a plurality of energy storage units 50.
[0054] A plurality of source signal lines 10 are configured to provide source signals. A group of data signal lines includes a plurality of data signal lines 30, with data signal lines 30 within the same group connected to the same source signal line 10, and data signal lines 30 in different groups connected to different source signal lines 10. The data signal lines 30 are configured to receive source signals and provide data signals. A plurality of sub-pixels 40 are connected to the data signal lines 30 and configured to receive data signals and emit light according to the data signals. A plurality of energy storage units 50 are connected to the data signal lines 30 and configured to receive and store data signals. Some of the data signal lines 30 are connected to the sub-pixels 40, and at least one of the other data signal lines 30 is connected to the energy storage unit 50.
[0055] This application prevents the data signal line from being disconnected by setting up an energy storage unit connected to the data signal line, thereby preventing interference to the data signal line connected to the sub-pixel and thus affecting the normal light emission of the pixel.
[0056] The following will provide a detailed description of various embodiments of this application that conform to the above-described inventive concept.
[0057] like Figure 3 As shown, the display panel may include a display area 1000 and a non-display area 2000 located around the display area 1000.
[0058] The display area 1000 includes sub-pixels 40, data signal lines 30, and gate drive signal lines 60. The data signal lines 30 extend along a first direction F1, and a plurality of data signal lines 30 are arranged along a second direction F2. The gate drive signal lines 60 extend along the second direction F2, and a plurality of gate drive signal lines 60 are arranged along the first direction F1. The first direction F1 can be the column direction of the display panel, and the second direction F2 can be the row direction of the display panel.
[0059] A plurality of sub-pixels 40 are arranged in an array in the display area 1000, and this array can be a rectangular array. The plurality of sub-pixels 40 are arranged along a first direction F1 to form a column of sub-pixels 40, and the plurality of columns of sub-pixels 40 are arranged along a second direction F2 to fill the entire display area 1000. Each column of sub-pixels 40 is connected to the same data signal line 30. Alternatively, odd-numbered rows of sub-pixels 40 in each column are connected to one data signal line 30, and even-numbered rows of sub-pixels 40 are connected to another data signal line 30. Of course, there are also other arrangements, such as a column of sub-pixels 40 connected to three data signal lines 30, four data signal lines 30, etc., which are not listed here. In the subsequent embodiments of this application, the example of a column of sub-pixels 40 connected to the same data signal line 30 will be used for illustration. While satisfying the above arrangement, the plurality of sub-pixels 40 are simultaneously arranged along the second direction F2 to form a row of sub-pixels 40, and the plurality of rows of sub-pixels 40 are arranged along the first direction F1 to fill the entire display area 1000. Each row of sub-pixels 40 is connected to the same gate drive signal line 60.
[0060] The non-display area 2000 is equipped with an active drive module 100 and a gate drive module 200.
[0061] Please also refer to Figure 2 and Figure 3The source drive module 100 can be disposed below the display area 1000. The source drive module 100 includes a driver IC, source signal lines 10, source drive transistors 20, and multiplexed signal lines 70. One end of each of the source drive signal lines 10 is connected to the driver IC, and the other end is connected to the first terminal of the source drive transistor, configured to transmit source drive signals to the first terminal of the source drive transistor. One end of each multiplexed signal line 70 is connected to multiplexed signal terminals MUX1, 2, ..., and the other end is connected to the control terminal of the source drive transistor, configured to transmit multiplexed signals to the control terminal of the source drive transistor. Data signal lines 30 in the display area 1000 extend to the source drive module 100 and are connected to the second terminal of the source drive transistor, configured to receive source signals and provide data signals based on the source signals. A single source signal line 10 can be connected to a group of data signal lines 30. Specifically, the display panel can include n source signal lines 10, n groups of data signal lines, and n groups of source driving transistors. When the display panel adopts a 1:k MUX scheme, each group of data signal lines includes k adjacent data signal lines 30, and each group of source driving transistors includes k source driving transistors, i.e., there are a total of n*k data signal lines and n*k source driving transistors. The display panel also includes k multiplexed signal lines 70. The k data signal lines 30, k source driving transistors, and k multiplexed signal lines 70 are connected one-to-one. Data signal lines 30 within the same group are connected to the same source signal line 10, and data signal lines 30 in different groups are connected to different source signal lines 10, i.e., the k source driving transistors in the same group are connected to the same source driving signal line 10.
[0062] A sub-pixel 40 is simultaneously connected to a data signal line 30 and a gate drive signal line 60. For example... Figure 4 As shown, Figure 4 This is a schematic diagram of the pixel driving circuit corresponding to a sub-pixel 40. This circuit is an 8T1C circuit (8 transistors, one capacitor). In other embodiments, this circuit can be a 2T1C circuit, a 3T1C circuit, or a 7T1C circuit, etc. The data signal terminal DATA of the pixel driving circuit is connected to the data signal line 30, and the control electrode of the data writing transistor T4 is connected to the gate driving signal line 60. The data signal is written into the pixel driving circuit under the control of the gate driving signal to control the light-emitting unit to emit light.
[0063] like Figure 2As shown, in an optional embodiment, there are p columns of sub-pixels 40. The number of data signal lines 30 is greater than the number of columns of sub-pixels 40. The difference between the number of data signal lines 30 and the number of columns of sub-pixels 40 is less than the number of data signal lines 30 in a group of data signal lines, i.e., p < n*k, n*kp < k. This means that at least one group of data signal lines will have redundant data signal lines 30 that are not connected to the sub-pixels 40. In this case, some data signal lines 30 in this group of data signal lines are connected to one column of sub-pixels 40, while other data signal lines 30 are not connected to the sub-pixels 40. At least one of the other data signal lines 30 that are not connected to the sub-pixels 40 is connected to an energy storage unit 50. Optionally, n*kp data signal lines can be connected to n*kp energy storage units 50 respectively. Optionally, the energy storage unit 50 can be a capacitor, and the value of one capacitor is equivalent to the parasitic capacitance value of one column of sub-pixels 40. In this way, the influence of the data signal line 30 connected to the energy storage unit 50 on the source signal line 10 can be reduced, thereby reducing the influence on other data signal lines 30 connected to the sub-pixels 40 in the same group, thus making the display panel emit light uniformly.
[0064] Optionally, when n*kp data signal lines are connected to n*kp energy storage units 50 respectively, the n*kp data signal lines 30 connected to the energy storage units 50 are located at the edges of the display panel. Specifically, when n*kp is even, (n*kp) / 2 of the n*kp data signal lines 30 connected to the energy storage units 50 are located at one edge of the display panel, and the other (n*kp) / 2 are located at the opposite edge of the display panel. When n*kp is odd, (n*k-p+1) / 2 of the n*kp data signal lines 30 connected to the energy storage units 50 are located at one edge of the display panel, and the other (n*kp-1) / 2 are located at the opposite edge of the display panel.
[0065] Taking a 466*466 resolution display product with a 1:9 MUX scheme as an example. Three sub-pixels 40 (R, G, B) constitute one pixel, resulting in 1398 columns of sub-pixels 40, i.e., p = 1398. Because the product uses a 1:9 MUX scheme, k = 9. To ensure that each column of sub-pixels 40 is connected to a data signal line 30 without redundant data signal lines 30, p < n*k, n*kp < k, i.e., 1398 < n*9, n*9 - 1398 < 9, therefore n is 156. This results in 156 source signal lines 10, 156 groups of data signal lines, and 156 groups of source drive transistors, totaling 1404 data signal lines 30 and 1404 source drive transistors. Six data signal lines 30 are not connected to the sub-pixels 40, and at least one of these six data signal lines 30 is connected to the energy storage unit 50. Optionally, two, three, four, five, or six of the six data signal lines 30 can be connected to different energy storage units 50. The energy storage unit 50 can be a capacitor, with the value of one capacitor being equivalent to the parasitic capacitance of a column of sub-pixels 40. When six data signal lines 30 are connected to different energy storage units 50, three of them are located on one edge of the display panel, and the other three are located on the opposite edge of the display panel. That is, three of them are located on the far left of the first group of data signal lines, and the other three are located on the far right of the 156th group of data signal lines. Optionally, the energy storage unit 50 can be located on the side of the data signal lines 30 closest to the edge of the display panel. Specifically, the energy storage unit 50 can be located on the side of the non-display area 2000 closest to the display area 1000.
[0066] In an alternative embodiment, such as Figures 5 to 10 As shown, Figure 5 This is a schematic diagram of the hierarchical structure of the display panel. Figure 6 This is a partial schematic diagram of the active layer. Figure 7 This is a partial schematic diagram of the first gate layer. Figure 8 This is a partial schematic diagram of the second gate layer. Figure 9 This is a partial schematic diagram of the first source / drain metal layer. Figure 10 for Figures 6 to 9 A schematic diagram showing the stacked layers. The display panel, on the third direction F3 from the non-display side to the display side, may sequentially include a substrate 401, an active layer 402, a first gate insulating layer 403, a first gate layer 404, a second gate insulating layer 405, a second gate layer 406, an interlayer insulating layer 407, a first source / drain metal layer 408, a passivation layer 409, a first planarization layer 410, a second source / drain metal layer 411, a second planarization layer 412, and a light-emitting unit and packaging structure 413. The third direction F3 is the thickness direction of the display panel.
[0067] The active layer 402, the first gate layer 404, the second gate layer 406, the first source / drain metal layer 408, and the second source / drain metal layer 411 are conductive layers. The active layer 402, the first gate insulating layer 403, the first gate layer 404, the second gate insulating layer 405, the second gate layer 406, the interlayer insulating layer 407, and the first source / drain metal layer 408 are used to form transistors and capacitor structures in pixel driving circuits. When the energy storage unit 50 is a capacitor, the first terminal of the capacitor can be located in one of the active layer 402, the first gate layer 404, the second gate layer 406, the first source / drain metal layer 408, and the second source / drain metal layer 411, and the second terminal of the capacitor can be located in another of the active layer 402, the first gate layer 404, the second gate layer 406, the first source / drain metal layer 408, and the second source / drain metal layer 411.
[0068] In another alternative embodiment, the display panel may sequentially include, from the non-display side to the display side, a substrate 401, an active layer 402, a first gate insulating layer 403, a first gate layer 404, a second gate insulating layer 405, a second gate layer 406, a third gate insulating layer (not shown) located between the second gate layer 406 and the third gate layer, a third gate layer (not shown) located between the third gate insulating layer and the interlayer insulating layer 407, an interlayer insulating layer 407, a first source / drain metal layer 408, a passivation layer 409, a first planarization layer 410, a second source / drain metal layer 411, a second planarization layer 412, and a light-emitting unit and a packaging structure 413 on the third-direction F3. The first electrode of the capacitor can be located in one of the following layers: active layer 402, first gate layer 404, second gate layer 406, third gate layer, first source / drain metal layer 408, and second source / drain metal layer 411. The second electrode of the capacitor can be located in another layer of the following layers: active layer 402, first gate layer 404, second gate layer 406, third gate layer, first source / drain metal layer 408, and second source / drain metal layer 411.
[0069] In an optional embodiment, the display panel further includes power signal lines and a plurality of reset signal lines, the power signal lines and reset signal lines being configured to provide constant voltage signals. The power signal lines and... Figure 4 The pixel driving circuit shown is connected to the first power supply signal terminal VDD, and several reset signal lines are respectively connected to... Figure 4 The reset signal terminals Vinit1, Vinit2, and Vinit3 of the pixel driving circuit shown are connected. The first terminal of the capacitor can be connected to the source signal line 10, and the second terminal can be connected to the power signal line or the reset signal line.
[0070] This application also discloses a display device, which includes the display panel described above.
[0071] In one embodiment, the display device further includes a housing, and the display panel is disposed within the housing.
[0072] The display device provided in this application embodiment can be any device with display function, such as a mobile phone, tablet computer, television, laptop computer, or vehicle-mounted equipment.
[0073] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A display panel, characterized in that, include: Several source signal lines are configured to provide source signals; A plurality of data signal line groups, wherein each data signal line group includes a plurality of data signal lines, wherein the data signal lines in the same group are connected to the same source signal line, and the data signal lines in different groups are connected to different source signal lines; the data signal lines are configured to receive source signals and provide data signals according to the source signals. Several sub-pixels, connected to the data signal line, are configured to receive the data signal and emit light according to the data signal; Several energy storage units are connected to the data signal line and are configured to receive and store the data signal; Some of the data signal lines are connected to the sub-pixel, and at least one of the other data signal lines is connected to the energy storage unit.
2. The display panel according to claim 1, characterized in that, The number of the plurality of source signal lines is n, the number of the plurality of data signal line groups is n, a group of the data signal line groups includes k data signal lines, and the plurality of sub-pixels are arranged along the first direction to form p columns of sub-pixels. Among them, p root data signal lines are connected to p column sub-pixels, and n*kp root data signal lines are connected to a plurality of energy storage units; p < n*k, n*kp < k.
3. The display panel according to claim 2, characterized in that, The n*kp data signal lines connected to the energy storage unit are located at the edge of the display panel.
4. The display panel according to claim 3, characterized in that, Of the n*kp data signal lines connected to the energy storage unit, (n*kp) / 2 are located on one edge of the display panel, and the other (n*kp) / 2 are located on the opposite edge of the display panel.
5. The display panel according to claim 4, characterized in that, k = 9, n*kp = 6; 3 of the 6 data signal lines connected to the energy storage unit are located on one side edge of the display panel, and the other 3 are located on the opposite side edge of the display panel.
6. The display panel according to claim 2, characterized in that, The display panel also includes: Base; An active layer is disposed on one side of the substrate; The first gate layer is located on the side of the active layer away from the substrate; The second gate layer is located on the side of the first gate layer away from the active layer; The first source / drain metal layer is located on the side of the second gate layer away from the first gate layer; The second source / drain metal layer is located on the side of the first source / drain metal layer away from the active layer; The energy storage unit is a capacitor. The first electrode of the capacitor is located in one of the active layer, the first gate layer, the second gate layer, the first source-drain metal layer, and the second source-drain metal layer. The second electrode of the capacitor is located in the other layer of the active layer, the first gate layer, the second gate layer, the first source-drain metal layer, and the second source-drain metal layer.
7. The display panel according to claim 6, characterized in that, The n*kp data signal lines are connected to the n*kp capacitors, and one data signal line is connected to one capacitor; the value of one capacitor is equal to the parasitic capacitance value of a column of sub-pixels.
8. The display panel according to claim 2, characterized in that, The display panel further includes n*k source drive transistors; one source drive signal line is connected to k data signal lines through the k source drive transistors respectively.
9. The display panel according to claim 6, characterized in that, The display panel also includes a power signal line and a reset signal line, which are configured to provide a constant voltage signal; the first terminal of the capacitor is connected to the source signal line, and the second terminal is connected to the power signal line or the reset signal line.
10. The display panel according to claim 1, characterized in that, The energy storage unit is located on the side of the data signal line near the edge of the display panel.
11. The display panel according to claim 2, characterized in that, The display panel also includes: Base; An active layer is disposed on one side of the substrate; The first gate layer is located on the side of the active layer away from the substrate; The second gate layer is located on the side of the first gate layer away from the active layer; The third gate layer is located on the side of the second gate layer away from the first gate layer. The first source / drain metal layer is located on the side of the third gate layer away from the second gate layer; The second source / drain metal layer is located on the side of the first source / drain metal layer away from the active layer; The energy storage unit is a capacitor. The first electrode of the capacitor is located in one of the active layer, the first gate layer, the second gate layer, the third gate layer, the first source / drain metal layer, and the second source / drain metal layer. The second electrode of the capacitor is located in the other layer of the active layer, the first gate layer, the second gate layer, the third gate layer, the first source / drain metal layer, and the second source / drain metal layer.
12. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1-11.