Near-earth satellite-borne phased array signal processing system

Abstract

The utility model provides a near-earth satellite-borne phased array signal processing system (short for 5G NR-NTN), comprising a front-end 5G signal transceiving system connected through a high-speed FMC interface (short for O-RU); the data front-end processing system is connected with the front-end 5G signal transceiving system through the high-speed FMC interface (O-DU for short); the data co-processing system is connected with the data front-end processing system (called O-CU for short) through a high-speed XMC connector; wherein the front-end 5G signal receiving and transmitting system is used for receiving and transmitting 5G signals, the data front-end processing system is used for processing the signals, the data co-processing system is used for exchanging data, and the front-end 5G signal receiving and transmitting system, the data front-end processing system and the data co-processing system form an integrated signal processing module. According to the utility model, a high-performance CX8242 chip is adopted as the core of a front-end 5G signal transceiving system, and the ADC and DAC with high sampling rate and high resolution and the ADCFB with low noise are combined, so that the precision and efficiency of signal processing are effectively improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of communication, specifically, near earth satellite phased array signal processing system. BACKGROUND

[0002] With the rapid development of global communication technology, especially the wide application of 5G communication technology, people's demand for high-speed, stable and reliable communication is increasing. Under this background, near earth satellite communication, as an important development direction of future communication field, is gradually attracting widespread attention in the industry. Near earth satellite communication uses low earth orbit satellites to achieve global coverage, has the advantages of low transmission delay, small path loss, wide coverage, etc., and has important significance for realizing global modern information integration, meeting big data demand and realizing air, space, land and sea multi-dimensional space interconnection coverage.

[0003] However, the implementation of near earth satellite communication system faces many technical challenges. Among them, signal processing, as the core link of the communication system, directly affects the communication quality and efficiency of the whole system. Traditional satellite communication systems usually use fixed antennas and signal processing modules, which are difficult to realize flexible configuration and expansion, and have high power consumption and prominent heat dissipation problems. In addition, with the introduction of 5G NR-NTN (Non-Terrestrial Network, non-ground network) technology, higher requirements are put forward for the speed, accuracy and flexibility of signal processing.

[0004] In order to cope with these challenges, the industry has begun to explore the design and implementation of near earth satellite phased array signal processing system module. Phased array antenna technology can form a beam pointing to a specific direction by electronically controlling the phase and amplitude of each unit in the antenna array, thereby realizing high-speed and high-precision signal transmission and reception. At the same time, the introduction of modular design concept makes the system can be flexibly configured and expanded according to different application scenarios and requirements, improving the adaptability and flexibility of the system.

[0005] However, the existing near earth satellite phased array signal processing system module still has many shortcomings in performance, power consumption, heat dissipation and modular design. For example, the performance bottleneck of the front-end signal processing module limits the overall performance of the system; power consumption and heat dissipation problems affect the stability and reliability of the system under long-time work; the modular design is not flexible enough to meet the needs of future technology upgrade. UTILITY MODEL CONTENT

[0006] In view of the defects in the prior art, the purpose of the utility model is to provide a near earth satellite phased array signal processing system.

[0007] According to the near earth satellite phased array signal processing system provided by the utility model, it comprises:

[0008] The front-end 5G signal transceiver system is connected through a high-speed FMC interface;

[0009] The data front-end processing system is connected with the front-end 5G signal transceiver system through the high-speed FMC interface;

[0010] The data coprocessing system is connected with the data front-end processing system through a high-speed XMC connector;

[0011] The front-end 5G signal transceiver system performs 5G signal transceiving, the data front-end processing system performs signal processing, and the data coprocessing system performs data exchange, and the front-end 5G signal transceiver system, the data front-end processing system and the data coprocessing system constitute an integrated signal processing module.

[0012] Preferably, the front-end 5G signal transceiver system comprises:

[0013] A CX8242 chip for signal transceiving;

[0014] A synchronous clock CX3E04 for providing a synchronous clock signal for the CX8242 chip;

[0015] At least two analog-to-digital converters ADCs with a maximum input signal frequency of 6 GHz;

[0016] At least two digital-to-analog converters DACs with a maximum output signal frequency of 6 GHz;

[0017] At least one analog-to-digital converter feedback mechanism ADCFB with a maximum input signal frequency of 6 GHz.

[0018] Preferably, the data front-end processing system comprises:

[0019] Two PC802 chips with independent functions for processing radio frequency and physical layer lower Low-PHY;

[0020] An FPGA chip for managing packet data convergence protocol PDCP, service data adaptation protocol SDAP and radio resource control RRC protocol entities, and optical-electric data conversion;

[0021] A refresh chip JFMRS01RH, a board-level power supply network and a system clock module.

[0022] Preferably, the data coprocessing system comprises:

[0023] An LX2160 processor chip for data exchange;

[0024] A set of on-board DDR4 particles as data cache;

[0025] A timing control CPLD chip.

[0026] Preferably, the system further comprises an ORU remote radio unit connected with the data front-end processing system through an eCPRI interface, for performing the tasks of High-PHY, Medium Access Control (MAC) and Radio Link Control (RLC) on the physical layer.

[0027] Preferably, the front-end 5G signal transceiver system, the data front-end processing system and the data co-processing system are integrated on the same circuit board to form a compact module structure.

[0028] Preferably, the system supports the O-RAN architecture and can divide the baseband unit and the radio unit into three different modules of O-RAN radio unit (RU), O-RAN distributed unit (DU) and O-RAN central unit (CU).

[0029] Compared with the prior art, the utility model has the beneficial effects that:

[0030] 1、The utility model discloses a high-performance CX8242 chip as the core of the front-end 5G signal transceiver system, combined with high sampling rate, high resolution ADC and DAC, and low noise ADCFB, effectively improve the precision and efficiency of signal processing.

[0031] 2、The utility model discloses a modular design, and the front-end 5G signal transceiver system, data front-end processing system and data co-processing system are designed as independent modules respectively, and are connected through FMC interface and XMC connector, convenient for the upgrading and extension of the system.

[0032] 3、The utility model discloses a design that fully considers the power consumption and heat dissipation problem, and through the optimization circuit design and the adoption low power consumption device, effectively reduces the power consumption of the system, adopts the high-performance clock module and the synchronous mechanism, ensures the clock synchronization and data synchronization between the modules, improves the overall stability and reliability of the system. BRIEF DESCRIPTION OF DRAWINGS

[0033] Other features, objects and advantages of the utility model will become more apparent through reading the following detailed description of the non-restrictive embodiments with reference to the accompanying drawings:

[0034] Figure 1 It is the structural principle diagram of the utility model. DETAILED DESCRIPTION

[0035] The utility model will be explained in detail below in combination with specific embodiments. The following embodiments will help the person skilled in the art to further understand the utility model, but do not limit the utility model in any form. It should be pointed out that, for the person skilled in the art, on the premise of not departing from the utility model concept, a number of changes and improvements can be made. These all belong to the protection scope of the utility model.

[0036] Referring to Figure 1 According to the near-earth satellite phased array signal processing system, the front-end 5G signal transceiver system 1 is connected with the data front-end processing system 2 through the high-speed FMC interface, the data front-end processing system 2 is connected with the data coprocessing system 3 through the high-speed XMC connector, and the ORU remote radio unit is connected with the data front-end processing system 2 through the eCPRI interface. The ORU remote radio unit is used for executing the tasks of the upper High-PHY of the physical layer, the medium access control MAC and the radio link control RLC. The front-end 5G signal transceiver system 1 is used for transmitting and receiving 5G signals, the data front-end processing system 2 is used for signal processing, and the data coprocessing system 3 is used for data exchange. The front-end 5G signal transceiver system 1, the data front-end processing system 2 and the data coprocessing system 3 constitute an integrated signal processing module.

[0037] The front-end 5G signal transceiver system 1 comprises: a CX8242 chip for signal transceiving; a synchronous clock CX3E04 for providing a synchronous clock signal for the CX8242 chip; at least two analog-digital converters ADCs with a highest input signal frequency of 6 GHz; at least two digital-analog converters DACs with a highest output signal frequency of 6 GHz; and at least one analog-digital converter feedback mechanism ADCFB with a highest input signal frequency of 6 GHz. The CX3E04 chip generates a high-precision clock source, which is mainly applied in a phased array system clock network and a cellular device (a multi-carrier GSM system, LTE, W-CDMA), etc.; supports 14-way clock and SYNC channels, and has multi-channel and multi-chip synchronization functions; the high-precision clock signal source required by the CX8242 chip and an FPGA chip is generated by the CX3E04 chip, the clock signal pin of the CX8242 chip is directly interconnected with the CX3E04, and the clock signal pin of the FPGA chip is interconnected with the CX3E04 through an FMC interface; the CX8242 chip is internally integrated with three channels of 14-bit ADCs (two channels of receiving and one channel of feedback); the CX8242 chip is internally integrated with two channels of 14-bit, 12GSPS DACs. The CX8242 chip is a dual-channel, broadband, radio frequency direct sampling transceiver chip integrated with 14-bit, 12GSPS DACs and 14-bit ADCs, supports direct sampling input and output of a radio frequency signal up to 6 GHz, is integrated with an on-chip high-performance sampling clock module, has a sampling clock jitter of less than 100 fs, and can reach 70 fs at the lowest, is integrated with a DSA module, greatly expands the transceiving dynamic range, is integrated with a SerDes module with a high speed of 25GSPS, is integrated with a flexible and configurable digital channel, maximally improves the system integration degree of a user, and reduces the power consumption of a whole machine. The transmitting DAC link supports 4X-240X flexible and configurable interpolation filtering and an NCO module, is integrated with a PA protection module, supports a high instantaneous signal bandwidth of 1200M, is integrated with a DSA (digital signal attenuation) module with an adjustment range of more than 40 dB, and is used for adjusting the output power of the transmitting link. The receiving ADC link supports 2X-80X flexible and configurable decimation filters and an NCO module, supports a high instantaneous signal bandwidth of 1200 MHz, is integrated with a DSA module with an adjustment range of about 24 dB, and is used for adjusting the energy of a received signal. The feedback ADC link supports 2X-80X flexible and configurable decimation filters and an NCO module, supports a high instantaneous signal bandwidth of 1200 MHz, is integrated with a DSA module with an adjustment range of about 24 dB, and is used for adjusting the energy of a received signal, and the feedback link can be used as a DPD receiving feedback link or a normal receiving link.4 groups of SerDes receive lanes are used for transmitting link data reception, 6 groups of SerDes transmit lanes are used for receiving link data output, the SerDes module supports two interface protocols of JESD204B / C, and the transmission rate of a single lane is up to 25 Gbps.

[0038] The data front-end processing system 2 comprises two independent function PC802 chips for processing radio frequency and low physical layer (Low-PHY); one FPGA chip for managing packet data convergence protocol (PDCP), service data adaptation protocol (SDAP) and radio resource control (RRC) protocol entity, and optoelectronic data conversion; refresh chip JFMRS01RH, board-level power supply network and system clock module. The board-level power supply network and system clock module provide power supply voltages at different levels and internal module clocks for the PC802 chip, the FPGA chip and the system refresh JFMRS01RH chip. After the power supply network required by the FPGA generates voltages at different levels, the internal program initialization of the SPI storage chip is completed and the FPGA runs. After the FPGA performs data caching processing through the JESD204B interface protocol, it is interconnected to the LX2160 chip through the PCIE data interface of the PC802 chip; the system refresh JFMRS01RH chip communicates through a serial port of the FPGA and detects whether the system is abnormal in real time.

[0039] The data co-processing system 3 comprises one LX2160 processor chip for data exchange, one set of on-board DDR4 particles as data cache, and one timing control CPLD chip. The LX2160 processor chip internally integrates a PCIE 4.0 interface and interconnects the PC802 chip for data communication; the LX2160 integrates a DDR4 controller, can mount DDR4 particles, and supports ECC; the CPLD chip serves as a system power timing control to meet the control requirements of the LX2160 processor on power timing, and also serves as a Buffer function for serial ports, IIC, SPI and other interfaces of the LX2160 processor chip.

[0040] The front-end 5G signal transceiver system 1, the data front-end processing system 2 and the data co-processing system 3 are integrated on the same circuit board to form a compact module structure. The near-Earth satellite phased array signal processing system supports the O-RAN architecture and can divide the baseband unit and the radio unit into three different modules of O-RAN radio unit (RU), O-RAN distributed unit (DU) and O-RAN central unit (CU).

[0041] The near-earth satellite phased array signal processing system module technology integrates 5G wireless signal transceiving, signal processing and data exchange, and can realize a component of a new generation of 5G New Radio-Non Terrestrial Network (5G NR-NTN) communication technology.

[0042] The 5G NR-NTN belongs to a LEO (Low Earth Orbit) satellite system, and the LEO satellite system belongs to an open radio access network (O-RAN).

[0043] The O-RAN allows the baseband unit and the radio unit to be divided into three different modules and 5G protocol layers, each of which can be composed of different module units: RU (O-RAN radio unit), responsible for processing radio frequency and low-PHY (Low-PHY); DU (O-RAN distributed unit), responsible for performing the tasks of high-PHY (High-PHY), medium access control (MAC) and radio link control (RLC); CU (O-RAN central unit), responsible for managing packet data aggregation protocol (PDCP), service data adaptation protocol (SDAP) and radio resource control (RRC) protocol entities;

[0044] The near-earth satellite phased array signal processing system module includes: a front-end 5G signal transceiving system 1, a data front-end processing system 2, and a data co-processing system 3.

[0045] The front-end 5G signal transceiving system 1 is connected to the data front-end processing system 2 through a high-speed FMC interface, and the data co-processing system 3 is connected to the data front-end processing system 2 through a high-speed XMC connector. The overall functional composition is as follows:

[0046] The front-end 5G signal transceiving system 1 is composed of CX8242 and a synchronous clock CX3E04; the data front-end processing system 2 is composed of two independent functional PC802 chips on board, a JFMRS01RH refresh chip, a board-level power supply network, and a system clock module; and the data co-processing system 3 is composed of a LX2160 processor chip on board, a set of on-board DDR4 particles, and a timing control CPLD chip.

[0047] Working principle of the near-earth satellite phased array signal processing system module:

[0048] Front-end 5G signal transceiver system 1 is connected to data front-end processing system 2 through high-speed FMC interface, and data co-processing system 3 is connected to data front-end processing system 2 through high-speed XMC connector. The working principle is as follows:

[0049] Front-end 5G signal transceiver system 1 is responsible for signal transceiver by CX8242 on board, and input and output is completed by two ADCs with the highest input signal frequency of 6GHZ, two DACs with the highest output signal frequency of 6GHZ and one ADCFB with the highest input signal frequency of 6GHZ. After receiving the synchronous clock of data front-end processing system 2 through CX3E04 and coding and decoding by CX8242, the data is given to data front-end processing system 2 for processing.

[0050] Data front-end processing system 2 completes the data signal received by front-end 5G signal transceiver system 1 by two independent functional PC802 chips and one FPGA chip on board, and is responsible for the following work:

[0051] PC802 chip: processing radio frequency and low physical layer (Low-PHY), completing physical layer processing and digital front-end (DFE) and other task functions.

[0052] DU function: performing the tasks of high physical layer (High-PHY), medium access control (MAC) and radio link control (RLC), transmitting the processed frequency domain IQ samples to the radio frequency unit of ORU remote end through the use of eCPRI interface; O-CU: FPGA is responsible for the photoelectric data processing of high-speed signal. And is responsible for managing packet data aggregation protocol (PDCP), service data adaptation protocol (SDAP) and radio resource control (RRC) protocol entity.

[0053] FPGA chip: after data front-end processing system 2 receives the data of front-end 5G signal transceiver system 1, the O-RU and O-DU functions are completed by PC802 chip, and then given to the on-board FPGA to manage packet data aggregation protocol (PDCP), service data adaptation protocol (SDAP) and radio resource control (RRC) protocol entity and photoelectric data conversion processing, and then through XMC high-speed bus to data co-processing system 3 for backend data processing required by core network computing-intensive network application and exchange.

[0054] Data front-end processing system 3 on board has a timing control CPLD chip, a LX2160 chip and a group of large-capacity DDR4 memory chips. DDR4 is used as data cache, and LX2160 is used as data exchange. Through XMC high-speed bus, the following task processing is performed with data co-processing system 3:

[0055] Responsible for backend O-CU data processing required by core network computing-intensive network application; responsible for core network data exchange.

[0056] The utility model discloses a structure that adopts near-earth satellite phase array signal processing system module, solves the integration of 5G wireless signal transceiving, signal processing, data exchange, and through this architecture can realize the component of LEO's 5G NR-NTN communication technology in O-RAN. Solve the more flexible design of traditional RAN using single baseband unit (BBU) and radio unit (RU) and other modules. Reach the combination of global modernization information, big data demand, to realize air, sky, land, sea multi-dimensional space interconnection coverage.

[0057] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0058] The specific embodiments of the utility model are described above. It should be understood that the utility model is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essential content of the utility model. The embodiments of the present application and the features in the embodiments can be arbitrarily combined with each other without conflict.

Claims

1. A near-earth satellite-borne phased array signal processing system, characterized by, The system comprises: a front-end 5G signal transceiver system (1) connected through a high-speed FMC interface; a data front-end processing system (2) connected to the front-end 5G signal transceiver system (1) through the high-speed FMC interface; a data co-processing system (3) connected to the data front-end processing system (2) through a high-speed XMC connector; wherein the front-end 5G signal transceiver system (1) performs 5G signal transceiving, the data front-end processing system (2) performs signal processing, and the data co-processing system (3) performs data exchange, and the front-end 5G signal transceiver system (1), the data front-end processing system (2) and the data co-processing system (3) constitute an integrated signal processing module.

2. The near-Earth spaceborne phased array signal processing system of claim 1, wherein, The front-end 5G signal transceiver system (1) comprises: a CX8242 chip for signal transceiving; a synchronous clock CX3E04 providing a synchronous clock signal for the CX8242 chip; at least two analog-to-digital converters ADCs with a maximum input signal frequency of 6 GHz; at least two digital-to-analog converters DACs with a maximum output signal frequency of 6 GHz; at least one analog-to-digital converter feedback mechanism ADCFB with a maximum input signal frequency of 6 GHz.

3. The near-Earth spaceborne phased array signal processing system of claim 1, wherein, The data front-end processing system (2) comprises: two PC802 chips with independent functions for processing radio frequency and low physical layer Low-PHY; one FPGA chip for managing packet data convergence protocol PDCP, service data adaptation protocol SDAP and radio resource control RRC protocol entities, and optical-electric data conversion; refresh chip JFMRS01RH, board-level power supply network and system clock module.

4. The near-Earth spaceborne phased array signal processing system of claim 1, wherein, The data co-processing system (3) comprises: one LX2160 processor chip for data exchange; a set of on-board DDR4 particles as data cache; one timing control CPLD chip.

5. The near-Earth spaceborne phased array signal processing system of claim 1, wherein, The system further comprises an ORU remote radio unit connected to the data front-end processing system (2) through an eCPRI interface for performing the tasks of high physical layer High-PHY, medium access control MAC and radio link control RLC.

6. The near-Earth spaceborne phased array signal processing system of claim 1, wherein, The front-end 5G signal transceiver system (1), the data front-end processing system (2) and the data co-processing system (3) are integrated on the same circuit board to form a compact module structure.

7. The near-Earth spaceborne phased array signal processing system of claim 1, wherein, The system supports O-RAN architecture and can divide the baseband unit and the radio unit into three different modules of O-RAN radio unit RU, O-RAN distributed unit DU and O-RAN central unit CU.

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