E1 interface device for connecting PCM device and signaling conversion device
By using FPGA/DSP co-design and a low-jitter clock buffer circuit, precise clock synchronization of multiple E1 signals was achieved, solving the problems of clock drift and insufficient processing power in traditional systems, improving system stability and anti-interference capabilities, and adapting to the signaling conversion requirements in complex network environments.
Patent Information
- Application Number
- CN202520666540.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-10
- Publication Date
- 2026-02-24
- Estimated Expiration
- 2035-04-10
AI Technical Summary
In multi-channel E1 interface systems, traditional PCM devices and E1 interface devices have difficulty maintaining global clock consistency, which can easily lead to time slot offsets and frame errors. The processing capacity of a single control unit is insufficient, making it difficult to meet the hybrid signaling conversion requirements in complex network environments.
Employing an FPGA/DSP collaborative design, combined with low-jitter clock buffer and isolation protection circuits, a clock synchronization circuit composed of Si5341B and 8SLVP2104 provides a consistent reference clock for the FPGA controller and DSP chip, achieving precise clock synchronization of multiple E1 signals. Through the collaborative work of the E1 transceiver, FPGA controller, and DSP chip, efficient task separation of clock generation, time slot allocation, and frame synchronization is achieved.
It achieves precise clock synchronization of multiple E1 signals, improves system stability and anti-interference capability, can adapt to the needs of high bandwidth, multiple E1 access and signaling conversion, and enhances system reliability and processing capability.
Smart Images
Figure CN223941367U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of telecommunications technology, and in particular relates to an E1 interface device for connecting PCM equipment and signaling conversion equipment. Background Technology
[0002] Traditional PCM devices and E1 interface devices mostly adopt a simple TDM structure, which uses a single or a small number of processors to achieve frame synchronization, signaling extraction and data packaging. Their circuit structure is relatively simple and the cost is low, making them suitable for small-scale systems.
[0003] The shortcomings of traditional technology are:
[0004] In multi-channel E1 interface systems, it is difficult to maintain global consistency of the clocks of each channel, which can easily lead to time slot offsets and frame errors.
[0005] A single control unit (such as a low-end MCU or a single-chip DSP) is easily overwhelmed by multiple high-speed data processing and signaling conversion tasks, leading to a decrease in system stability.
[0006] Traditional designs lack modular division of labor, making it difficult to meet the conversion requirements of hybrid signaling in complex network environments (such as simultaneously supporting E1 trunk signaling and IP-based SIP signaling). Utility Model Content
[0007] The purpose of this invention is to provide an E1 interface device for connecting PCM devices and signaling conversion devices. It solves the technical problems of clock drift and hardware processing capability bottlenecks in traditional systems by using FPGA / DSP collaboration, low jitter clock buffer and isolation protection circuit to achieve precise clock synchronization of multiple E1 signals.
[0008] To achieve the above objectives, the present invention adopts the following technical solution:
[0009] An E1 interface device for connecting PCM equipment and signaling conversion equipment includes E1 interface A, E1 interface B, E1 interface C, E1 interface D, E1 transceiver A, E1 transceiver B, E1 transceiver C, E1 transceiver D, FPGA controller A, FPGA controller B, DPS chip A, DPS chip B, clock synchronization circuit, 232 communication module, communication interface, power supply circuit and 12V power supply interface;
[0010] E1 interfaces A, B, C, and D are connected to E1 transceivers A, B, C, and D, respectively.
[0011] E1 transceiver A and E1 transceiver B are both connected to FPGA controller A; E1 transceiver C and E1 transceiver D are both connected to FPGA controller B.
[0012] Both FPGA controller A and FPGA controller B are connected to DPS chip A; both FPGA controller A and FPGA controller B are also connected to DPS chip B.
[0013] The 232 communication module is connected to DPS chip A, and the communication interface is connected to the 232 communication module;
[0014] The clock synchronization circuit generates three clock signals, which are used to provide reference clocks for FPGA controller A, FPGA controller B and DPS chip B respectively.
[0015] The power supply circuit provides power to E1 transceiver A, E1 transceiver B, E1 transceiver C, E1 transceiver D, FPGA controller A, FPGA controller B, DPS chip A, DPS chip B, clock synchronization circuit, and 232 communication module.
[0016] Preferably, the E1 interface A includes an E1 differential interface A, an isolation transformer A, an isolation transformer B, a TVS diode A, a TVS diode B, a TVS diode C, a TVS diode D, a resistor RR, and a filter capacitor.
[0017] E1 differential interface A is connected to external E1 differential bus A. The two differential signal lines output by E1 differential interface A are connected to the two ends of the primary side of isolation transformer A respectively. At the same time, the two differential signal lines output by E1 differential interface A are connected to the two ends of the primary side of isolation transformer B through resistors R1 and R2 respectively.
[0018] The two ends of the secondary side of isolation transformer A are connected to the RTIP terminal and the TRING terminal of E1 receiver A, respectively; the two ends of the secondary side of isolation transformer B are connected to the TTIP terminal and the TRING terminal of E1 receiver A, respectively.
[0019] The resistor RR is connected in series between the two ends of the secondary side of the isolation transformer A, and the filter capacitor is connected in series between the two ends of the secondary side of the isolation transformer B.
[0020] TVS transistors C and D are TVS protection circuits on both ends of the secondary side of isolation transformer A.
[0021] TVS transistor A and TVS transistor B are TVS protection circuits on both ends of the secondary side of isolation transformer B.
[0022] The circuit principles of E1 interface B, E1 interface C and E1 interface D are the same as those of E1 interface A.
[0023] Preferably, the clock synchronization circuit includes a clock generator and a clock buffer. The clock generator is connected to the input terminal of the clock buffer, and the output terminal of the clock buffer outputs a clock signal for a 1:4 output channel, wherein the three output channels are respectively connected to FPGA controller A, FPGA controller B and DPS chip B.
[0024] Preferably, the clock generator is a Si5341B and the clock buffer is an 8SLVP2104.
[0025] Preferably, the power supply circuit includes a 5VDC-DC module, a TVS protection circuit, a 1.2V regulator, and a 3.3V regulator. The input terminal of the 5VDC-DC module is connected to a 12V power interface, and the output terminal is connected to the input terminal of the 1.2V regulator and the input terminal of the 3.3V regulator, respectively. The output terminal of the 1.2V regulator outputs 1.2V power, and the output terminal of the 3.3V regulator outputs 3.3V power.
[0026] The 1.2V power supply provides 1.2V operating power to FPGA controller A and FPGA controller B;
[0027] The 3.3V power supply powers E1 transceiver A, E1 transceiver B, E1 transceiver C, E1 transceiver D, FPGA controller A, FPGA controller B, DPS chip A, DPS chip B, clock synchronization circuit, and 232 communication module.
[0028] Preferably, the model of E1 transceiver A, E1 transceiver B, E1 transceiver C and E1 transceiver D are all 82P2281;
[0029] Both FPGA controller A and FPGA controller B are model Lattice ECP5LFE5U-45F-8MG285C;
[0030] The models of DPS chip A and DPS chip B are ADSP-BF533;
[0031] The model number of the 232 communication module is MAX232.
[0032] This invention relates to an E1 interface device for connecting PCM equipment and signaling conversion equipment. It solves the technical problems of clock drift and hardware processing bottlenecks in traditional systems by employing FPGA / DSP collaboration, low-jitter clock buffering, and isolation protection circuits to achieve precise clock synchronization of multiple E1 signals. Each pair of E1 signals in this invention uses one FPGA and two DSPs working collaboratively. This allows for task separation and efficient collaboration in clock generation, time slot allocation, frame synchronization, and data packaging. The clock synchronization circuit composed of Si5341B and 8SLVP2104 provides a consistent, low-jitter reference clock for FPGA controller A, FPGA controller B, and DSP chip B, ensuring global synchronization. This provides significant advantages in clock synchronization, data processing, and module division of labor, better adapting to the needs of high bandwidth, multiple E1 access, and signaling conversion, while improving system reliability and anti-interference capabilities. Attached Figure Description
[0033] Figure 1 This is a schematic diagram of the present invention.
[0034] Figure 2 This is a block diagram of the E1 interface A of this utility model;
[0035] Figure 3 This is a block diagram of the clock synchronization circuit of this utility model.
[0036] Figure 4 This is a schematic diagram showing the connection between the E1 transceiver, FPGA, and DSP of this utility model;
[0037] Figure 5 This is a block diagram of the power supply circuit of this utility model. Detailed Implementation
[0038] Depend on Figures 1-5 The E1 interface device shown is used to connect PCM equipment and signaling conversion equipment, including E1 interface A, E1 interface B, E1 interface C, E1 interface D, E1 transceiver A, E1 transceiver B, E1 transceiver C, E1 transceiver D, FPGA controller A, FPGA controller B, DPS chip A, DPS chip B, clock synchronization circuit, 232 communication module, communication interface, power supply circuit and 12V power supply interface;
[0039] E1 interfaces A, B, C, and D are connected to E1 transceivers A, B, C, and D, respectively.
[0040] The E1 interface A includes an E1 differential interface A, an isolation transformer A, an isolation transformer B, a TVS diode A, a TVS diode B, a TVS diode C, a TVS diode D, a resistor RR, and a filter capacitor.
[0041] E1 differential interface A is connected to external E1 differential bus A. The two differential signal lines output by E1 differential interface A are connected to the two ends of the primary side of isolation transformer A respectively. At the same time, the two differential signal lines output by E1 differential interface A are connected to the two ends of the primary side of isolation transformer B through resistors R1 and R2 respectively.
[0042] The two ends of the secondary side of isolation transformer A are connected to the RTIP terminal and the TRING terminal of E1 receiver A, respectively; the two ends of the secondary side of isolation transformer B are connected to the TTIP terminal and the TRING terminal of E1 receiver A, respectively.
[0043] The resistor RR is connected in series between the two ends of the secondary side of the isolation transformer A, and the filter capacitor is connected in series between the two ends of the secondary side of the isolation transformer B.
[0044] TVS transistors C and D are TVS protection circuits on both ends of the secondary side of isolation transformer A.
[0045] TVS transistor A and TVS transistor B are TVS protection circuits on both ends of the secondary side of isolation transformer B.
[0046] The circuit principles of E1 interface B, E1 interface C and E1 interface D are the same as those of E1 interface A.
[0047] Taking E1 interface A as an example, the external E1 differential bus (high-speed differential signal transmitted via coaxial or twisted pair) is first connected through E1 differential interface A.
[0048] The E1 differential interface A ensures balanced signal transmission and isolates the two differential signals via dedicated isolation transformer A and isolation transformer B via R1 and R2, respectively.
[0049] Isolation transformers provide electromagnetic isolation and impedance matching at the physical layer, thereby preventing errors caused by common-mode interference and ground potential differences.
[0050] A resistor RR is connected in series on the secondary side of isolation transformer A to provide appropriate impedance matching. At the same time, TVS diodes are installed on both sides of the transformer (TVS diodes C and D are on the secondary side of transformer A; TVS diodes A and B are on the secondary side of transformer B) to form an ESD and surge protection circuit. In addition, a filter capacitor (connected in series on the secondary side of isolation transformer B) is used to reduce high-frequency interference and noise, ensuring that the signal input to the E1 transceiver has a high signal-to-noise ratio.
[0051] After the entire E1 signal enters, it is protected and isolated before being transmitted to the E1 transceiver in differential signal form. Communication between the E1 differential interface and the E1 transceiver is achieved via the LVDS bus, thereby ensuring high-speed signal transmission and interference immunity.
[0052] E1 transceiver A and E1 transceiver B are both connected to FPGA controller A; E1 transceiver C and E1 transceiver D are both connected to FPGA controller B.
[0053] In this embodiment, all E1 transceivers use the 82P2281 chip, which is specifically designed for the E1 interface and has functions such as frame synchronization, encoding and decoding of differential signals, and alarm status detection.
[0054] In this embodiment, during use, the differential signal from the isolation transformer is processed by the line interface circuit (LIU) built into the 82P2281 to convert the analog or high-speed differential signal with large jitter into a digital signal.
[0055] The frame synchronization module integrated within the 82P2281 is used to detect synchronization signals in E1 frames (usually in TS0) and extract key signaling (such as signaling data in TS16), and output the processed digital data to the subsequent FPGA controller via a digital parallel port.
[0056] Both FPGA controller A and FPGA controller B are connected to DPS chip A; both FPGA controller A and FPGA controller B are also connected to DPS chip B.
[0057] When connected to an FPGA, the 82P2281 outputs digital data via a parallel data bus. Data, synchronization, and status signals are typically transmitted using an LVDS differential bus or directly using high-speed parallel signal lines.
[0058] In this embodiment, the FPGA controller uses two Lattice ECP5LFE5U-45F-8MG285C chips, each responsible for processing the digital signals output from two E1 transceivers. FPGA controller A is responsible for E1 transceivers A and B, and FPGA controller B is responsible for E1 transceivers C and D.
[0059] In use, the FPGA internally implements a high-speed parallel data receiving circuit to extract frame synchronization, time slot data, and signaling information from the data acquired by the 82P2281. Utilizing high-speed logic resources, the FPGA can perform timing checks, data verification, and preliminary signaling separation.
[0060] In this embodiment, the two FPGAs can also exchange data and synchronize status through a high-speed parallel bus (such as LVDS parallel data bus or dedicated high-speed GPIO interface) to ensure the consistency of overall E1 signal processing.
[0061] A high-speed LVDS or direct parallel data bus is used between the FPGA and the E1 transceiver.
[0062] The FPGA and DSP communicate via the SPI interface.
[0063] The 232 communication module is connected to DPS chip A, and the communication interface is connected to the 232 communication module;
[0064] In this embodiment, when developing its application software, DPS chip A can be responsible for global clock generation, time slot allocation, and frame synchronization processing; DPS chip B can be responsible for packaging and encapsulating the data processed by the FPGA and sending the final data to the downstream signaling conversion equipment. The specific development can refer to the following process principle:
[0065] DPS chip A processes the reference clock from the clock synchronization circuit to achieve global timing control and frame boundary signal generation, and transmits the pre-processed E1 time slot allocation information to each FPGA to ensure the consistency of the entire system in terms of physical clock and frame synchronization.
[0066] DPS chip B receives data from two FPGAs, processes it uniformly through a high-speed data interface (such as SPI), and then packages the data according to the communication protocol (such as according to E1 relay or SIP signaling protocol requirements) before outputting it to downstream devices.
[0067] The clock synchronization circuit generates three clock signals, which are used to provide reference clocks for FPGA controller A, FPGA controller B and DPS chip B respectively.
[0068] The clock synchronization circuit includes a clock generator and a clock buffer. The clock generator is connected to the input terminal of the clock buffer, and the output terminal of the clock buffer outputs a clock signal for a 1:4 output channel. The three output channels are respectively connected to FPGA controller A, FPGA controller B, and DPS chip B.
[0069] The clock generator is model Si5341B, and the clock buffer is model 8SLVP2104.
[0070] In this embodiment, the clock generator uses the Si5341B, which can generate a high-precision, low-jitter, multi-output reference clock.
[0071] The clock buffer uses an 8SLVP2104, which can divide the single clock output of the Si5341B into four channels. In this embodiment, three channels are selected as reference clocks.
[0072] During operation, the 8SLVP2104 receives input from the Si5341B, divides it into four outputs, and outputs three of them to FPGA controller A, FPGA controller B, and DPS chip B, respectively, as a unified reference clock to ensure the timing consistency of the entire system.
[0073] The power supply circuit provides power to E1 transceiver A, E1 transceiver B, E1 transceiver C, E1 transceiver D, FPGA controller A, FPGA controller B, DPS chip A, DPS chip B, clock synchronization circuit, and 232 communication module.
[0074] The power supply circuit includes a 5VDC-DC module, a TVS protection circuit, a 1.2V regulator, and a 3.3V regulator. The input terminal of the 5VDC-DC module is connected to a 12V power interface, and the output terminal is connected to the input terminal of the 1.2V regulator and the input terminal of the 3.3V regulator, respectively. The output terminal of the 1.2V regulator outputs 1.2V power, and the output terminal of the 3.3V regulator outputs 3.3V power.
[0075] The 1.2V power supply provides 1.2V operating power to FPGA controller A and FPGA controller B;
[0076] The 3.3V power supply powers E1 transceiver A, E1 transceiver B, E1 transceiver C, E1 transceiver D, FPGA controller A, FPGA controller B, DPS chip A, DPS chip B, clock synchronization circuit, and 232 communication module.
[0077] In this embodiment, the 5VDC-DC module is model LM2596, the TVS protection circuit is a protection circuit composed of TVS tubes, the TVS tube model is PESD5V0S1UL, the 1.2V regulator model is MIC5365-1.2YM5, and the 3.3V regulator model is TPS7A3301.
[0078] The model numbers of E1 transceivers A, B, C, and D are all 82P2281.
[0079] Both FPGA controller A and FPGA controller B are model Lattice ECP5LFE5U-45F-8MG285C;
[0080] The models of DPS chip A and DPS chip B are ADSP-BF533;
[0081] The model number of the 232 communication module is MAX232.
[0082] The MAX232 chip is responsible for communicating with the signaling conversion equipment.
[0083] This invention relates to an E1 interface device for connecting PCM equipment and signaling conversion equipment. It solves the technical problems of clock drift and hardware processing bottlenecks in traditional systems by employing FPGA / DSP collaboration, low-jitter clock buffering, and isolation protection circuits to achieve precise clock synchronization of multiple E1 signals. Each pair of E1 signals in this invention uses one FPGA and two DSPs working collaboratively. This allows for task separation and efficient collaboration in clock generation, time slot allocation, frame synchronization, and data packaging. The clock synchronization circuit composed of Si5341B and 8SLVP2104 provides a consistent, low-jitter reference clock for FPGA controller A, FPGA controller B, and DSP chip B, ensuring global synchronization. This provides significant advantages in clock synchronization, data processing, and module division of labor, better adapting to the needs of high bandwidth, multiple E1 access, and signaling conversion, while improving system reliability and anti-interference capabilities.
Claims
1. An E1 interface device for connecting a PCM device and a signaling conversion device, characterized in that: Includes E1 interface A, E1 interface B, E1 interface C, E1 interface D, E1 transceiver A, E1 transceiver B, E1 transceiver C, E1 transceiver D, FPGA controller A, FPGA controller B, DPS chip A, DPS chip B, clock synchronization circuit, 232 communication module, communication interface, power supply circuit and 12V power supply interface. E1 interfaces A, B, C, and D are connected to E1 transceivers A, B, C, and D, respectively. E1 transceiver A and E1 transceiver B are both connected to FPGA controller A; E1 transceiver C and E1 transceiver D are both connected to FPGA controller B. Both FPGA controller A and FPGA controller B are connected to DPS chip A; both FPGA controller A and FPGA controller B are also connected to DPS chip B. The 232 communication module is connected to DPS chip A, and the communication interface is connected to the 232 communication module; The clock synchronization circuit generates three clock signals, which are used to provide reference clocks for FPGA controller A, FPGA controller B and DPS chip B respectively. The power supply circuit provides power to E1 transceiver A, E1 transceiver B, E1 transceiver C, E1 transceiver D, FPGA controller A, FPGA controller B, DPS chip A, DPS chip B, clock synchronization circuit, and 232 communication module.
2. The E1 interface device for connecting a PCM device and a signaling conversion device as described in claim 1, characterized in that: The E1 interface A includes an E1 differential interface A, an isolation transformer A, an isolation transformer B, a TVS diode A, a TVS diode B, a TVS diode C, a TVS diode D, a resistor RR, and a filter capacitor. E1 differential interface A is connected to external E1 differential bus A. The two differential signal lines output by E1 differential interface A are connected to the two ends of the primary side of isolation transformer A respectively. At the same time, the two differential signal lines output by E1 differential interface A are connected to the two ends of the primary side of isolation transformer B through resistors R1 and R2 respectively. The two ends of the secondary side of isolation transformer A are connected to the RTIP terminal and the TRING terminal of E1 receiver A, respectively; the two ends of the secondary side of isolation transformer B are connected to the TTIP terminal and the TRING terminal of E1 receiver A, respectively. The resistor RR is connected in series between the two ends of the secondary side of the isolation transformer A, and the filter capacitor is connected in series between the two ends of the secondary side of the isolation transformer B. TVS transistors C and D are TVS protection circuits on both ends of the secondary side of isolation transformer A. TVS transistor A and TVS transistor B are TVS protection circuits on both ends of the secondary side of isolation transformer B. The circuit principles of E1 interface B, E1 interface C and E1 interface D are the same as those of E1 interface A.
3. An E1 interface device for connecting a PCM device and a signaling conversion device as described in claim 1, characterized in that: The clock synchronization circuit includes a clock generator and a clock buffer. The clock generator is connected to the input terminal of the clock buffer, and the output terminal of the clock buffer outputs a clock signal for a 1:4 output channel. The three output channels are respectively connected to FPGA controller A, FPGA controller B, and DPS chip B.
4. An E1 interface device for connecting a PCM device and a signaling conversion device as described in claim 3, characterized in that: The clock generator is model Si5341B, and the clock buffer is model 8SLVP2104.
5. An E1 interface device for connecting a PCM device and a signaling conversion device as described in claim 1, characterized in that: The power supply circuit includes a 5VDC-DC module, a TVS protection circuit, a 1.2V regulator, and a 3.3V regulator. The input terminal of the 5VDC-DC module is connected to a 12V power interface, and the output terminal is connected to the input terminal of the 1.2V regulator and the input terminal of the 3.3V regulator, respectively. The output terminal of the 1.2V regulator outputs 1.2V power, and the output terminal of the 3.3V regulator outputs 3.3V power. The 1.2V power supply provides 1.2V operating power to FPGA controller A and FPGA controller B; The 3.3V power supply powers E1 transceiver A, E1 transceiver B, E1 transceiver C, E1 transceiver D, FPGA controller A, FPGA controller B, DPS chip A, DPS chip B, clock synchronization circuit, and 232 communication module.
6. An E1 interface device for connecting a PCM device and a signaling conversion device as described in claim 1, characterized in that: The model numbers of E1 transceivers A, B, C, and D are all 82P2281. Both FPGA controller A and FPGA controller B are model Lattice ECP5LFE5U-45F-8MG285C; The models of DPS chip A and DPS chip B are ADSP-BF533; The model number of the 232 communication module is MAX232.