Backlight driving system, display system and display

Abstract

The utility model is applicable to the technical field of display, and particularly relates to a backlight driving system, a display system and a display. The backlight driving system comprises a system controller, a switch time sequence controller and N driving chip cascade branches, each driving chip cascade branch comprises M driving chips which are connected in series, the driving chips are used for controlling LED lamp beads connected with the driving chips, each driving chip is in duplex communication, the system controller is connected with the switch time sequence controller, and the switch time sequence controller is connected with the N driving chip cascade branches. The switch time sequence controller is respectively connected with the first driving chip of each driving chip cascade branch through a corresponding interface, the switch time sequence controller is in duplex communication, and by setting a one-input multiple-output or multiple-input multiple-output signal transmission mode of one switch time sequence controller, communication signal lines of the driving chips are reduced under a direct-driven display system, and the display efficiency is improved. According to the technical scheme, all driving chips do not need to be connected in series, physical line delay control can be achieved through the switch time sequence controller, the black frame insertion function is achieved, and therefore the reliability of a display system is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a backlight driving system, a display system, and a monitor. Background Technology

[0002] Mini LED (Mini Light-Emitting Diode) backlighting is an emerging display technology that offers advantages such as higher brightness, wider color gamut, and lower power consumption. As market penetration increases, users are demanding lower system costs and higher reliability, leading to the development of Active Matrix (AM) backlighting solutions.

[0003] AM (Advanced Modem) backlight drivers typically employ an architecture where driver chips (Integrated Circuit, IC) are evenly distributed across the LED chips on a printed circuit board (PCB), and communication with the front-end controller is achieved via the shortest path bridging (Serial-Parallel-Broadcast, SPB) protocol or other single-wire protocols. Compared to traditional passive matrix (PM) backlight drivers, it offers advantages such as fewer cable pins, lower system cost, and less concentrated heat distribution.

[0004] To further reduce system hardware costs, the backlight local dimming solution adopts a system-on-chip (SoC) direct-drive control scheme, i.e., without a BCON chip, where the SoC directly controls the AM driver IC. This offers advantages such as higher integration, lower system cost, and less latency between the backlight and the screen. Currently, existing SoC boards control the backlight for local dimming via the Serial Peripheral Interface (SPI) protocol. However, current AM driver ICs typically identify and receive control signals from the front end through SPB or other single-wire communication protocols. Since SoC manufacturers do not integrate SPB or other single-wire communication protocols, an SPI signal line is needed to simulate and send data in this communication format. SoCs only have 1-2 SPI interfaces, which increases the number of AM driver ICs controlled by each SPI interface compared to solutions with BCON / MCU.

[0005] The communication connection methods for SoC direct drive solutions are as follows: 1) Single-line unidirectional communication via DIS and DOS. The last IC DOS in the previous row is cascaded with the first IC DIS in the next row, and so on. The last IC DOS signal is returned to the backlight controller, such as... Figure 1As shown; 2) Single-line bidirectional communication is performed via DIS and DOS. The last IC DOS in the previous row is cascaded with the first IC DIS in the next row, and so on. The signal from the last IC DOS is not returned to the backlight controller. Figure 2 As shown; 3) Addressing, readback, FB feedback, etc. are performed through Di / Do, register values ​​are modified and LD data is updated through Dip, and the backlight is controlled using an architecture of serial-parallel transmission, unidirectional cascading, and DOS return, such as Figure 3 As shown. Due to the large number of driver IC chips in a single lane cascade and only one DIS / DOS communication line connected in series, if any one IC fails, it will affect the normal operation of all subsequent ICs, resulting in poor communication reliability. In addition, DIS / DOS needs to reuse multiple functions such as updating brightness data, FB feedback, and fault reading, resulting in poor real-time performance. Furthermore, there is a significant delay between the data update times of the first and last ICs, which is not conducive to BFI functionality. There are many communication signal lines, which consume a lot of SPI DMA port resources, and the reliability of hardware connections is poor.

[0006] Therefore, how to improve the system architecture in a SoC-driven display system to enhance the reliability of hardware connections has become an urgent problem to be solved. Summary of the Invention

[0007] In view of this, embodiments of this application provide a backlight driving system, a display system, and a display to address the problem of how to improve the system architecture in a SoC-driven display system to enhance the reliability of hardware connections.

[0008] In a first aspect, embodiments of this application provide a backlight driving system, the backlight driving system including a system controller, a switching timing controller and N cascaded branches of driving chips, the cascaded branches of driving chips including M driving chips connected in series, the driving chips being used to control LED beads connected thereto, each driving chip being a full-duplex communication, and N and M being integers greater than zero;

[0009] The system controller is connected to the switch timing controller, and the switch timing controller is connected to the first driver chip of each cascaded branch of the driver chip through a corresponding interface. The switch timing controller is a full-duplex communication controller.

[0010] In one embodiment, the switching timing controller further includes N address interfaces, each address interface being connected to the address voltage interface of the first driver chip in each cascaded branch of the driver chip, so as to determine the row address of each cascaded branch of the driver chip.

[0011] In one embodiment, the system controller includes one or two serial peripheral interfaces, and the system controller is connected to the switching timing controller through the serial peripheral interfaces.

[0012] In one embodiment, the system controller is a system-on-a-chip, a front-end timing controller, or a microcontroller unit.

[0013] Secondly, embodiments of this application provide a display system, the display system including a backlight driving system and a backlight panel, the backlight panel being composed of LED beads;

[0014] The backlight driving system includes a system controller, a switching timing controller, and N cascaded driving chip branches. Each cascaded driving chip branch includes M driving chips connected in series. Each driving chip is connected to a corresponding LED bead. Each driving chip is a full-duplex communication chip. N and M are both integers greater than zero.

[0015] The system controller is connected to the switch timing controller, and the switch timing controller is connected to the first driver chip of each cascaded branch of the driver chip through a corresponding interface. The switch timing controller is a full-duplex communication controller.

[0016] In one embodiment, the switching timing controller further includes N address interfaces, each address interface being connected to the address voltage interface of the first driver chip in each cascaded branch of the driver chip, so as to determine the row address of each cascaded branch of the driver chip.

[0017] In one embodiment, the system controller includes one or two serial peripheral interfaces, and the system controller is connected to the switching timing controller through the serial peripheral interfaces.

[0018] In one embodiment, the system controller is a system-on-a-chip, a front-end timing controller, or a microcontroller unit.

[0019] In one embodiment, the backlight panel includes M lamp panels, each of which is connected to a driver chip.

[0020] Thirdly, embodiments of this application provide a display system, the display including the display system described in the second aspect and its improvements.

[0021] The beneficial effects of this application embodiment compared with the prior art are as follows: The backlight driving system of this application includes a system controller, a switching timing controller, and N cascaded branches of driving chips. Each cascaded branch of driving chips includes M driving chips connected in series. The driving chips are used to control the LED beads connected to them. Each driving chip is a full-duplex communication device. The system controller is connected to the switching timing controller. The switching timing controller is connected to the first driving chip of each cascaded branch of driving chips through a corresponding interface. The switching timing controller is a full-duplex communication device. By setting a one-input-multiple-output or multiple-input-multiple-output signal transmission mode of the switching timing controller, the communication signal lines of the driving chips are reduced in the direct-drive display system. It is not necessary for all driving chips to be connected in series. Moreover, the switching timing controller can realize physical line delay control and has black frame insertion function, thereby improving the reliability of the display system. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a single-wire, simplex, single-string IC cascade structure provided by existing technology;

[0024] Figure 2 This is a schematic diagram of a single-wire, full-duplex, single-string IC cascade structure provided by existing technology;

[0025] Figure 3 This is a schematic diagram of an IC cascade structure provided by existing technology, which includes dual single-wire serial-parallel, simplex, and single-string connections.

[0026] Figure 4 This is a schematic diagram of a backlight driving system provided in Embodiment 3 of this application;

[0027] Figure 5 This is a schematic diagram of a backlight driving system provided in Embodiment 4 of this application. Detailed Implementation

[0028] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0029] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0030] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0031] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0032] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0033] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0034] It should be understood that the sequence number of each step in the following embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0035] To illustrate the technical solution of this application, specific embodiments are described below.

[0036] See Figure 4 This is a schematic diagram of a backlight driving system provided in Embodiment 1 of this application. The backlight driving system includes a system controller, a switching timing controller, and N cascaded driving chip branches. Each cascaded driving chip branch includes M driving chips connected in series. The driving chips are used to control the LED beads connected to them. Each driving chip is a full-duplex communication chip. N and M are both integers greater than zero.

[0037] The system controller is connected to the switch timing controller, and the switch timing controller is connected to the first driver chip of each cascaded branch of the driver chip through a corresponding interface. The switch timing controller is a full-duplex communication controller.

[0038] In one embodiment, the system controller includes one or two serial peripheral interfaces, and the system controller is connected to the switching timing controller through the serial peripheral interfaces.

[0039] In one embodiment, the system controller is a system-on-a-chip (SoC), a front-end timing controller, or a microcontroller unit. The front-end host computer is not limited to a SoC chip; it can also be other timing control chips such as a TCON / MCU.

[0040] A switch timing controller (STCON) is added between the SoC / timing controller (TCON) and the driver chip. Like the driver IC, this controller supports full-duplex communication, enabling one-input-many-output or many-input-many-output signal transmission. It can determine the control mode by identifying the DIS / DOS signal line data connected to the SoC / TCON.

[0041] The control modes include: fixed address, readback register, FB feedback, and local dimming update.

[0042] The switching timing controller identifies the front-end SoC / TCON controller signals as addressing instructions. Then, each branch's DIS / DOS sequentially sends addressing instructions to its respective first driver IC. After the first driver IC completes addressing, the instructions are passed to the next IC, and so on, completing the chip addressing work for each individual branch.

[0043] The switching timing controller identifies the front-end SoC / TCON controller signal as a readback instruction for a certain register corresponding to a certain branch. The corresponding DIS / DOS branch outputs data to the first driver IC of that branch and is configured in reverse communication mode.

[0044] The switching timing controller identifies the front-end SoC / TCON controller signal as an FB instruction, and each branch of DIS / DOS outputs instructions to the first driver IC to switch DIS / DOS to FB mode. Then, the switching timing controller receives interrupt information from each branch to check if there is insufficient voltage in the LED string.

[0045] The switching timing controller identifies the front-end controller signal as a local dimming command, then splits it into branches, and distributes the corresponding brightness data to the corresponding driver IC according to the mapping.

[0046] This application mainly targets direct drive solutions such as SoC / TCON with only 1 to 2 sets of SPI / single-wire signal input and output at the front end. The architecture has built-in delay control between physical rows and naturally supports the Black Frame Insertion (BFI) function.

[0047] like Figure 5 The diagram shown is a structural schematic of a backlight driving system provided in Embodiment 2 of this application. The switching timing controller further includes N address interfaces. Each address interface is connected to the address voltage interface of the first driver chip in each cascaded branch of the driver chip to determine the row address of each cascaded branch of the driver chip.

[0048] The driver chip (IC) has its own Addr pin. On the adapter board, each string of chips is assigned a different addr voltage value for identification and differentiation. After the driver IC is powered on, the voltage of the addr pin must first be identified to determine which row it is in, and then the column address is determined. That is, by adding an address pin to each driver IC, the row and column address information of each driver IC can be determined, which improves the addressing efficiency.

[0049] This application embodiment also provides a display system, the display system including a backlight driving system and a backlight panel, the backlight panel being composed of LED beads; the backlight driving system including a system controller, a switching timing controller, and N cascaded branches of driving chips, each cascaded branch including M driving chips connected in series, each driving chip being connected to a corresponding LED bead, each driving chip being a full-duplex communication, and N and M being integers greater than zero; the system controller is connected to the switching timing controller, the switching timing controller being connected to the first driving chip of each cascaded branch through a corresponding interface, the switching timing controller being a full-duplex communication.

[0050] In one embodiment, the switching timing controller further includes N address interfaces, each address interface being connected to the address voltage interface of the first driver chip in each cascaded branch of the driver chip, so as to determine the row address of each cascaded branch of the driver chip.

[0051] In one embodiment, the system controller includes one or two serial peripheral interfaces, and the system controller is connected to the switching timing controller through the serial peripheral interfaces.

[0052] In one embodiment, the system controller is a system-on-a-chip, a front-end timing controller, or a microcontroller unit.

[0053] In one embodiment, the backlight panel includes M LED strips, each connected to a driver chip. This application embodiment is applicable to scenarios where LED strips are arranged horizontally in a physical structure. The SoC / TCON direct-drive system architecture inherently includes row / lane addresses, eliminating the need for cascading driver ICs between LED strips / LED strips.

[0054] This application embodiment also provides a display system, the display including a backlight driving system and a backlight panel, the backlight panel being composed of LED beads; the backlight driving system including a system controller, a switching timing controller and N cascaded branches of driving chips, each cascaded branch including M driving chips connected in series, each driving chip being connected to a corresponding LED bead, each driving chip being a full-duplex communication, and N and M being integers greater than zero; the system controller is connected to the switching timing controller, the switching timing controller being connected to the first driving chip of each cascaded branch of driving chips through a corresponding interface, the switching timing controller being a full-duplex communication.

[0055] In one embodiment, the switching timing controller further includes N address interfaces, each address interface being connected to the address voltage interface of the first driver chip in each cascaded branch of the driver chip, so as to determine the row address of each cascaded branch of the driver chip.

[0056] In one embodiment, the system controller includes one or two serial peripheral interfaces, and the system controller is connected to the switching timing controller through the serial peripheral interfaces.

[0057] In one embodiment, the system controller is a system-on-a-chip, a front-end timing controller, or a microcontroller unit.

[0058] In one embodiment, the backlight panel includes M lamp panels, each of which is connected to a driver chip.

[0059] It should be noted that the information interaction and execution process between the above modules are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, which will not be repeated here.

[0060] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0061] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0062] In the embodiments provided in this application, it should be understood that the disclosed apparatus / computer devices and methods can be implemented in other ways. For example, the apparatus / computer device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0063] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0064] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A backlight driving system, characterized by, The backlight driving system comprises a system controller, a switch timing controller and N driving chip cascaded branches, each of the driving chip cascaded branches comprises M driving chips connected in series, each of the driving chips is used for controlling an LED lamp bead connected thereto, each of the driving chips is duplex communication, and N and M are integers greater than zero. The system controller is connected with the switch timing controller, the switch timing controller is connected with the first driving chip of each driving chip cascaded branch through a corresponding interface, and the switch timing controller is duplex communication.

2. The backlight driving system of claim 1, wherein, The switch timing controller further comprises N address interfaces, each of the address interfaces is connected with the address voltage interface of the first driving chip of each driving chip cascaded branch, so as to determine the row address of each driving chip cascaded branch.

3. The backlight driving system of claim 1, wherein, The system controller comprises one or two serial peripheral interfaces, and the system controller is connected with the switch timing controller through the serial peripheral interfaces.

4. The backlight driving system according to any one of claims 1 to 3, characterized in that, The system controller is a system level chip, a front-end timing controller or a micro control unit.

5. A display system characterized by, The display system comprises a backlight driving system and a backlight plate, and the backlight plate is composed of LED lamp beads. The backlight driving system comprises a system controller, a switch timing controller and N driving chip cascaded branches, each of the driving chip cascaded branches comprises M driving chips connected in series, each of the driving chips is connected with a corresponding LED lamp bead, each of the driving chips is duplex communication, and N and M are integers greater than zero. The system controller is connected with the switch timing controller, the switch timing controller is connected with the first driving chip of each driving chip cascaded branch through a corresponding interface, and the switch timing controller is duplex communication.

6. The display system of claim 5, wherein, The switch timing controller further comprises N address interfaces, each of the address interfaces is connected with the address voltage interface of the first driving chip of each driving chip cascaded branch, so as to determine the row address of each driving chip cascaded branch.

7. The display system of claim 5, wherein, The system controller comprises one or two serial peripheral interfaces, and the system controller is connected with the switch timing controller through the serial peripheral interfaces.

8. The display system of any one of claims 5 to 7, wherein, The system controller is a system level chip, a front-end timing controller or a micro control unit.

9. The display system of claim 8, wherein, The backlight plate comprises M lamp plates, each of the lamp plates is connected with a driving chip.

10. A display, characterized by The display comprises the display system according to any one of claims 5 to 9.

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