Array substrate and display panel
By designing a centrally symmetrical transfer electrode and pixel electrode structure on the array substrate, the light leakage problem caused by scan line misalignment in LCD displays is solved, thereby improving the light efficiency and stability of the display panel.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-08
- Publication Date
- 2026-03-10
AI Technical Summary
In VR products, LCD displays suffer from increased light leakage and reduced luminous efficiency due to misalignment of scan lines caused by high pixel density.
The array substrate is designed so that the intersections of two adjacent transition electrodes with the data lines and scan lines are centrally symmetrical, the drains of the thin-film transistors are also centrally symmetrical, the pixel electrodes are symmetrical, and protrusions are provided at the vias to bridge the electrodes and prevent light leakage.
By keeping the overlap width between the vias and the scan lines constant, the light effect of the display panel is improved, and the display stability and light effect uniformity are enhanced.
Smart Images
Figure CN223986265U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, specifically to an array substrate and a display panel. Background Technology
[0002] The pixel density of LCD (Liquid Crystal Display) displays for VR (Virtual Reality) products has exceeded 1500 PPI (Pixels Per Inch) and is expected to move towards 1700 PPI and 2000 PPI. During the manufacturing of LCD display panels, misalignment in the film layers containing the scan lines can exacerbate light leakage in the display area, resulting in reduced luminous efficiency. Utility Model Content
[0003] Embodiments of this application provide an array substrate to improve the problem of reduced light efficiency in display panels.
[0004] In a first aspect, embodiments of this application provide an array substrate, comprising:
[0005] substrate;
[0006] Multiple scan lines are spaced apart on the substrate along a column direction;
[0007] Multiple data lines are spaced apart on the substrate along the row direction;
[0008] Multiple pixel units are disposed between two adjacent data lines. Each pixel unit includes a thin-film transistor, a transition electrode, and a pixel electrode. The gate of the thin-film transistor is electrically connected to the scan line, and the source of the thin-film transistor is electrically connected to the data line. The transition electrode is electrically connected to the drain of the thin-film transistor through a first via penetrating between the film layer containing the transition electrode and the film layer containing the drain of the thin-film transistor. The pixel electrode is electrically connected to the transition electrode through a second via penetrating between the film layer containing the pixel electrode and the film layer containing the transition electrode. Two adjacent transition electrodes in the row direction are centrally symmetrical about the intersection of the data line and the scan line. The drains of two adjacent thin-film transistors in the row direction are centrally symmetrical about the intersection of the data line and the scan line. Two adjacent pixel electrodes in the row direction are symmetrically arranged.
[0009] In a top view of the array substrate, a portion of the scan line overlaps with a portion of the first via.
[0010] Furthermore, the adapter electrode extends toward the second via with a first protrusion that extends beyond the edge of the second via.
[0011] Furthermore, the ratio of the width of the first protrusion to the width of the opening of the second through hole ranges from 0.1 to 0.2.
[0012] Furthermore, the pixel electrode extends toward the second via with a second protrusion that extends beyond the edge of the second via.
[0013] Furthermore, the width of the second protrusion is 0.3um to 0.6um.
[0014] Furthermore, the widths of the two second protrusions of two adjacent pixel electrodes located in the row direction are the same.
[0015] Furthermore, two adjacent pixel electrodes located in the row direction are centrally symmetrical about the intersection of the data line and the scan line.
[0016] Furthermore, two adjacent pixel electrodes located in the row direction are axially symmetrical about the data line as the axis of symmetry.
[0017] Furthermore, in the top view of the array substrate, a portion of one of the two adjacent pixel electrodes in the row direction overlaps with one of the two adjacent first vias in the same row direction, and a portion of the other of the two adjacent pixel electrodes in the row direction does not overlap with the other of the two adjacent first vias in the same row direction.
[0018] Secondly, embodiments of this application provide a display panel, the display panel including the array substrate.
[0019] The beneficial effects of this application are:
[0020] This application provides an array substrate in which two adjacent transition electrodes in the row direction are centrally symmetrical about the intersection of the data line and the scan line, the drains of two adjacent thin-film transistors in the row direction are centrally symmetrical about the intersection of the data line and the scan line, and the two adjacent pixel electrodes in the row direction are symmetrical. This ensures that the total overlap width of the two first vias in the row direction with the scan line remains constant, thereby improving the light leakage problem of the display panel caused by misalignment of the scan line and enhancing the light emission efficiency of the display panel. Attached Figure Description
[0021] Figure 1This is a top view of the array substrate of the display panel of this application;
[0022] Figure 2 This is an enlarged schematic diagram of position A of the first type of array substrate of the display panel of this application;
[0023] Figure 3 This is an enlarged schematic diagram of position A of the second type of array substrate of the display panel of this application;
[0024] Figure 4 This is a cross-sectional view of the array substrate of this application.
[0025] Explanation of reference numerals in the attached figures:
[0026] 10-Array substrate; 100-Substrate; 200-Scan line; 300-Data line; 400-Pixel unit; 410-Thin film transistor; 412-Source; 413-Drain; 420-Transfer electrode; 421-First protrusion; 430-Pixel electrode; 431-Second protrusion; 500-First via; 600-Second via.
[0027] 101-Buffer layer, 102-First gate metal layer, 103-First gate insulating layer, 104-Semiconductor layer, 105-Second gate insulating layer, 106-Second gate metal layer, 107-First interlayer insulating layer, 108-Source metal, 109-Second interlayer insulating layer. Detailed Implementation
[0028] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The technical solutions described below are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.
[0029] Furthermore, the terms "first," "second," and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms "multiple" and similar words indicate two or more unless otherwise expressly specified.
[0030] Embodiments of this application provide a display panel, see reference. Figures 1-4 The display panel includes a substrate 10, which includes a substrate 100, multiple scan lines 200, multiple data lines 300, and multiple pixel units 400.
[0031] Specifically, multiple scan lines 200 are spaced apart along the column direction M on the substrate 100; multiple data lines 300 are spaced apart along the row direction L on the substrate 100; a pixel unit 400 is disposed between two adjacent data lines 300, and the pixel unit 400 includes a thin-film transistor 410, a transition electrode 420, and a pixel electrode 430. The gate of the thin-film transistor 410 is electrically connected to the scan line 200, and the source 412 of the thin-film transistor 410 is electrically connected to the data line 300. The transition electrode 420 passes through the film layer containing the transition electrode 420 and the film layer containing the drain 413 of the thin-film transistor 410. The first via 500 is electrically connected to the drain 413. The pixel electrode 430 is electrically connected to the transition electrode 420 through a second via 600 that passes through the film layer where the pixel electrode 430 is located and the film layer where the transition electrode 420 is located. Two adjacent transition electrodes 420 located in the row direction L are centrally symmetrical about the intersection of the data line 300 and the scan line 200. The drains 413 of two adjacent thin film transistors 410 located in the row direction L are centrally symmetrical about the intersection of the data line 300 and the scan line 200. In the top view of the substrate 10, a portion of the scan line 200 overlaps with a portion of the first via 500.
[0032] During the fabrication of an LCD display panel, misalignment in the film layer where the scan line 200 is located can easily lead to increased light leakage in the display area, resulting in reduced luminous efficiency. Therefore, the technical solution of this application addresses this by setting adjacent transition electrodes 420 along the horizontal direction L to be centrally symmetrical about the intersection of the data line 300 and the scan line 200; the drains 413 of adjacent thin-film transistors 410 along the horizontal direction L to be centrally symmetrical about the intersection of the data line 300 and the scan line 200; and adjacent pixel electrodes 430 along the horizontal direction L to be symmetrical. This ensures that the total overlap width between the two first vias 500 and the scan line 200 along the horizontal direction L remains constant, thereby improving the light leakage problem caused by misalignment of the scan line 200 and enhancing the luminous efficiency of the display panel.
[0033] In this embodiment, reference Figure 2 , Figure 3The transition electrode 420 has a first protrusion 421 extending toward the second via 600, and the first protrusion 421 extends beyond the edge of the second via 600. By providing the first protrusion 421 extending toward the second via 600, and the first protrusion 421 extending beyond the edge of the second via 600, it is beneficial to bridge the pixel electrode 430 and the transition electrode 420, and to avoid the second via 600 being over-etched, which would cause corrosion of the film layer below the transition electrode 420 and reduce the stability of the thin-film transistor 410.
[0034] In this embodiment, reference Figure 2 , Figure 3 The ratio of the width 'a' of the first protrusion 421 to the width 'b' of the opening of the second via 600 is in the range of 0.1 to 0.2. By setting the ratio of the width 'a' of the first protrusion 421 to the width 'b' of the opening of the second via 600 to be in the range of 0.1 to 0.2, on the one hand, excessive interference to the electric field of the pixel electrode 430 caused by the width of the first protrusion 421 being too long is avoided; on the other hand, the problem of poor morphology of the second via 600 caused by the width of the first protrusion 421 being too short is avoided. Preferably, the ratio of the width of the first protrusion 421 to the width of the opening of the second through hole 600 is in the range of 0.1, 0.105, 0.11, 0.115, 0.12, 0.125, 0.13, 0.135, 0.14, 0.145, 0.15, 0.155, 0.16, 0.165, 0.17, 0.175, 0.18, 0.185, 0.19, 0.195, or 0.2.
[0035] In this embodiment, reference Figure 2 , Figure 3 The pixel electrode 430 extends toward the second via 600 with a second protrusion 431, which extends beyond the edge of the second via 600. By providing the second protrusion 431 extending toward the second via 600, and the second protrusion 431 extending beyond the edge of the second via 600, it is possible to prevent misalignment during subsequent drilling processes, avoid etching solution from corroding the morphology of the second via 600, and consequently corrode the pixel electrode 430, leading to display abnormalities in the display panel.
[0036] In this embodiment, reference Figure 2 , Figure 3 The width c of the two second protrusions 431 of two adjacent pixel electrodes 430 located in the row direction L is the same.
[0037] In this embodiment, reference Figure 2 , Figure 3The width c of the second protrusion 431 is 0.3um to 0.6um. By setting the width c of the second protrusion 431 to 0.3um to 0.6um, it is possible to avoid the pixel electrode 430 climbing uphill and causing poor morphology of the second via 600, which would reduce the stability of the display panel. Preferably, the width c of the second protrusion 431 is 0.3um, 0.31um, 0.32um, 0.33um, 0.34um, 0.35um, 0.36um, 0.37um, 0.38um, 0.39um, 0.4um, 0.41um, 0.42um, 0.43um, 0.44um, 0.45um, 0.46um, 0.47um, 0.48um, 0.49um, 0.5um, 0.51um, 0.52um, 0.53um, 0.54um, 0.55um, 0.56um, 0.57um, 0.58um, 0.59um, or 0.6um.
[0038] In this embodiment, reference Figure 2 Two adjacent pixel electrodes 430 located in the row direction L are centrally symmetrical about the intersection of the data line 300 and the scan line 200. By setting two adjacent pixel electrodes 430 located in the row direction L to be centrally symmetrical about the intersection of the data line 300 and the scan line 200, that is, a completely symmetrical pixel design is performed in the row direction L of the substrate 10, which can ensure the consistency of the shape of the pixel electrodes 430, thereby helping to improve the uniformity of the light effect of the display panel.
[0039] Specifically, in the top view of the substrate 10, two adjacent pixel electrodes 430 located in the row direction L do not overlap with two adjacent first vias 500 located in the same row direction L.
[0040] In this embodiment, reference Figure 3 The two adjacent pixel electrodes 430 located in the row direction L are axially symmetrical about the data line 300.
[0041] Specifically, in the top view of the substrate 10, a portion of one of the two adjacent pixel electrodes 430 located in the row direction L overlaps with one of the two adjacent first vias 500 located in the same row direction L, and a portion of the other pixel electrode 430 located in the row direction L does not overlap with the other of the two adjacent first vias 500 located in the same row direction L.
[0042] In this embodiment, reference Figure 4The substrate 10 further includes a buffer layer disposed on the substrate 100, a first gate metal layer 102, a first gate insulating layer 103 disposed on the side of the buffer layer away from the substrate 100 and covering the first gate metal layer 102, a semiconductor layer 104 disposed on the first gate insulating layer 103, a second gate insulating layer 105 disposed on the first gate insulating layer 103 and covering the semiconductor layer 104, a second gate metal layer 106 disposed on the second gate insulating layer 105, and a layer covering the buffer layer. The second gate metal layer 106 includes a first interlayer insulating layer 107, a source metal 108 disposed on the first interlayer insulating layer 107, a second interlayer insulating layer 109 covering the first interlayer insulating layer 107 and the source metal 108, a transition electrode 420 (drain metal 413), and a pixel electrode 430. The source metal 108 is connected to the source 412 of the semiconductor layer 104 through a third via, and the transition electrode 420 is connected to the drain 413 in the semiconductor layer 104 through a first via 500. Specifically, the first via 500 penetrates the second interlayer insulating layer 109, the first interlayer insulating layer 107, and part of the second gate insulating layer 105, so that the transition electrode 420 is electrically connected to the drain 413 of the semiconductor layer 104. The transition electrode 420 is electrically connected to the drain 413 of the semiconductor layer 104 through the first via. The pixel electrode 430 is electrically connected to the transition electrode 420. The third via penetrates the first interlayer insulating layer 107 and the second gate insulating layer 105, so that the source metal 108 is electrically connected to the source 412 on the semiconductor layer 104.
[0043] The specific embodiments of this application have been described in detail above. The embodiments disclosed above are merely preferred embodiments of this application. Those skilled in the art can make many modifications and improvements without departing from the concept of this application. All such modifications and improvements fall within the scope of protection defined by the claims of this application.
Claims
1. An array substrate, characterized by, The array substrate comprises: a substrate; a plurality of scan lines, which are arranged on the substrate in a column direction; a plurality of data lines, which are arranged on the substrate in a row direction; a plurality of pixel units, which are arranged between two adjacent data lines, and each of the pixel units comprises a thin film transistor, a transfer electrode and a pixel electrode, the gate of the thin film transistor is electrically connected with the scan line, the source of the thin film transistor is electrically connected with the data line, the transfer electrode is electrically connected with the drain of the thin film transistor through a first via hole penetrating between the film layer where the transfer electrode is located and the film layer where the drain is located, the pixel electrode is electrically connected with the transfer electrode through a second via hole penetrating between the film layer where the pixel electrode is located and the film layer where the transfer electrode is located, two adjacent transfer electrodes in the row direction are symmetrically centered on the intersection of the data line and the scan line, the drains of two adjacent thin film transistors in the row direction are symmetrically centered on the intersection of the data line and the scan line, and two adjacent pixel electrodes in the row direction are symmetrically arranged. In a top view of the array substrate, a part of the scan line overlaps a part of the first via hole.
2. The array substrate of claim 1, wherein, The transfer electrode extends a first protrusion toward the second via hole, and the first protrusion exceeds the edge of the second via hole.
3. The array substrate of claim 2, wherein, The ratio of the width of the first protrusion to the width of the opening of the second via hole ranges from 0.1 to 0.
2.
4. The array substrate of claim 1, wherein, The pixel electrode extends a second protrusion toward the second via hole, and the second protrusion exceeds the edge of the second via hole.
5. The array substrate of claim 4, wherein, The width of the second protrusion is 0.3 um to 0.6 um.
6. The array substrate of claim 4, wherein, The widths of the two second protrusions of two adjacent pixel electrodes in the row direction are the same.
7. The array substrate according to any one of claims 1 to 6, wherein, Two adjacent pixel electrodes in the row direction are symmetrically centered on the intersection of the data line and the scan line.
8. The array substrate according to any one of claims 1 to 6, wherein, Two adjacent pixel electrodes in the row direction are axially symmetric with the data line as the axis of symmetry.
9. The array substrate of claim 8, wherein, In a top view of the array substrate, a part of one of the two adjacent pixel electrodes in the row direction overlaps one of the two adjacent first via holes in the same row direction, and a part of the other of the two adjacent pixel electrodes in the row direction does not overlap the other of the two adjacent first via holes in the same row direction.
10. A display panel, characterized by, The array substrate of any one of claims 1-9 is included.