Processing device and electronic equipment

Abstract

The embodiment of the utility model discloses a processing device and electronic equipment, the electronic equipment comprises the processing device, the processing device comprises two processing boards, a co-processing board, a data transmission board and a back board; the back plate comprises a 3U VPX back plate with four grooves, and the processing plate, the co-processing plate and the data transmission plate are inserted into the groove positions of the four grooves side by side in the same direction; external interfaces of the co-processing board and the data transmission board comprise two paths of controller area network (CAN) buses, and the CAN buses are used for being connected with a satellite platform.

Description

Technical Field

[0001] This utility model relates to the field of integrated air-space-ground systems, and in particular to a processing device and electronic device. Background Technology

[0002] With the development of information technology, integrated space-air-ground information networks have become a research hotspot. Such networks can provide global coverage, high speed, and large capacity communication services, suitable for various environments and application scenarios. Low Earth Orbit (LEO) satellites can be used to conduct satellite-to-ground communication experiments, verifying the stability, reliability, and transmission efficiency of satellite networks, laying the foundation for widespread future applications. Currently, communication with satellite platforms can be achieved by carrying corresponding processing devices (payloads) on LEO satellites.

[0003] However, current processing devices typically use a single bus for information transmission when communicating with satellite platforms, which leads to a significant reduction in transmission performance. Utility Model Content

[0004] This utility model provides a processing device and an electronic device that can improve the transmission performance of the processing device.

[0005] The technical solution of this utility model embodiment is implemented as follows:

[0006] In a first aspect, this utility model proposes a processing device, which includes: two processing boards, a co-processing board, a data transmission board, and a backplate;

[0007] The backplane includes a 3U VPX backplane with 4 slots, in which the processing board, the coprocessing board and the data transmission board are inserted side by side in the same direction;

[0008] The external interfaces of the coprocessor board and the data transmission board include two CAN buses, which are used to connect to the satellite platform.

[0009] In the above scheme, the two processing boards are interconnected.

[0010] In the above scheme, the processing device further includes an (Input / Output, I / O) board; the I / O board provides one Ethernet interface to connect to the satellite platform; correspondingly,

[0011] The I / O board internally provides data interaction functions between the processing board, the coprocessor board, and the data transmission board.

[0012] In the above solution, the external interfaces of the backplane include one or more of a power supply interface, a comprehensive management interface, and a ground survey interface; correspondingly,

[0013] The backplate has one or more of the following functions:

[0014] Used to provide signal interconnection between boards in different slots;

[0015] Used to transfer external input signals to various boards.

[0016] In the above scheme, the coprocessor board includes one or more of the following: XC7Z045 chip, DDR4 SDRAM memory, watchdog chip, crystal oscillator, RS422 chip, single-channel level conversion chip, current detection chip, and Zynq-7000 series field-programmable gate array (FPGA).

[0017] In the above scheme, the processing board includes one or more of the following: FT-2000 / 4 chip, DC / DC converter, DDR power chip, DDR4 SDRAM memory, crystal oscillator, RS422 transmitting chip and RS422 receiving chip.

[0018] In the above scheme, the data transmission board includes a baseband section and a radio frequency section; wherein, the baseband section includes one or more of the following: XC7Z045-2FFG900I chip, AD9634 analog-to-digital converter, and Zynq-7000 series FPGA.

[0019] In the above scheme, the power input terminal of each board in the backplane includes a current limiting switch; wherein, the current limiting switch is used to shut off the power supply of the board when the instantaneous current value at power-on is higher than the preset current limit value of the board.

[0020] In the above scheme, the coprocessor board has one or more of the following functions:

[0021] Used for managing air, space, and ground data;

[0022] Used to manage the controller's health data.

[0023] In the above scheme, the processing board has one or more of the following functions:

[0024] Used to provide network computing power to the controller;

[0025] Data distribution function;

[0026] Data processing functions.

[0027] In the above scheme, the data transmission board is used to provide data conversion function for communication between the processing device and the ground station.

[0028] Secondly, this utility model proposes an electronic device, which includes the processing device described in the first aspect.

[0029] This utility model provides a processing device and an electronic device. The electronic device includes a processing device comprising two processing boards, a co-processing board, a data transmission board, and a backplane. The backplane is a 3U VPX backplane with four slots, in which the processing boards, co-processing boards, and data transmission boards are inserted side-by-side in the same direction. The external interfaces of the co-processing boards and data transmission boards include two CAN buses for connecting to a satellite platform. In other words, the processing device proposed in this utility model can include a backplane, which can be a 3U VPX backplane with four slots, allowing two processing boards, a co-processing board, and a data transmission board to be inserted side-by-side in the same direction. The external interfaces of the co-processing boards and data transmission boards include two CAN buses for connecting to a satellite platform. This utility model adds a dual-bus physical architecture to ensure that the processing device can use two CAN buses to connect to the satellite platform, thereby effectively improving the communication efficiency between the processing device and the satellite platform, and thus enhancing the transmission performance of the processing device. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the composition and structure of the processing device in this utility model. Figure 1 ;

[0031] Figure 2 This is a schematic diagram of the composition of the back plate in this utility model. Figure 1 ;

[0032] Figure 3 This is a schematic diagram of the composition of the back plate in this utility model. Figure 2 ;

[0033] Figure 4 This is a schematic diagram of the Ethernet connection in this utility model;

[0034] Figure 5 This is a schematic diagram of the external interface of the processing device in this utility model;

[0035] Figure 6 This is a schematic diagram of the hardware design of the processing board in this utility model;

[0036] Figure 7 This is a schematic diagram of the hardware design of the processing board in this utility model;

[0037] Figure 8 This is a schematic diagram of the data transmission board hardware design in this utility model;

[0038] Figure 9 This is a schematic diagram of the I / O board in this utility model;

[0039] Figure 10 This is a schematic diagram of the power supply relationship of the circuit board in this utility model;

[0040] Figure 11 This is a schematic diagram of the power supply principle of the circuit board in this utility model;

[0041] Figure 12 This is a schematic diagram of the composition and structure of the processing device in this utility model. Figure 2 ;

[0042] Figure 13 This is a schematic diagram of the composition and structure of the electronic device in this utility model. Detailed Implementation

[0043] The technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the relevant utility model and not intended to limit the utility model. Furthermore, it should be noted that, for ease of description, only the parts related to the relevant utility model are shown in the accompanying drawings.

[0044] With the development of information technology, integrated space-air-ground information networks have become a research hotspot. Such networks can provide global coverage, high speed, and large capacity communication services, suitable for various environments and application scenarios. LEO satellites can be used to conduct space-to-ground communication experiments, verifying the stability, reliability, and transmission efficiency of satellite networks, laying the foundation for widespread future applications. Currently, communication with satellite platforms can be achieved by mounting corresponding processing devices (payloads) on LEO satellites.

[0045] However, current processing devices typically use a single bus for information transmission when communicating with satellite platforms, which leads to a significant reduction in transmission performance.

[0046] To address the aforementioned problems, this invention proposes a processing device and an electronic device. The electronic device includes a processing unit comprising two processing boards, a co-processing board, a data transmission board, and a backplane. The backplane is a 3U VPX backplane with four slots, in which the processing boards, co-processing boards, and data transmission boards are inserted side-by-side in the same direction. The external interfaces of the co-processing boards and data transmission boards include two CAN buses for connecting to a satellite platform. In other words, the processing device proposed in this invention can include a backplane, which can be a 3U VPX backplane with four slots, allowing two processing boards, a co-processing board, and a data transmission board to be inserted side-by-side in the same direction. The two CAN buses included in the external interfaces of the co-processing boards and data transmission boards can be used to connect to a satellite platform. This invention adds a dual-bus physical architecture to ensure that the processing device can use two CAN buses to connect to the satellite platform, thereby effectively improving the communication efficiency between the processing device and the satellite platform, and ultimately enhancing the transmission performance of the processing device.

[0047] In the description of the embodiments of this utility model, any references to direction and orientation are for ease of description only and should not be construed as any limitation on the scope of protection of this utility model. Related terms, such as “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “upper,” “lower,” “top,” and “bottom,” and their derivatives (such as “horizontally,” “downward,” “upward,” etc.), should be interpreted as the orientation discussed as described in the utility model or shown in the drawings. These related terms are for ease of description only and should not be considered as explanations of instruments or equipment or specific operations in a particular orientation. Terms such as “attached,” “fixed to,” “connected,” and “interconnected” refer to a relationship in which a structure is directly or indirectly fixed or attached to another structure by means of an insertion structure, unless explicitly described, including movable, fixed, or associated structures. Furthermore, the features and advantages of this utility model are described with reference to preferred embodiments. Therefore, the preferred embodiments describe possible, non-limiting combinations of features, which may exist independently or in combination. This invention is not particularly limited to the preferred embodiments. The scope of this invention is defined by the claims.

[0048] This utility model embodiment provides a processing device, which may include: two processing boards, a coprocessing board, a data transmission board, and a backplane.

[0049] It is understood that, in the embodiments of this utility model, the processing device can be deployed with spaceborne core network functions. The processing device can be composed of multiple functional modules, and under unified task scheduling and management, it can complete the interaction of space-ground information.

[0050] It should be noted that, in the embodiments of this utility model, the backplane may include a 3U VPX backplane with 4 slots, and two processing boards, coprocessing boards and data transmission boards may be inserted side by side in the same direction in the 4 slots.

[0051] It should be noted that, in the embodiments of this utility model, the two processing boards can be interconnected, thereby improving the computing power of the processing device.

[0052] It should be noted that, in the embodiments of this utility model, the external interfaces of the coprocessor board and the data transmission board include two CAN buses, which are used to connect to the satellite platform.

[0053] In other words, in the embodiments of this utility model, the external interfaces of both the coprocessor board and the data transmission board can include two CAN buses with a speed of 500kbps, so that the coprocessor board and the data transmission board can be connected to the satellite platform using two buses. The embodiments of this utility model do not specifically limit the transmission rate of the bus.

[0054] It should be noted that, in the embodiments of this utility model, the processing device may further include an input / output (I / O) board; the I / O board can provide one Ethernet interface to connect to the satellite platform externally; correspondingly, the I / O board can provide data interaction functions between the processing board, the coprocessing board, and the data transmission board internally. The embodiments of this utility model do not specifically limit the number and type of modules included in the processing device.

[0055] It should be noted that, in the embodiments of this utility model, the external interfaces of the backplane include one or more of a power supply interface, a comprehensive management interface, and a ground survey interface; correspondingly,

[0056] The back panel has one or more of the following functions:

[0057] Used to provide signal interconnection between boards in different slots;

[0058] Used to transfer external input signals to various boards.

[0059] Furthermore, in the embodiments of this utility model, the coprocessor board may include one or more of the following: an XC7Z045 chip, a DDR4 SDRAM memory, a watchdog chip, a crystal oscillator, an RS422 chip, a single-channel level conversion chip, a current detection chip, and a Zynq-7000 series field-programmable gate array (FPGA). The coprocessor board may also include other devices. The embodiments of this utility model do not specifically limit the number and type of devices included in the coprocessor board.

[0060] Furthermore, in embodiments of this utility model, the processing board may include one or more of the following: an FT-2000 / 4 chip, a DC / DC converter, a DDR power supply chip, a DDR4 SDRAM memory, a crystal oscillator, an RS422 transmitting chip, and an RS422 receiving chip. This utility model embodiment does not specifically limit the number and type of devices included in the processing board.

[0061] Furthermore, in the embodiments of this utility model, the data transmission board may include a baseband section and a radio frequency section; wherein, the baseband section includes one or more of the following: XC7Z045-2FFG900I chip, AD9634 analog-to-digital converter, and Zynq-7000 series FPGA. The embodiments of this utility model do not specifically limit the number and type of devices included in the data transmission board.

[0062] It should be noted that, in the embodiments of this utility model, the power input terminal of each board in the backplane may include a current limiting switch; wherein, the current limiting switch is used to shut off the power supply of the board when the instantaneous current value at power-on is higher than the preset current limit value of the board, thereby isolating short circuits and single event latch-up (SEL) phenomena from the entire satellite.

[0063] It should be noted that, in the embodiments of this utility model, the function of the coprocessor board may include one or more of the following: for managing air-space-ground data; for managing the health data of the controller. The embodiments of this utility model do not specifically limit the function of the coprocessor board.

[0064] It should be noted that, in the embodiments of this utility model, the processing board may include one or more of the following functions: providing network computing power to the controller; data distribution function. The embodiments of this utility model do not specifically limit the functions of the processing board.

[0065] It should be noted that, in the embodiments of this utility model, the data transmission board can be used to provide data conversion function for communication between the processing device and the ground station. The embodiments of this utility model do not specifically limit the function of the data transmission board.

[0066] Figure 1 This is a schematic diagram of the composition and structure of the processing device in this utility model. Figure 1 ,like Figure 1 As shown, the processing device 10 may include two processing boards 11, a coprocessing board 12, a data transmission board 13, and a backplane 14.

[0067] Figure 2 This is a schematic diagram of the composition of the back plate in this utility model. Figure 1 ,like Figure 2As shown, the backplane 14 includes a 3UVPX backplane with 4 slots. The processing board 11, the coprocessor board 12 and the data transmission board 13 are inserted side by side in the same direction in the 4 slots.

[0068] It should be noted that in this utility model, the back plate 14 in the processing device 10 can be any type of back plate, such as a 4-slot 3U VPX back plate, or a 6-slot 3U VPX back plate. This utility model embodiment does not limit the type of back plate.

[0069] It should be noted that, in the embodiments of this utility model, the two processing boards 11 can be interconnected, thereby improving the computing power of the processing device.

[0070] It should be noted that, in the embodiments of this utility model, the processing device 10 further includes an IO board 15; the IO board 15 can provide one Ethernet interface to connect with the satellite platform 20; correspondingly, the IO board 15 can also provide data interaction functions between the processing board, the coprocessing board and the data transmission board.

[0071] For example, in an embodiment of this utility model, Figure 3 This is a schematic diagram of the composition of the back plate in this utility model. Figure 2 The structure adopts a single-row board plug-in mode. All boards (i.e., processing board 11, coprocessing board 12, data transmission board 13) are plugged in and out in the same direction. The chassis is designed with 4 slots. All external lines are implemented through the backplane and the rear IO board 15. The backplane wiring can realize the inter-board communication of each board, and the IO board realizes the internal and external interface interconnection function.

[0072] It should be noted that, in the embodiments of this utility model, Figure 4 This is a schematic diagram of the Ethernet connection in this utility model, as shown below. Figure 4 As shown, the processing board 11 forms a cold backup relationship between boards. The processing board 11, the coprocessing board 12, and the data transmission board 13 use Ethernet interfaces to complete cross-access to each unit within the single board. The IO board 15 (i.e., the switching module) can provide one Ethernet interface to connect with the satellite platform 20 (i.e., the satellite service module) to realize network communication with the satellite platform 20.

[0073] It should be noted that, in the embodiments of this utility model, the external interface of the backplane 14 includes one or more of a power supply interface, a comprehensive management interface, and a ground survey interface; correspondingly, the functions of the backplane include one or more of the following: it can be used to provide signal interconnection between boards in different slots; it can be used to transfer external input signals to each board.

[0074] For example, in an embodiment of this utility model, Figure 5 This is a schematic diagram of the external interface of the processing device in this utility model, as shown below. Figure 5 As shown, the external interfaces of the backplane 14 may include a power supply interface (i.e., X01), a comprehensive management interface (i.e., X02), and a ground survey interface (i.e., X03). This embodiment of the utility model does not specifically limit the number and type of interfaces.

[0075] For example, in an embodiment of the present invention, the external interface of the back plate 14 can be represented by Table 1 below.

[0076] Table 1

[0077] Serial Number interface Interface type Corresponding interface 1 X01 J30J-25ZKNP5-J Power supply from energy modules 2 X02 J30J-37ZKNP5-J Integrated Management Interface 3 X03 J30J-51ZKNP5-J Ground survey interface 4 X04 SMA Data transmission 5 X05 SMA Data transmission reception

[0078] Furthermore, in embodiments of this utility model, Figure 6 This is a schematic diagram of the hardware design of the processing board in this utility model, as shown below. Figure 6 As shown, the coprocessor board 12 may include one or more of the following: an XC7Z045 chip, a Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), a watchdog chip, a crystal oscillator, an RS422 chip, a single-channel level conversion chip, a current detection chip, and a Zynq-7000 series FPGA. The coprocessor board 12 may also include other devices. This embodiment of the present invention does not specifically limit the number and type of devices included in the coprocessor board 12.

[0079] It should be noted that, in the embodiments of this utility model, the external interfaces of the coprocessor board 12 are shown in Table 2 below. The embodiments of this utility model do not specifically limit the number and type of external interfaces of the coprocessor board 12.

[0080] Table 2

[0081]

[0082] It should be noted that, in the embodiments of this utility model, as shown in Table 2 above, the CAN bus in the external interface of the coprocessor board 12 includes two channels, that is, the coprocessor board 12 can be connected to the satellite platform 20 through two channels, thereby improving the data transmission efficiency. That is, this utility model embodiment adds a dual-bus physical architecture to the field of satellite communication for the first time, so as to ensure that communication can be carried out in two ways.

[0083] It should be noted that, in the embodiments of this utility model, in the design of the coprocessor board 12, the processor can be a Xilinx Zynq-7000 series FPGA XQ7Z045-1FFG900, packaged in a BGA900. This series of chips integrates a dual-core processor on a single chip. Cortex TM The Zyqn processor features an A9 processor and a 28nm programmable logic device. Each Central Processing Unit (CPU) has a processing power of 2.5 DMIPS / MHz and a clock speed of up to 1GHz. It integrates a rich set of interfaces and peripherals, with the internal programmable logic device being a Kintex-7 FPGA. The Zyqn processor integrates interface circuits including Universal Serial Bus (USB), Gigabit Ethernet (GbE), CAN, Universal Asynchronous Receiver / Transmitter (UART), I2C, Serial Peripheral Interface (SPI), memory interface, and General Purpose Input / Output (GPIO).

[0084] It should be noted that, in this embodiment of the invention, the Zynq-7000 can be externally connected to two 32-bit 1Gb Double-Data-Rate Three Synchronous Dynamic Random Access Memory (DDR3 SDRAM) via a DDR3 interface. The DDR3 model can be MT41K256M16HA-125IT, and the board features a magnetic random access memory (MRAM) with high-speed read / write and high integration, capable of cyclic writing. The MRAM can be MR4A16BCMA35 with a capacity of 16Mb. The ZYNQ7000 supports an embedded multi-media card (eMMC) interface. The eMMC chip can be MTFC32GAKAECN-4M IT with a capacity of 32GB, and the VDD and VDDQ power supplies can be 3.3V.

[0085] For example, in the embodiments of this utility model, the main component list of the coprocessor board 12 is shown in Table 3 below. This utility model embodiment does not specifically limit the number and type of components included in the coprocessor board 12.

[0086] Table 3

[0087]

[0088]

[0089]

[0090] Furthermore, in the embodiments of this utility model, the processing board 11 may include one or more of the following: FT-2000 / 4 chip, DC / DC converter, DDR power chip, DDR4 SDRAM memory, crystal oscillator, RS422 transmitting chip and RS422 receiving chip. The embodiments of this utility model do not specifically limit the number and type of devices included in the processing board 11.

[0091] For example, in an embodiment of this utility model, Figure 7 This is a schematic diagram of the hardware design of the processing board in this utility model, as shown below. Figure 7 As shown, the processing board 11 can use Phytium's FT-2000 / 4 high-performance processor as the main controller. Its main function is to provide computing power for Tiandi Communication, carry out communication service business, and manage and execute different business modes. It features onboard dual-channel 8GB DDR4 memory chips. The main external interfaces of the board include I2C, RS422, and Gigabit Ethernet. The CJC6811A can be a Cortex-based microcontroller chip, SSD indicates a solid-state drive, SATA III indicates a solid-state drive interface, and WX1860 indicates the main controller chip, primarily used in network communication equipment.

[0092] For example, in the embodiments of this utility model, the external interfaces of the processing board 11 can be as shown in Table 4 below. The embodiments of this utility model do not specifically limit the number and type of external interfaces of the processing board 11.

[0093] Table 4

[0094]

[0095] For example, in an embodiment of the present invention, the main components of the processing board 11 are listed in Table 5 below. The present invention does not specifically limit the number and type of components included in the processing board 11.

[0096] Table 5

[0097]

[0098]

[0099] It should be noted that, in the embodiments of this utility model, as shown in Table 5, the processor of the processing board 11 can be the Phytium FT-2000 / 4 desktop high-performance processor, with an industrial-grade quality level, an operating temperature range of -40℃ to 85℃, and an FCBGA1144 package. The processor core obtains the internal temperature of the chip through a TS sensor and adjusts the speed of the heat sink fan according to the temperature change. When the temperature exceeds the threshold, the CPU core frequency can be reduced; when the temperature exceeds the limit temperature, the CPU powers down. The DDR4 chip can be the Micron MT40A256M16LY-062E AUT:F, with a power supply voltage of 1.25V, a 64-bit data bus width, and support for error checking and correction. The system interface card (SSD) chip is used to store the FT-2000 / 4 processor's boot files. A Cypress S25FL512SAGMFVG13 chip is selected, with an automotive-grade quality rating, an SPI data interface, and a storage capacity of 512Mb. A Solid State Drive (SSD) chip is used to store the FT-2000 / 4 processor's system files. A Komei CMFDJNWT51600XT256 chip can be selected, with an industrial-grade quality rating and a storage capacity of 256GB. This chip can meet the system's operational and fast read / write requirements, and its operating temperature range is -40°C to +85°C. A network interface card (NIC) chip is used to expand the system's network interface. A WX1860AL4 chip can be selected, with an industrial-grade quality rating, supporting PCIe Gen2x4 host interface, GbE network interface, 1000Base-T / 100Base-T / 10Base-T, RGMII, and network protocol acceleration (Transmission Control Protocol). Protocol (TCP) / User Datagram Protocol (UDP) and Internet Protocol (IP) are used for interconnection between networks. It supports SM2 / SM3 / SM4 algorithms. The clock extension chip is used to distribute the clocks of various functional modules of the board. The AU5411A-QMR from Aura Technologies can be selected. The quality level is extended industrial grade, with 10 output differential buffers and less than 50fs of additional jitter.

[0100] Furthermore, in an embodiment of this utility model, the data transmission board 13 may include a baseband section 21 and a radio frequency section 22; wherein, the baseband section 21 includes one or more of the following: an XC7Z045-2FFG900I chip, an AD9634 analog-to-digital converter, and a Zynq-7000 series FPGA.

[0101] For example, in an embodiment of this utility model, Figure 8 This is a schematic diagram of the data transmission board hardware design in this utility model, as shown below. Figure 8 As shown, the data transmission board 13 can realize the ground and space data transmission and reception functions of the core experimental payload of the 6th Generation Mobile Networks (6G). The board can adopt the 3UVPX standard and is divided into a baseband section 21 and an RF section 22 according to its functions. The baseband section 21 can realize two-channel high-speed intermediate frequency sampling, high-speed real-time processing, and modulation signal transmission. The board uses two ADI AD9634 chips, which can realize two-channel 12-bit 250MSPS signal sampling functions. It uses one Xilinx XC7Z045-2FFG900I high-performance SOC chip, which completes digital channelization reception and other processing functions in real time. The clock chip uses ADI's AD9516-1 to divide the clock frequency to the AD, DA, and FPGA. The modulated signal is output to the RF unit through one ADI AD9746 DA chip. The RF module performs up-conversion and down-conversion signal processing, connecting the filtered intermediate frequency signal to the baseband board via an inter-board RF connector. The baseband board controls the RF channel. This board is mainly intended for applications such as digital channel receivers, software radio, direct RF storage, and broadband signal acquisition. In the RF unit, LNA stands for Low Noise Amplifier, FLT stands for FLT for obtaining a stable voltage after filtering, ADC stands for Analog-to-Digital Converter, SPI stands for Serial Peripheral Interface, and Mixer stands for Mixer.

[0102] It should be noted that, in the embodiments of this utility model, the external interfaces of the data transmission board 13 can be as shown in Table 6 below. The embodiments of this utility model do not specifically limit the number and type of external interfaces of the data transmission board 13.

[0103] Table 6

[0104]

[0105] It should be noted that, in the embodiments of this utility model, as shown in Table 6 above, the CAN bus in the external interface of the data transmission board 13 includes two channels, that is, the data transmission board 13 can be connected to the satellite platform 20 through two channels to ensure that communication can be carried out in two ways, thereby improving the data transmission efficiency.

[0106] It should be noted that, in the embodiments of this utility model, in the design of the baseband section 21 of the data transmission board 13, the processor can be a Xilinx Zynq-7000 series FPGA XQ7Z045-1FFG900I, packaged as a BGA900I. This series of chips integrates a dual-core processor in a single chip. Cortex TM The Zyqn processor features an A9 processor and a 28nm programmable logic device. Each CPU has a processing power of 2.5 DMIPS / MHz and a clock speed of up to 1GHz. It integrates a rich set of interfaces and peripherals, with the internal programmable logic device being a Kintex-7 FPGA. The Zyqn processor integrates interface circuits such as USB, GbE, CAN, UART, I2C, SPI, memory interface, and GPIO.

[0107] For example, in the embodiments of this utility model, the main component list of the data transmission board 13 is shown in Table 7 below. This utility model embodiment does not specifically limit the number and type of components included in the data transmission board 13.

[0108] Table 7

[0109]

[0110]

[0111]

[0112] Furthermore, in an embodiment of this utility model, the processing device 10 further includes an IO plate 15; Figure 9 This is a schematic diagram of the I / O board in this utility model, as shown below. Figure 9 As shown, the main functions of IO board 15 include: providing a conversion interface for internal and external signals; the internal board needs to bring out 2 CAN buses, 2 Ethernet interfaces and a debug serial port through the specified connectors.

[0113] Furthermore, in embodiments of this utility model, the processing board 11 may include one or more of the following functions: providing network computing power to the controller; data distribution; and data processing.

[0114] Furthermore, in embodiments of this utility model, the coprocessor board 12 may include one or more of the following functions: managing air-space-ground data; and managing the health data of the controller.

[0115] It should be noted that in the embodiments of this utility model, the coprocessor board 12 is the management center of the processing device 10, which can be responsible for the management of uplink and downlink data, data storage management, and controller health management, etc. It can use the internal solid-state memory to store uplink and downlink data, application backup, and data backup.

[0116] It should be noted that, in the embodiments of this utility model, the data transmission board 13 can be used to provide data conversion function for communication between the processing device and the ground station.

[0117] It should be noted that, in the embodiments of this utility model, the power input terminal of each board in the backplane 14 includes a current limiting switch; wherein, the current limiting switch can be used to shut off the power supply of the board when the instantaneous current value at power-on is higher than the preset current limit value of the board.

[0118] For example, in an embodiment of this utility model, Figure 10 This is a schematic diagram of the power supply relationship of the circuit board in this utility model, as shown below. Figure 10 As shown, for the safety of the processing device and the entire satellite, a current limiting switch can be designed at the power input terminal of each board. When the instantaneous current at startup exceeds the current limit value of the board's fuse, the current limiting circuit shuts off the power supply to the board, thus isolating short circuits and single-event latch-up phenomena from the entire satellite. The boards can refer to the processing board 11, coprocessing board 12, and data transmission board 13 inserted in the backplane 14.

[0119] For example, in the embodiments of this utility model, the power supply table of each board is shown in Table 8 below. The embodiments of this utility model do not specifically limit the size of the current limiting value of the fuse.

[0120] Table 8

[0121]

[0122] For example, in an embodiment of this utility model, Figure 11 This is a schematic diagram of the power supply principle of the circuit board in this utility model, as shown below. Figure 11 As shown, the power supply design of each board in the backplane 14 is as follows: Figure 11 As shown; the TPS2421 chip can be used for hot-swappable power management, providing highly integrated power management and protection functions, and is suitable for a voltage range of 3.0V to 20V. The TPS2421 chip has a variety of protection features, including non-current limiting fault threshold, hard current limiting, and fault timer, which can effectively protect the system from short circuits and other damage.

[0123] In other words, in the embodiments of this utility model, on the one hand, the external interfaces of the coprocessor board 12 and the data transmission board 13 include two CAN buses, meaning that the coprocessor board 12 and the data transmission board 13 can be connected to the satellite platform 20 through two buses, thereby improving data transmission efficiency. That is, this utility model embodiment adds a dual-bus physical architecture to the field of satellite communication for the first time, to ensure that communication can be carried out in two ways. On the other hand, the power input terminal of each board in the backplane can include a current limiting switch; wherein, the current limiting switch is used to shut off the power supply of the board when the instantaneous current value of the power-on is higher than the preset current limit value of the board, thereby isolating short circuits and single event latch-up (SEL) phenomena from the entire satellite; and the backplane design on the processing device in this utility model embodiment can decouple the processing board from the satellite service module.

[0124] This invention proposes a processing device comprising: two processing boards, a co-processing board, a data transmission board, and a backplane. The backplane is a 3U VPX backplane with four slots, in which the processing boards, co-processing boards, and data transmission boards are inserted side-by-side in the same direction. The external interfaces of the co-processing boards and data transmission boards include two CAN buses for connecting to a satellite platform. In other words, the processing device proposed in this invention can include a backplane, which can be a 3U VPX backplane with four slots, allowing two processing boards, a co-processing board, and a data transmission board to be inserted side-by-side in the same direction. The external interfaces of the co-processing boards and data transmission boards include two CAN buses for connecting to a satellite platform. This invention adds a dual-bus physical architecture to ensure that the processing device can use two CAN buses to connect to the satellite platform, thereby effectively improving the communication efficiency between the processing device and the satellite platform, and ultimately enhancing the transmission performance of the processing device.

[0125] Based on the above embodiments, another embodiment of the present invention proposes a processing device. Figure 12 This is a schematic diagram of the composition and structure of the processing device in this utility model. Figure 2 ,like Figure 12 As shown, the processing device 10 (i.e., the 6G core experimental payload), as the main information processing and acquisition center for space-to-ground communication, is interconnected with the components of the satellite platform 20 as follows: Figure 12As shown, the processing device 10 may include two processing boards 11, a coprocessor board 12, a data transmission board 13 (i.e., a data transmission module), and a switching chip (i.e., an I / O board 15). The two processing boards 11 can also be interconnected to improve the computing power of the 6G core test payload. User plane functions (UPF) and operating systems can be deployed on the processing boards 11. The high-performance processing board, including the system, operating system, and processing hardware platform, can perform information processing, analysis, and forwarding functions for the 6G core test payload. It summarizes data types and statuses and communicates with the data transmission board 13 via the switching module (IO board 15), which then transmits status information to the ground control station. The co-processing module 12 primarily provides controller management and application data management functions. It monitors the voltage, current, and temperature of individual units to manage the core network's health status. It has a built-in large-capacity SSD to back up the operating systems of each individual controller unit, managing application data, uplink and downlink messages, and system and application backups. The switching module (IO board 15) provides a data interaction node for the 6G core test payload. It has one external Ethernet interface connected to the satellite platform 20 and internally provides data interaction functions between the two processing boards 11, the co-processing board 12, and the data transmission board 13. Figure 12 As shown, the data transmission board 13 can complete the space-to-ground communication task together with the external antenna. The data transmission board 13 can be connected to an external satellite antenna to form a space-to-ground communication with the ground station. According to the calculation and analysis of the uplink and downlink remote control link margin, the transmission power of the 1.2-meter portable ground station is 40W. At the same time, it ensures that the uplink and downlink code rates are 1Mbps under the condition of moderate rain and rain attenuation. The system has a link margin of about 4.01dB.

[0126] For example, in an embodiment of this utility model, the composition structure of the processing device can be as shown in Table 9 below. The processing device 10 can be subdivided into 5 parts, namely, processing board 11, coprocessing board 12, data transmission board 13, backplane 14 and IO board 15 (switching module).

[0127] Table 9

[0128]

[0129] It should be noted that in the embodiments of this utility model, the processing device can adopt the 3U VPX standard and adopt a single-row board plug-in mode structural design. All boards can be plugged in and out in the same direction side by side. The chassis is designed with 4 slots, and the external lines are all realized through the back plate 14 and the rear IO board 15.

[0130] It should be noted that, in the embodiments of this utility model, the core of the 6G core test payload (i.e., processing device 10) is the processing board 11 and the coprocessor board 12, which are designed and implemented as a high-performance Phytium FT-2000 / 4 processing board and a high-performance Z7 coprocessor board (XC7Z045). The Phytium processing board has a QSPI Flash BOOT memory with one physical medium and an onboard SSD storage device with a capacity of 256GB, used to store the operating system, applications, and other user data; the Z7 coprocessor board has a NorFlash program memory with two physical mediums, storing BOOT, operating system, and APP, and an onboard SSD storage device with a capacity of 256GB, storing the system backup and application data of the core controller, and switching the operating system and APP on different storage devices through a dog bark reset; the data transmission board has a NorFlash program memory with one physical medium, storing BOOT, operating system, and APP, and switching multiple operating systems and APP on storage devices through a dog bark reset. The operating system of the Phytium FT-2000 / 4 processing board is the Galaxy Kylin V10 server version, while the operating systems of the coprocessor board 12 (XC7Z045) and the data transmission board 13 (XC7Z045) can be Linux. The 6G core test payload IO board 15 contains a switching module and supports 8 Gigabit Ethernet interfaces, which can be connected to two Phytium processing boards 11, coprocessor board 12, data transmission board 13, and 1 external interface to connect to the satellite integrated management platform. The data transmission board 13 completes the baseband demodulation, decoding + encoding and modulation of the satellite transceiver. The processed data is transmitted to the processing board 11 for analysis and processing via Ethernet interface or CAN bus.

[0131] It should be noted that in the embodiments of this utility model, the external interface of the coprocessor board 12 and the data transmission board 13 includes two CAN buses, that is, the coprocessor board 12 and the data transmission board 13 can be connected to the satellite platform 20 through two buses, thereby improving the data transmission efficiency.

[0132] In other words, in the embodiments of this utility model, on the one hand, the external interfaces of the coprocessor board 12 and the data transmission board 13 include two CAN buses, meaning that the coprocessor board 12 and the data transmission board 13 can be connected to the satellite platform 20 through two buses, thereby improving data transmission efficiency. That is, this utility model embodiment adds a dual-bus physical architecture to the field of satellite communication for the first time, to ensure that communication can be carried out in two ways. On the other hand, the power input terminal of each board in the backplane can include a current limiting switch; wherein, the current limiting switch is used to shut off the power supply of the board when the instantaneous current value of the power-on is higher than the preset current limit value of the board, thereby isolating short circuits and single event latch-up (SEL) phenomena from the entire satellite; and the backplane design on the processing device in this utility model embodiment can decouple the processing board from the satellite service module.

[0133] This invention proposes a processing device comprising: two processing boards, a co-processing board, a data transmission board, and a backplane. The backplane is a 3U VPX backplane with four slots, in which the processing boards, co-processing boards, and data transmission boards are inserted side-by-side in the same direction. The external interfaces of the co-processing boards and data transmission boards include two CAN buses for connecting to a satellite platform. In other words, the processing device proposed in this invention can include a backplane, which can be a 3U VPX backplane with four slots, allowing two processing boards, a co-processing board, and a data transmission board to be inserted side-by-side in the same direction. The external interfaces of the co-processing boards and data transmission boards include two CAN buses for connecting to a satellite platform. This invention adds a dual-bus physical architecture to ensure that the processing device can use two CAN buses to connect to the satellite platform, thereby effectively improving the communication efficiency between the processing device and the satellite platform, and ultimately enhancing the transmission performance of the processing device.

[0134] Based on the above embodiments, another embodiment of the present invention provides an electronic device, wherein the electronic device includes a processing device.

[0135] Figure 13 This is a schematic diagram of the composition structure of the electronic device in this utility model, as shown below. Figure 13 As shown, the electronic device 30 includes a processing unit 10, which may include two processing boards 11, a coprocessing board 12, a data transmission board 13, and a backplane 14.

[0136] It should be noted that, in the embodiments of this utility model, the back panel 14 includes a 3U VPX back panel with 4 slots, and the processing board 11, the coprocessing board 12 and the data transmission board 13 are inserted side by side in the same direction in the slots.

[0137] It should be noted that, in the embodiments of this utility model, the external interfaces of the coprocessor board 12 and the data transmission board 13 include two CAN buses, which are used to connect to the satellite platform 20.

[0138] It should be noted that, in the embodiments of this utility model, the processing device 10 further includes an IO board 15; the IO board 15 can provide one Ethernet interface to connect with the satellite platform 20; correspondingly, the IO board 15 can also provide data interaction functions between the processing board, the coprocessing board and the data transmission board.

[0139] It should be noted that, in the embodiments of this utility model, the two processing boards 11 are interconnected.

[0140] It should be noted that, in the embodiments of this utility model, the power input terminal of each board in the backplane 14 includes a current limiting switch; wherein, the current limiting switch can be used to shut off the power supply of the board when the instantaneous current value at power-on is higher than the preset current limit value of the board.

[0141] For example, in embodiments of this utility model, such as Figure 10 As shown, for the safety of the processing device and the entire satellite, a current limiting switch can be designed at the power input terminal of each board. When the instantaneous current at startup exceeds the current limit value of the board's fuse, the current limiting circuit shuts off the power supply to the board, thus isolating short circuits and single-event latch-up phenomena from the entire satellite. The boards can refer to the processing board 11, coprocessing board 12, and data transmission board 13 inserted in the backplane 14.

[0142] In other words, based on the processing device 10 in the electronic device 30 proposed in this utility model, on the one hand, the external interface of the coprocessor board 12 and the data transmission board 13 in the processing device 10 includes two CAN buses, that is, the coprocessor board 12 and the data transmission board 13 can be connected to the satellite platform through two buses, thereby improving the data transmission efficiency. That is, this utility model embodiment adds a dual-bus physical architecture to the field of satellite communication for the first time, so as to ensure that communication can be carried out in two interface ways. On the other hand, the power input terminal of each board in the backplane 14 can include a current limiting switch; wherein, the current limiting switch is used to shut off the power supply of the board when the instantaneous current value of the power-on is higher than the preset current limit value of the board, thereby isolating short circuit and single event latch-up (SEL) from the entire satellite; and the backplane 14 designed on the processing device in this utility model embodiment can decouple the processing board 11 from the satellite service module.

[0143] This invention proposes an electronic device comprising a processing unit, which includes two processing boards, a co-processing board, a data transmission board, and a backplane. The backplane is a 3U VPX backplane with four slots, in which the processing boards, co-processing boards, and data transmission boards are inserted side-by-side in the same direction. The external interfaces of the co-processing boards and data transmission boards include two CAN buses for connecting to a satellite platform. In other words, the processing unit proposed in this invention can include a backplane, which can be a 3U VPX backplane with four slots, allowing two processing boards, a co-processing board, and a data transmission board to be inserted side-by-side in the same direction. The external interfaces of the co-processing boards and data transmission boards include two CAN buses for connecting to a satellite platform. This invention adds a dual-bus physical architecture to ensure that the processing unit can use two CAN buses to connect to the satellite platform, thereby effectively improving the communication efficiency between the processing unit and the satellite platform, and ultimately enhancing the transmission performance of the processing unit.

[0144] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the scope of protection of the present utility model.

Claims

1. A processing device, characterized by, The processing device comprises two processing boards, a coprocessing board, a data transmission board and a backplane; The backplane comprises a 4-slot 3U VPX backplane, and the processing board, the coprocessing board and the data transmission board are inserted into the 4-slot slots in parallel and in the same direction; The external interface of the coprocessing board and the data transmission board comprises two controller area networks (CAN) buses, which are used to connect with a satellite platform.

2. The processing device according to claim 1, wherein, The two processing boards are interconnected.

3. The processing device of claim 1, wherein, The processing device further comprises an input / output (IO) board; The IO board provides an Ethernet interface to the outside for connecting with the satellite platform; correspondingly, The IO board provides data interaction functions among the processing board, the coprocessing board and the data transmission board.

4. The processing device according to claim 2, wherein, The external interface of the backplane comprises one or more of a power supply interface, an integrated management interface and a ground measurement interface; correspondingly, The functions of the backplane comprise one or more of the following: providing signal interconnection between different slot boards; transferring external input signals to each board.

5. The processing device according to claim 1, wherein, The coprocessing board comprises one or more of an XC7Z045 chip, a DDR4 SDRAM memory, a watchdog chip, a crystal oscillator, an RS422 chip, a single-level conversion chip, a current detection chip and a field programmable gate array (FPGA) of the Zynq-7000 series.

6. The processing device according to claim 1, wherein, The processing board comprises one or more of an FT-2000 / 4 chip, a DC / DC converter, a DDR power supply chip, a DDR4 SDRAM memory, a crystal oscillator, an RS422 sending chip and an RS422 receiving chip.

7. The processing device according to claim 1, wherein, The data transmission board comprises a baseband part and a radio frequency part; wherein the baseband part comprises one or more of an XC7Z045-2FFG900I chip, an AD9634 analog-to-digital converter and an FPGA of the Zynq-7000 series.

8. The processing device according to claim 2, wherein, The power input end of each board in the backplane comprises a current limiting switch; wherein the current limiting switch is used to turn off the power supply of the board when the instantaneous current value of the startup is higher than the preset current limiting value of the board.

9. The processing device according to claim 5, wherein, The functions of the coprocessing board comprise one or more of the following: managing space, air and ground data; managing health data of the controller.

10. The processing device according to claim 6, wherein, The functions of the processing board comprise one or more of the following: providing network computing power function to the controller; data distribution function; data processing function.

11. The processing device according to claim 7, wherein, The data transceiver board is used to provide data conversion function for communication between the processing device and a ground station.

12. An electronic device, comprising: The electronic device comprises the processing device according to any one of claims 1 to 11.

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