GIP circuit and display device
By setting an anomaly detection module in the GIP circuit of the display screen, anomalies in the output signal of the row gate drive module of any clock signal line can be detected, which solves the problem that other row anomalies cannot be detected in the prior art, realizes fast reset and elimination of display anomalies, and enhances product competitiveness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-19
- Publication Date
- 2026-03-20
AI Technical Summary
The existing display's GIP circuit only connects the output line of the last row to the driver IC, making it unable to detect abnormal output signals from other rows cascaded with clock signal lines, thus making it impossible to eliminate display abnormalities.
By setting up an anomaly detection module corresponding to multiple clock signal lines and utilizing the cascaded relationship of gate drive modules, an anomaly in the output signal of the gate drive module of any clock signal line row can be detected, and a rapid reset can be performed without changing the detection pin of the existing driver IC.
It enables rapid detection and elimination of abnormal output signals from the row gate drive module on any clock signal line, improving the detection effect of display abnormalities and enhancing product competitiveness.
Smart Images
Figure CN224020427U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the abnormal detection technical field of display panel, especially GIP circuit and display device. BACKGROUND
[0002] In the use process of the display screen, there may be related adverse, such as in the process of gate drive, the interference of static electricity or external signal drive, etc., the abnormal output of gate drive circuit makes Gate signal unable to continue scanning down, so that the display screen appears abnormal phenomena such as horizontal line or horizontal line.
[0003] The last row of gate of the GIP (Gate in Panel) circuit of the display screen will output a high level pulse, and the pulse signal is connected to the display screen driving IC, and the display screen driving IC will receive the high level pulse every frame, and compare with the related signal, so as to judge that the gate drive of the display screen is normal output. When the abnormal output of a certain row causes the row to be unable to continue to pass, the signal received by the display screen driving IC is not a high level pulse, so it is considered that the current display screen gate drive process has related abnormality, and the display screen driving IC will start reset or other actions, which can avoid the existence of display abnormal state, without the need for user to manually operate, and the consumer experience is improved.
[0004] However, referring to Figure 1 , in the prior art, the display screen driving IC usually has only one PIN on one side to detect the state of the GIP output signal, while the actual GIP has multiple sets of CLK signal lines corresponding to Gate output, Figure 1 When Gn-3 row output is abnormal, the row and the corresponding CLK signal line are not connected to the detection pin of the display screen driving IC, so the display screen driving IC detection pin cannot detect the signal, so the display screen driving IC cannot act, and the display abnormality cannot be eliminated. Utility model content
[0005] The GIP circuit of the existing display panel has only the output line of the last row of GIP circuit connected to the detection of the driving IC of the display panel, so that the output signal abnormality of the row GIP circuit cascaded by other clock signal lines cannot be detected, resulting in no action of the display screen driving IC and the display abnormality cannot be eliminated.
[0006] In view of the above problems, a GIP circuit and display device are provided, by setting multiple abnormality detection modules corresponding to the clock signal lines, according to the cascade relationship of the gate drive module, the output signal abnormality of the gate drive module of any row of clock signal line can be detected, so that reset can be quickly performed, and display abnormality can be eliminated. Without changing the detection pin PIN of the existing driving IC, the detection effect is improved, and the product competitiveness is improved.
[0007] A GIP circuit comprises:
[0008] a plurality of clock signal lines;
[0009] a plurality of gate drive modules;
[0010] each of the clock signal lines is electrically connected with a prescribed sequence of the gate drive modules, and each of the gate drive modules is electrically connected with a corresponding row gate scanning line;
[0011] the gate drive modules connected with the same clock signal line are sequentially cascaded;
[0012] each of the clock signal lines is electrically connected with a driving IC of a display panel;
[0013] wherein, the GIP circuit further comprises a plurality of abnormality detection modules;
[0014] each of the abnormality detection modules is electrically connected with an output line of any row of gate drive modules connected with any clock signal line and a detection pin of the driving IC, so as to detect the output signal of the gate drive modules of the row or other rows connected with the clock signal line.
[0015] In a first possible implementation manner of the GIP circuit, the gate drive modules are respectively electrically connected with left and right ends of the row gate scanning lines in an odd-even interleaving manner, the plurality of clock signal lines comprise a first group of clock signal lines and a second group of clock signal lines, the first group of clock signal lines are electrically connected with the gate drive modules of the prescribed sequence on the left side, and the second group of clock signal lines are electrically connected with the gate drive modules of the prescribed sequence on the right side.
[0016] In a second possible implementation manner of the first possible implementation manner of the GIP circuit, the first group of clock signals comprises a first clock signal line and a second clock signal line, the first clock signal line is electrically connected with the gate drive modules of a first prescribed sequence, and the second clock signal line is electrically connected with the gate drive modules of a second prescribed sequence.
[0017] In a third possible implementation manner of the second possible implementation manner of the GIP circuit, the second group of clock signals comprises a third clock signal line and a fourth clock signal line, the third clock signal line is electrically connected with the gate drive modules of a third prescribed sequence, and the fourth clock signal line is electrically connected with the gate drive modules of a fourth prescribed sequence.
[0018] In a fourth possible implementation manner of the second possible implementation manner of the GIP circuit, the abnormality detection module comprises:
[0019] a first high-level unit;
[0020] the first TFT transistor and the second TFT transistor are electrically connected with the first high level unit after being connected in common at the drain,
[0021] the first TFT transistor and the second TFT transistor are electrically connected with the first high level unit after being connected in common at the drain,
[0022] the source of the first TFT transistor and the second TFT transistor is electrically connected with the first detection pin of the driving IC after being connected in common, the gate of the first TFT transistor is electrically connected with the output line of the gate drive module of any row of the first specified sequence, and the gate of the second TFT transistor is electrically connected with the output line of the gate drive module of any row of the second specified sequence.
[0023] In combination with the third possible implementation manner of the utility model, in the fifth possible implementation manner, the abnormality detection module comprises:
[0024] a second high level unit;
[0025] a third TFT transistor and a fourth TFT transistor;
[0026] the third TFT transistor and the fourth TFT transistor are electrically connected with the second high level unit after being connected in common at the drain,
[0027] the source of the third TFT transistor and the fourth TFT transistor is electrically connected with the second detection pin of the driving IC after being connected in common, the gate of the third TFT transistor is electrically connected with the output line of the gate drive module of any row of the third specified sequence, and the gate of the fourth TFT transistor is electrically connected with the output line of the gate drive module of any row of the fourth specified sequence.
[0028] In the second aspect, a display device comprises the GIP circuit of the first aspect.
[0029] The GIP circuit and the display device are implemented, the abnormality detection module corresponding to a plurality of clock signal lines is arranged, according to the cascade relationship of the gate drive module, the abnormality of the gate drive module output signal of any row of clock signal lines can be detected, so that the reset can be quickly performed, the display abnormality is eliminated, the detection effect is improved without changing the detection pin PIN of the existing driving IC, and the product competitiveness is improved. BRIEF DESCRIPTION OF DRAWINGS
[0030] In order to more clearly illustrate the technical scheme in the embodiments of the utility model, the drawings needed to be used in the embodiment description will be briefly introduced, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can be obtained according to these drawings without creating creative labor.
[0031] Figure 1 is a GIP circuit schematic diagram in the prior art;
[0032] Figure 2 is a GIP circuit schematic diagram of the utility model. DETAILED DESCRIPTION
[0033] The technical solutions in the utility model will be apparently and completely described in combination with the drawings in the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the utility model belongs. The terminology used in the description of the utility model herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used in this description and the appended claims, the singular forms "a", "an" and "the" include plural references unless the context clearly dictates otherwise.
[0035] It is to be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.
[0036] It is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like, indicate directions or positions based on the directions or positions shown in the drawings, and are used for convenience of description and simplification of description only, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application.
[0037] In addition, the terms "first", "second", "third", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise specifically defined.
[0038] The GIP circuit of the existing display panel is, for example, Figure 1 , Figure 1It is a GIP circuit schematic diagram in the prior art; since only the output line of the GIP circuit of the last row is connected with the detection of the driving IC of the display panel, the output signal abnormality of the row GIP circuit cascaded by other clock signal lines cannot be detected, so that the display screen driving IC cannot be operated and the display abnormality cannot be eliminated.
[0039] In view of the above problems, a GIP circuit and a display device are provided.
[0040] A GIP circuit, such as Figure 2 , Figure 2 It is a GIP circuit schematic diagram of the utility model. Including multiple clock signal lines, multiple gate drive modules GOA;Each clock signal line is connected with the gate drive module GOA of the prescribed sequence, and each gate drive module GOA is connected with the corresponding row gate scanning line;The gate drive module GOA connected with the same clock signal line is cascaded in turn;Each clock signal line is connected with the driving IC of the display panel;Wherein, the GIP circuit further includes multiple abnormality detection modules;The abnormality detection module is respectively connected with the output line of the gate drive module GOA of any row connected with any clock signal line and the detection pin of the driving IC, to detect the output signal of the gate drive module GOA of other rows connected with the row or the clock signal line.Through setting the abnormality detection module corresponding to multiple clock signal lines, according to the cascade relationship of the gate drive module GOA, the output signal abnormality of the gate drive module GOA of the row of any clock signal line can be detected, so that the reset can be carried out quickly, and the display abnormality can be eliminated, in the case that the detection pin PIN of the existing driving IC is not changed, the detection effect is improved, and the product competitiveness is improved.
[0041] Further, such as Figure 2 The gate drive module GOA is respectively connected with the left and right ends of the row gate scanning line in odd-even interleaving, multiple clock signal lines include first group clock signal line and second group clock signal line, the first group clock signal line is connected with the gate drive module GOA of the prescribed sequence on the left side, and the second group clock signal line is connected with the gate drive module GOA of the prescribed sequence on the right side.
[0042] Further, such as Figure 2The first set of clock signals includes a first clock signal line CK1L and a second clock signal line CK2L. The first clock signal line CK1L is electrically connected to the gate driver modules GOA in a first predetermined sequence, and the second clock signal line CK2L is electrically connected to the gate driver modules GOA in a second predetermined sequence. The first clock signal line CK1L is electrically connected to the gate driver modules GOA in rows Gn-1, Gn-5, and Gn-9, and these gate driver modules GOA in rows Gn-1, Gn-5, and Gn-9 are cascaded sequentially. The second clock signal line CK2L is electrically connected to the gate driver modules GOA in rows Gn-3 and Gn-7, and these gate driver modules GOA in rows Gn-3 and Gn-7 are cascaded sequentially.
[0043] Furthermore, such as Figure 2 The second set of clock signals includes a third clock signal line CK1R and a fourth clock signal line CK2R. The third clock signal line CK1R is electrically connected to the gate driver modules GOA in the third specified sequence, and the fourth clock signal line CK2R is electrically connected to the gate driver modules GOA in the fourth specified sequence. The third clock signal line CK1R is electrically connected to the gate driver modules GOA in rows Gn, Gn-4, and Gn-8, and these rows are cascaded sequentially. The second clock signal line CK2R is electrically connected to the gate driver modules GOA in rows Gn-2 and Gn-6, and these rows are cascaded sequentially.
[0044] Specifically, the anomaly detection module includes a first high-level unit VGH1; a first TFT transistor T1 and a second TFT transistor T2; the drains of the first TFT transistor T1 and the second TFT transistor T2 are connected together and then electrically connected to the first high-level unit VGH1; the sources of the first TFT transistor T1 and the second TFT transistor T2 are connected together and then electrically connected to the first detection pin PIN1 of the driver IC; the gate of the first TFT transistor T1 is electrically connected to the output line of the gate driving module GOA in any row of the first predetermined sequence; and the gate of the second TFT transistor T2 is electrically connected to the output line of the gate driving module GOA in any row of the second predetermined sequence. For the first clock signal line CK1L on the left, the first TFT transistor T1 is electrically connected to the output line of the gate driving module GOA in row Gn-1 connected to it; for the second clock signal line CK2L on the left, the second TFT transistor T2 is electrically connected to the output line of the gate driving module GOA in row Gn-3 connected to it.
[0045] Specifically, the abnormality detection module comprises a second high voltage level unit VGH2, a third TFT transistor T3 and a fourth TFT transistor T4, the drains of the third TFT transistor T3 and the fourth TFT transistor T4 are connected to the second high voltage level unit VGH2, the sources of the third TFT transistor T3 and the fourth TFT transistor T4 are connected to a second detection pin PIN2 of a driving IC, the gate of the third TFT transistor T3 is connected to an output line of a gate drive module GOA of any row of a third sequence, and the gate of the fourth TFT transistor T4 is connected to an output line of a gate drive module GOA of any row of a fourth sequence.
[0046] For the third clock signal line CK1R on the right side, the third TFT transistor T3 is connected to the output line of the gate drive module GOA of the Gn row, and for the second clock signal line CK2L on the right side, the fourth TFT transistor T4 is connected to the output line of the gate drive module GOA of the Gn-2 row.
[0047] In the second aspect, the display device comprises the GIP circuit of the first aspect.
[0048] The GIP circuit and the display device of the utility model, through setting up a plurality of clock signal lines corresponding abnormality detection module, according to the cascade relationship of gate drive module GOA, the abnormality of the output signal of the gate drive module GOA of any row of clock signal line can be detected, so as to carry out reset quickly, eliminate display abnormality, in the case that the detection pin PIN of existing driving IC is not changed, the detection effect is improved, and the product competitiveness is improved.
[0049] The above is only the preferred embodiment of the utility model, and does not limit the utility model, and any modification, equivalent replacement, improvement, etc. within the spirit and principle of the utility model should be included in the protection scope of the utility model.
Claims
1. A GIP circuit, characterized in that, include: Multiple clock signal lines; Multiple gate drive modules; Each of the clock signal lines is electrically connected to a specified sequence of gate driving modules, and each of the gate driving modules is electrically connected to a corresponding row gate scan line; The gate drive modules connected to the same clock signal line are cascaded in sequence. Each of the aforementioned clock signal lines is electrically connected to the driver IC of the display panel; The GIP circuit also includes multiple anomaly detection modules; The anomaly detection module is electrically connected to the output line of the gate drive module of any row connected to any clock signal line and the detection pin of the driver IC, respectively, to detect the output signal of the gate drive module of that row or other rows connected to the clock signal line.
2. The GIP circuit according to claim 1, characterized in that, The gate driving modules are electrically connected to the left and right ends of the row gate scan lines in an odd-even alternating manner. The plurality of clock signal lines include a first group of clock signal lines and a second group of clock signal lines. The first group of clock signal lines is electrically connected to the gate driving modules of a predetermined sequence on the left, and the second group of clock signal lines is electrically connected to the gate driving modules of a predetermined sequence on the right.
3. The GIP circuit according to claim 2, characterized in that, The first set of clock signals includes a first clock signal line and a second clock signal line. The first clock signal line is electrically connected to a gate driving module of a first predetermined sequence, and the second clock signal line is electrically connected to a gate driving module of a second predetermined sequence.
4. The GIP circuit according to claim 3, characterized in that, The second set of clock signals includes a third clock signal line and a fourth clock signal line. The third clock signal line is electrically connected to the gate driving module of the third predetermined sequence, and the fourth clock signal line is electrically connected to the gate driving module of the fourth predetermined sequence.
5. The GIP circuit according to claim 3, characterized in that, The anomaly detection module includes: First high-level unit; First TFT transistor and second TFT transistor; The drains of the first TFT transistor and the second TFT transistor are connected together and then electrically connected to the first high-level unit. The first TFT transistor and the second TFT transistor are connected to the same source and are electrically connected to the first detection pin of the driving IC. The gate of the first TFT transistor is electrically connected to the output line of the gate driving module of any row of the first predetermined sequence, and the gate of the second TFT transistor is electrically connected to the output line of the gate driving module of any row of the second predetermined sequence.
6. The GIP circuit according to claim 4, characterized in that, The anomaly detection module includes: Second high-level unit; The third TFT transistor and the fourth TFT transistor; The drains of the third TFT transistor and the fourth TFT transistor are connected together and then electrically connected to the second high-level unit. The sources of the third TFT transistor and the fourth TFT transistor are connected together and then electrically connected to the second detection pin of the driver IC. The gate of the third TFT transistor is electrically connected to the output line of the gate driving module in any row of the third predetermined sequence, and the gate of the fourth TFT transistor is electrically connected to the output line of the gate driving module in any row of the fourth predetermined sequence.
7. A display device, characterized in that, Includes the GIP circuit as described in any one of claims 1-6.