High-order FIR filter based on FPGA
By employing a combined structure of an input register module, a lookup table address generation module, and a shift-accumulator module in an FPGA, the problem of low resource utilization in traditional high-order FIR filters is solved, achieving efficient resource saving and improved computational efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-14
- Publication Date
- 2026-03-24
AI Technical Summary
Traditional FPGA-implemented high-order FIR filters suffer from low resource utilization and high power consumption, making it difficult to meet the high performance, low power consumption, and small size requirements of portable devices.
It adopts a combined structure of input register module, lookup table address generation module, lookup table module and shift accumulator module, and is configured as a five-input dual-output structure through bit splicing and LUT6, which reduces the use of adders and improves the utilization of LUT6.
It effectively saves resources, improves the resource utilization of LUT6 from 50% to 100%, reduces chip logic utilization, and improves computing efficiency.
Smart Images
Figure CN224037338U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of digital signal processing technology, specifically relating to a high-order FIR filter based on FPGA. Background Technology
[0002] In the field of digital signal processing, high-order finite impulse response (FIR) filters are widely used in various real-time signal processing systems due to their linear phase characteristics and stability. However, as the filter order increases, their implementation faces two major challenges: a sharp increase in computational complexity and enormous hardware resource consumption. Especially in Field Programmable Gate Array (FPGA) implementations, traditional distributed FIR filter structures require a large number of adders for input preprocessing, resulting in low resource utilization and increased power consumption, making it difficult to meet the stringent requirements of modern embedded systems for high performance, low power consumption, and small size.
[0003] Traditional FIR filter implementations reduce the resource usage for subsequent lookup table construction by pre-adding inputs with identical coefficients during the preprocessing stage. This structure introduces adders with half the number of coefficients during preprocessing. When implementing high-order FIR filters, these adders consume significant resources on the FPGA, increasing design resource consumption. Furthermore, existing structures do not fully utilize the structural features of the LUT6 in the lookup table design. Current technologies generally use the LUT6 as a six-input, one-output lookup table, leaving one of the LUT6's two output ports idle, thus reducing the LUT6's utilization rate.
[0004] In portable devices, there are strict limitations on cost, power consumption, and size, so small, low-cost FPGA chips are typically used to implement signal processing functions. How to efficiently implement high-order FIR filters within limited hardware resources is a key technical challenge in portable device design. To address this, an improved FIR filter structure is proposed to reduce the resource consumption of high-order FIR filters. Utility Model Content
[0005] This utility model discloses a high-order FIR filter based on FPGA, which aims to solve the technical problem that the adder of the existing distributed FIR filter will occupy a lot of resources, resulting in low resource utilization and high energy consumption.
[0006] To solve the aforementioned technical problems, the present invention adopts the following technical solution:
[0007] A high-order FIR filter based on FPGA includes an input register module, a lookup table address generation module, a lookup table module, and a shift accumulator module connected in sequence.
[0008] The input register module is used to receive serial input data and delay it, and output parallel data with the same number of filter taps to the lookup table address generation module.
[0009] The lookup table address generation module is used to concatenate two data with the same filtering coefficient and decompose them bit by bit, with the data in the same bit forming a lookup table address vector;
[0010] The lookup table module is used to group the address vector into groups of five bits, and to output the corresponding partial product by multiplying and accumulating the five-bit input and filter coefficient stored by multiple concatenated LUT6s. The LUT6 is configured as a five-input, dual-output structure.
[0011] The shift-accumulation module is used to shift the obtained partial products according to the weights corresponding to each partial product, and accumulate all the shifted results.
[0012] In this invention, the pre-addition is replaced by a bit-joining structure. In terms of hardware, only the wires need to be reconnected, which eliminates the step required by the traditional distributed structure to add each pair of input data with the same coefficients through a real number adder during the preprocessing stage. This directly eliminates the use of the adder, which can effectively save resources for high-order filters and directly reduce the logic utilization of the chip. In addition, by configuring LUT6 as a five-input dual-output structure, the resource utilization of LUT6 is increased from 50% to 100%, achieving a theoretical doubling of utilization.
[0013] Preferably, the lookup table address generation module includes multiple data splicing units, each data splicing unit corresponds to a pair of input data with the same filtering coefficient, and outputs the pair of data after bit splicing.
[0014] After adopting this technical solution, it should be noted that by equipping each pair of input data with the same coefficients with an independent and dedicated data splicing unit, the splicing operation of all N / 2 pairs of data can be completed in parallel within the same clock cycle, thereby achieving the effect of saving resources. Here, N is the total number of taps of the high-order FIR filter, that is, the total number of filter coefficients.
[0015] Preferably, the lookup table module includes multiple lookup table sub-units, each of which corresponds to a set of five-bit data in the lookup table address vector, used to calculate the multiplication and accumulation result of the five-bit input and the filter coefficient.
[0016] After adopting this technical solution, it should be noted that the lookup table address vector refers to the parallel vector composed of all data in the same bit after the concatenated pairs of data are decomposed bit by bit. Since the LUT6 is configured as a five-input structure, the address vector is grouped into groups of five bits, and the higher bits are padded with zeros if less than five bits. Each lookup table sub-unit is independently responsible for the multiplication and accumulation operation of a group of five-bit data, realizing parallel processing within the group. For an N-tap FIR filter, it corresponds to N parallel input data. Due to the linear phase characteristic, the i-th filter coefficient is the same as the (N-1)-i-th filter coefficient, forming N / 2 pairs of data. After each pair of data is concatenated, it is decomposed bit by bit, and the N / 2 data in the same bit form the address vector, that is, the address vector has a bit width of N / 2 bits. Combining the five-input structure of LUT6, the address vector is grouped into groups of five bits, and the number of groups is (N / 2) / 5=N / 10. Therefore, the number of lookup table sub-units is N / 10. The entire multiply-accumulate operation is broken down into N / 10 independent and concurrently executed table lookup operations. The massive multiply-accumulate task is decomposed into multiple small-scale parallel tasks, and the partial product corresponding to the current address vector can be generated within a single cycle, significantly improving computational efficiency.
[0017] Preferably, each of the lookup table subunits includes at least one level of lookup table group consisting of cascaded LUT6 lookup table units in the FPGA.
[0018] Preferably, the lookup table group is configured to receive a five-bit address input, and the LUT6 lookup table unit is configured as a five-input, dual-output structure, with a single LUT6 lookup table unit simultaneously outputting two bits of the multiplication-accumulation result.
[0019] After adopting this technical solution, it should be noted that LUT6 is usually used as a six-input single-output lookup table. This utility model configures it as a five-input, dual-output structure, which essentially treats one LUT6 as two independent five-input lookup tables. By simultaneously sending the five address bits into the five address ports of the LUT6 and fixing the sixth address port as an active level, the results of two pre-stored different bits can be read in parallel through its two output ports within one lookup cycle. This doubles the resource utilization of a single LUT6 and fundamentally reduces the total number of LUT6s required to achieve the same function.
[0020] Preferably, for a multiplication-accumulation result with an output bit width of M bits, the lookup table group consists of at least M / 2 LUT6 lookup table units, with the lower five address inputs of each LUT6 lookup table unit connected to the five-bit input, and its highest address input fixed to a high level.
[0021] After adopting this technical solution, it should be noted that for a lookup table group that needs to output M bits of results, the traditional single-output structure requires M LUT6s. Since each LUT6 of this invention can output two bits, only M / 2 LUT6s are needed to form the lookup table group, directly halving the resource requirements and improving the computational efficiency.
[0022] Furthermore, the input register module consists of multiple cascaded registers, the number of which is equal to the number of taps of the FIR filter.
[0023] Furthermore, the shift-accumulation module includes multiple shifters and an adder tree. The shifters are used to perform weighted shifts on partial products, and the adder tree is used to accumulate the shifted results.
[0024] In summary, due to the adoption of the above technical solution, the beneficial effects of this utility model are:
[0025] This invention provides a high-order FIR filter based on FPGA. By changing the merging structure of inputs with the same coefficients in the lookup table address generation module to a concatenation and merging structure, the introduction of adders is avoided, reducing resource consumption. In addition, the structural characteristics of LUT6 in FPGA are fully utilized in the lookup table module, dividing the address input into groups of five bits. At the same time, LUT6 is configured as a five-input two-output structure, so that one LUT6 can output two bits of multiplication and accumulation at the same time, reducing the resource usage when constructing the lookup table. Attached Figure Description
[0026] This utility model will be described by way of example and with reference to the accompanying drawings, wherein:
[0027] Figure 1 This is an overall block diagram of the present utility model;
[0028] Figure 2 This is a structural diagram of the present utility model;
[0029] Figure 3 This is a structural diagram of the input register module of this utility model;
[0030] Figure 4 This is a structural diagram of the lookup table address generation module of this utility model;
[0031] Figure 5 This is a structural diagram of the lookup table module of this utility model;
[0032] Figure 6 This is a structural diagram of the lookup table subunit of this utility model. Detailed Implementation
[0033] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the embodiments and accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and marked in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0034] In the description of the embodiments of this application, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the utility model product is in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0035] The following is combined Figures 1-6 This utility model will be described in detail.
[0036] A high-order FIR filter based on FPGA, such as Figure 1 , Figure 2 As shown, it includes an input register module, a lookup table address generation module, a lookup table module, and a shift accumulator module connected in sequence;
[0037] The input register module is used to receive serial input data and delay it, and output parallel data with the same number of filter taps to the lookup table address generation module.
[0038] like Figure 3 The diagram shows the structure of the input register module. X(n) represents the input data entering the system at the current time, and X(n-N+1) represents the input data entering the system N-1 cycles ago. Both are B-bit binary numbers. Furthermore, X... B (n) represents the Bth bit of the current input data. The input register module is used to store the input data of the past N-1 cycles and transmit it in parallel to the lookup table address generation module.
[0039] The lookup table address generation module is used to concatenate two data with the same filtering coefficient and decompose them bit by bit, with the data in the same bit forming a lookup table address vector;
[0040] like Figure 4 The diagram shows the structure of the lookup table address generation module. Utilizing the characteristic of coefficient stacking, it allocates the input N B-bit binary data to N / 2 2B-bit address buffer registers through bit concatenation operations. These registers are: addr_buf[0], addr_buf[1], ..., addr_buf[N / 2-1]. The lower B bits of each buffer register store X(n), X(n-1), ..., X(nN / 2+1), respectively, while the higher B bits store the corresponding symmetrical coefficient data X(n-N+1), X(n-N+2), ..., X(nN / 2). Ultimately, each buffer register contains two input data with the same coefficients. Transfer the same bit of data from N / 2 address buffer registers to one N / 2 address register, i.e., sequentially transfer [X0(n), X0(n-1), ..., X0(nN / 2+1)], [X1(n), X1(n-1), ..., X1(nN / 2+1)], ..., [X B (n-N+1),X B (n-N+2), ..., X B [nN / 2] is passed to the address register addr. One data point is passed to addr per cycle, requiring a total of 2B cycles. b This represents the b-th bit of the address register, where b ranges from [0 to N / 2+1]. The data in the address register is the address vector.
[0041] The lookup table module is used to group the address vector into groups of five bits, and to output the corresponding partial product by multiplying and accumulating the five-bit input and filter coefficient stored by multiple concatenated LUT6s. The LUT6 is configured as a five-input, dual-output structure.
[0042] The shift-accumulation module is used to shift the obtained partial products according to the weights corresponding to each partial product, and accumulate all the shifted results.
[0043] In this embodiment, by replacing pre-addition with a bit-joining structure, only reconnection of wires is required in hardware. This eliminates the step required in traditional distributed structures to add each pair of input data with the same coefficients through a real number adder during the preprocessing stage, thus directly eliminating the use of adders. For high-order filters, this effectively saves resources and directly reduces the logic utilization of the chip. In addition, by configuring LUT6 as a five-input dual-output structure, the resource utilization of LUT6 is increased from 50% to 100%, theoretically doubling the utilization.
[0044] In this embodiment, the lookup table address generation module includes multiple data concatenation units. Each data concatenation unit corresponds to a pair of input data with the same filter coefficients, and outputs the pair of data after bit concatenation. By equipping each pair of input data with the same coefficients with an independent, dedicated data concatenation unit, the concatenation operation of all N / 2 pairs of data can be completed in parallel within the same clock cycle, thereby achieving the effect of saving resources. Here, N is the total number of taps of the high-order FIR filter, that is, the total number of filter coefficients.
[0045] In this embodiment, as Figure 5 , Figure 6 As shown, the lookup table module includes multiple lookup table sub-units. Figure 5 The sub-units are denoted as lookup table sub-unit 1, lookup table sub-unit 2, ..., lookup table sub-unit N / 10. Each lookup table sub-unit corresponds to a set of five-bit data in the lookup table address vector, which is used to calculate the product and sum of the five-bit input and the filter coefficients. The lookup table address vector refers to the parallel vector formed by decomposing the concatenated pairs of data bit by bit, where all data share the same bit. Since the LUT6 is configured with a five-input structure, the address vector is grouped into groups of five bits, with zeros padded at the higher bits if less than five bits. Each lookup table sub-unit is independently responsible for the multiplication and accumulation operations of a group of five bits, achieving parallel processing within the group. For an N-tap FIR filter, which corresponds to N parallel input data, the linear phase characteristic makes the i-th and N-1-i-th filter coefficients the same, forming N / 2 pairs of data. After concatenating each pair of data, it is decomposed bit by bit, and the N / 2 data at the same bit form the address vector, that is, the address vector has a bit width of N / 2 bits. Combining the five-input structure of the LUT6, the address vector is grouped into groups of five bits, and the number of groups is (N / 2) / 5 = N / 10. Therefore, the number of lookup table sub-units is N / 10. The entire multiply-accumulate operation is broken down into N / 10 independent and concurrently executed table lookup operations. The massive multiply-accumulate task is decomposed into multiple small-scale parallel tasks, and the partial product corresponding to the current address vector can be generated within a single cycle, significantly improving the computational efficiency. The multiply-accumulate result of the address vector and all coefficients is obtained by adding the outputs of all lookup table sub-units, i.e., addr0h(0) + addr1h(1) + ... + addr N / 2-1 h(N / 2-1), this result is called the partial product.
[0046] In this embodiment, each lookup table subunit includes at least one level of lookup table group composed of cascaded LUT6 lookup table units in the FPGA.
[0047] In this embodiment, the lookup table group is configured to receive a five-bit address input, and the LUT6 lookup table unit is configured as a five-input, dual-output structure. A single LUT6 lookup table unit simultaneously outputs two bits of the multiplication-accumulation result. LUT6 is typically used as a six-input, single-output lookup table. This invention configures it as a five-input, dual-output structure, essentially treating one LUT6 as two independent five-input lookup tables. By simultaneously sending the five-bit address to the five address ports of the LUT6 and fixing the sixth address port as active, the results of two pre-stored different bits can be read in parallel through its two output ports within one lookup cycle. This doubles the resource utilization of a single LUT6, fundamentally reducing the total number of LUT6s required to achieve the same function.
[0048] In this embodiment, for a multiplication-accumulation result with an output width of M bits, the lookup table group consists of at least M / 2 LUT6 lookup table units. The lower five address inputs of each LUT6 lookup table unit are connected to the five-bit input, and its highest address input is fixed at a high level. For a lookup table group that needs to output an M-bit result, a traditional single-output structure requires M LUT6s. Since each LUT6 in this invention can output two bits, only a minimum of M / 2 LUT6s are needed to form the lookup table group, directly halving the resource requirements and improving computational efficiency.
[0049] In this embodiment, the input register module consists of multiple cascaded registers, and the number of registers is equal to the number of taps of the FIR filter.
[0050] In this embodiment, the shift-accumulate module includes multiple shifters and an adder tree. The shifters are used to perform weighted shifts on partial products, and the adder tree is used to accumulate the shifted results.
[0051] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. An FPGA-based high-order FIR filter, characterized in that, The input register module, the look-up table address generation module, the look-up table module and the shift and accumulation module are sequentially connected. The input register module is used for receiving serial input data and delaying, and outputting parallel data with the same number of filter taps to the look-up table address generation module. The look-up table address generation module is used for splicing two data with the same filter coefficients, and decomposing by bit, and the data on the same bit form a look-up table address vector.
2. The FPGA-based high-order FIR filter of claim 1, wherein, The look-up table module is used for grouping the address vector by five bits, and outputting corresponding partial products by looking up the multiplication and accumulation result of five-bit input and filter coefficients stored by a plurality of LUT6 cascades, and the LUT6 is configured as a five-input and double-output structure.
3. The FPGA-based high-order FIR filter of claim 2, wherein, The shift and accumulation module is used for shifting the obtained partial products according to the corresponding weight of each partial product, and accumulating all the shifted results.
4. The FPGA-based high-order FIR filter of claim 3, wherein, The look-up table address generation module includes a plurality of data splicing units, each data splicing unit corresponds to a pair of input data with the same filter coefficient, and outputs the bit spliced data.
5. The FPGA-based high-order FIR filter of claim 4, wherein, The look-up table module includes a plurality of look-up table subunits, each look-up table subunit corresponds to a group of five-bit data of the look-up table address vector, and is used for calculating the multiplication and accumulation result of the five-bit input and filter coefficient.
6. The FPGA-based high-order FIR filter of claim 5, wherein, Each look-up table subunit includes at least one look-up table group composed of LUT6 look-up table units cascaded in the FPGA.
7. The FPGA-based high-order FIR filter according to any one of claims 1-6, characterized in that, For the multiplication and accumulation result with an output bit width of M bits, the look-up table group is composed of at least M / 2 LUT6 look-up table units, the low five-bit address input end of each LUT6 look-up table unit is connected to the five-bit input, and the highest bit address input end is connected to high level. The input register module is composed of a plurality of cascaded registers, and the number of registers is equal to the number of taps of the FIR filter. The shift and accumulation module includes a plurality of shifters and a adder tree, the shifters are used for weighted shifting of partial products, and the adder tree is used for accumulation of the shifted results.