AD acquisition module suitable for capacitor voltage transformer

Abstract

The utility model discloses an AD acquisition module suitable for a capacitor voltage transformer, and the AD acquisition module carries out serial communication with a slave MCU through an SPI line, and can be connected with and collect fault signals of a plurality of CVT transformers. Key components such as an AD acquisition chip U7, a linear voltage regulator U6 and a crystal oscillator Y1 are integrated in the module. Wherein the AD acquisition chip U7 is provided with a plurality of groups of acquisition pins, and each group of pins comprises a positive electrode input and a negative electrode input which are respectively connected with a live wire and a zero wire of the CVT so as to realize accurate fault signal acquisition. The AD acquisition module has the characteristics of compact structure, stable performance, high acquisition precision and the like, and is suitable for an on-line monitoring system of the capacitor voltage transformer.

Description

Technical Field

[0001] This application relates to the field of power system technology, and in particular to an AD acquisition module adapted to capacitive voltage transformers. Background Technology

[0002] In power systems, capacitive voltage transformers (CVTs) are crucial electrical equipment, and monitoring their operational status is essential for ensuring the safe and stable operation of the power system. However, traditional CVT monitoring devices often suffer from insufficient monitoring accuracy and poor real-time performance, making it difficult to meet the high requirements of modern power systems for equipment status monitoring. Summary of the Invention

[0003] To address the shortcomings of existing technologies, the purpose of this application is to provide an AD acquisition module adapted to capacitive voltage transformers, which can accurately monitor CVTs.

[0004] To achieve the above objectives, this application adopts the following technical solution:

[0005] This application provides an AD acquisition module adapted to a capacitive voltage transformer. The AD acquisition module is connected to a slave MCU via an SPI line. The SPI line is used for serial communication between the slave MCU and the AD acquisition module. The AD acquisition module is connected to several CVT transformers and is used to acquire fault signals of each CVT transformer. The AD acquisition module includes: an AD acquisition chip U7, a linear regulator U6, and a crystal oscillator Y1. The linear regulator U6 is connected to the AD acquisition chip U7, and the crystal oscillator Y1 is connected to the AD acquisition chip U7. The AD acquisition chip U7 includes several sets of acquisition pins. Each set of acquisition pins includes a positive input pin and a negative input pin. The positive input pin is connected to the live wire of the CVT transformer, and the negative input pin is connected to the neutral wire of the CVT transformer.

[0006] As a preferred technical solution, the AD acquisition chip U7 includes an analog ground pin AGND, which is connected to analog ground; the AD acquisition chip U7 includes an analog voltage output pin AVDD, which is connected to the 3.3V analog working voltage line VDD3.3V_AVDD; capacitors C33 and C35 are connected in parallel between the analog voltage output pin AVDD and analog ground; the AD acquisition chip U7 includes a ground pin GND, which is connected to the ground terminal; a resistor R40 is connected in series between the ground terminal and analog ground; the AD acquisition chip U7 includes a digital voltage input pin DVDD, which is connected to the 3.3V AD working voltage line VDD3.3V_AD; the 3.3V AD working voltage line VDD3.3V_AD is connected to the AD power module; capacitors C34 and C35 are connected in parallel between the digital voltage input pin DVDD and the ground terminal; the AD acquisition chip U7 includes a clock signal input pin CLKIN; the AD acquisition chip U7 includes a capacitor pin CAP, which is connected to the ground terminal; a capacitor C38 is connected in series between the capacitor pin CAP and the ground terminal.

[0007] As a preferred technical solution, the AD acquisition chip U7 is model AD7616H or ADS131.

[0008] As a preferred technical solution, the linear regulator U6 includes a voltage input pin VIN, which is connected to the analog power supply voltage AVCC; the linear regulator U6 includes a ground pin GND, which is connected to the analog ground; the linear regulator U6 includes an enable pin CE, which is connected to the analog power supply voltage AVCC; the linear regulator includes a voltage output pin VOUT, which outputs the analog operating voltage VDD3.3V_AVDD; and capacitors C31 and C32 are connected in parallel between the voltage output pin VOUT and the analog ground.

[0009] As a preferred technical solution, the linear regulator U6 has the model number HE2210M533R.

[0010] As a preferred technical solution, the crystal oscillator Y1 includes a voltage input pin VDD, which is connected to the 3.3V AD working voltage line VDD3.3V_AD, and a capacitor C42 is connected in series between the voltage input pin VDD and the ground terminal; the crystal oscillator Y1 includes a standby wake-up pin ST; the crystal oscillator Y1 includes a clock signal output pin CLK, which is connected to the clock signal input pin CLKIN of the AD acquisition chip U7; the crystal oscillator Y1 includes a ground pin GND, which is connected to the ground terminal.

[0011] As a preferred technical solution, the crystal oscillator Y1 has a model number of 4.096M.

[0012] The AD acquisition module for capacitive voltage transformers provided in this application has the following main advantages:

[0013] 1. High-precision acquisition: The dedicated AD acquisition chip U7 enables high-precision acquisition of CVT transformer fault signals. This high precision helps in the timely detection and handling of potential CVT problems, improving the stability and safety of the power system.

[0014] 2. Stable Power Supply: The linear regulator U6 provides a stable power supply to the AD acquisition chip U7, ensuring that the AD acquisition module can work normally under various operating conditions. A stable power supply is the foundation for ensuring the accuracy of data acquisition and the long-term stable operation of the module.

[0015] 3. Stable Clock Signal: Crystal oscillator Y1 provides a stable clock signal to AD acquisition chip U7, which is crucial for ensuring the synchronization and accuracy of data acquisition. A stable clock signal helps reduce errors during data acquisition and improves data reliability.

[0016] 4. Multi-channel acquisition: The U7 AD acquisition chip contains several sets of acquisition pins, each set of pins connected to the live and neutral wires of the CVT transformer, enabling simultaneous acquisition from multiple channels. This greatly improves data acquisition efficiency, allowing the system to more comprehensively monitor the CVT's operating status.

[0017] 5. Easy integration and expansion: The AD acquisition module communicates serially with the slave MCU via an SPI line, making it easy to integrate into the entire monitoring system and facilitating subsequent functional expansion and upgrades. This modular design reduces system complexity and maintenance costs.

[0018] In summary, the AD acquisition module provided in this application has the advantages of high precision, stable power supply, stable clock signal, multi-channel acquisition, and easy integration and expansion, which can significantly improve the performance and reliability of the online monitoring system for capacitive voltage transformers. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of the online monitoring device for the capacitive voltage transformer of this application;

[0020] Figure 2 This is the circuit diagram of the AD acquisition module of this application;

[0021] Figure 3 This is a schematic diagram of the connection structure of each unit of the AD acquisition module in this application;

[0022] Figure 4 This is the circuit diagram of the AD acquisition chip U7 in this application;

[0023] Figure 5 The circuit diagram of the linear regulator U6 in this application is shown below.

[0024] Figure 6 This is a circuit diagram of the crystal oscillator Y1 of this application;

[0025] Figure 7 This is the circuit diagram of the CVT transformer in this application;

[0026] Figure 8 This is a circuit diagram of the MCU control module of this application;

[0027] Figure 9 This is a schematic diagram of the connection structure of each unit of the MCU control module in this application;

[0028] Figure 10 This is a circuit diagram of the clock chip module of this application;

[0029] Figure 11 This is a circuit diagram of the host MCU chip / slave MCU chip in this application;

[0030] Figure 12 This is a circuit diagram of the slave power supply control circuit of this application;

[0031] Figure 13 This is a schematic diagram of the connection structure of each unit in the slave power control circuit of this application;

[0032] Figure 14 This is a circuit diagram of the AD battery control circuit of this application;

[0033] Figure 15 This is a circuit diagram of the MCU power control circuit of this application;

[0034] Figure 16 This is a circuit diagram of the wireless power control circuit of this application;

[0035] Figure 17 This is a circuit diagram of the first AD voltage conversion circuit of this application;

[0036] Figure 18 This is a circuit diagram of the second AD voltage conversion circuit of this application;

[0037] Figure 19 This is a circuit diagram of the wired synchronization module of this application;

[0038] Figure 20 This is a graph showing the monitoring data obtained from the online monitoring method of the capacitive voltage transformer in this application. Detailed Implementation

[0039] To enable those skilled in the art to better understand the present application, the technical solutions in specific embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0040] like Figure 1 As shown, this application provides an online monitoring device for a capacitive voltage transformer. The online monitoring device for the capacitive voltage transformer includes a main unit and several slave units.

[0041] It should be noted that multiple master groups can be configured, and these master groups can communicate with each other via wired or wireless communication. Each master group can also communicate wirelessly with several slave devices. Each master represents a master node, and each slave represents a slave node.

[0042] In this application, the online monitoring device includes: 1 set of master units and 3 sets of slave units.

[0043] The host system includes: a PC server, a host MCU, and a host wireless module.

[0044] The PC server and the host MCU are connected via UART1, which is used for serial communication between them. The PC server and the host wireless module are connected via UART2, which is also used for serial communication between them.

[0045] The host MCU is connected to a 220V synchronization signal line 220VSYNC. This line provides voltage to the host and synchronizes the clock signals between the host and slave devices. The host MCU is connected to the host wireless module via a SYNC1 / WAKEUP line. This line is used to wake up the host wireless module when the host MCU receives a wake-up signal; in this application, the wake-up count is 5 times. The host MCU is also connected to the host wireless module via a SYNC2 / SYNC line, which transmits signals from the host MCU to the host wireless module synchronously.

[0046] In this application, the host wireless module adopts a ZIGB module, etc.

[0047] Each slave device includes: a slave MCU, a slave wireless module, an AD acquisition module, a wireless power module, and an AD power module.

[0048] In this application, the slave wireless module adopts a ZIGB module, etc.

[0049] The slave wireless module and the master wireless module are wirelessly connected for data transmission between them. The slave wireless module connects to the slave MCU via a SYNC1 / WAKEUP line. The SYNC1 / WAKEUP line is used to synchronously wake up the slave MCU when the slave wireless module receives a wake-up signal; in this application, the wake-up count is 5 times. The slave wireless module also connects to the slave MCU via a SYNC2 / SYNC line, which is used to synchronously transmit signals from the slave wireless module to the slave MCU. Finally, the slave wireless module and the slave MCU are connected via a UART1 line for serial communication.

[0050] The slave MCU connects to a spare 220V synchronization signal line 220VSYNC. This line provides voltage to the slave and synchronizes the clock signals between the master and slave. The slave MCU connects to the wireless power module via a ZIGBPOWER line. The wireless power module then connects to the slave wireless module, providing a suitable voltage through voltage conversion. The slave MCU also connects to the AD power module via an ADPOWER line. This power module connects to the AD acquisition module, providing a suitable voltage through voltage conversion. Finally, the slave MCU and the AD acquisition module are connected via an SPI line for serial communication.

[0051] The AD acquisition module is connected to several CVT transformers and is used to acquire fault signals from each CVT transformer.

[0052] The online monitoring device for capacitive voltage transformers disclosed in this application operates on the following principle: the AD acquisition module triggers analog-to-digital conversion and acquires fault signals from each CVT transformer; the AD acquisition module performs data conversion on the fault signals and outputs the converted data to the slave MCU via the SPI serial port; each slave MCU sends data to the master MCU, which processes and judges the data; the slave MCU and the master MCU communicate via the master wireless module and the slave wireless module.

[0053] With the above settings, the online monitoring device for capacitive voltage transformers of this application can realize the acquisition of fault signals from multiple CVT transformers.

[0054] The online monitoring device for capacitive voltage transformers in this application is configured with two signal synchronization methods.

[0055] The first signal synchronization method: Signal synchronization is performed through a 220V synchronization signal line 220VSYNC and a spare 220V synchronization signal line 220VSYNC.

[0056] The second signal synchronization method: The master unit broadcasts wake-up and acquisition commands to the slave units. The master unit's wireless module is woken up, which in turn drives the slave unit's wireless module to wake up the slave MCU, causing all slave units to wake up simultaneously. The slave MCU then drives the AD acquisition module to collect fault signals from each CVT transformer. All AD acquisition modules begin collecting CVT transformer fault signal data simultaneously, ensuring consistent and synchronized timing of CVT transformer fault signal data acquisition.

[0057] like Figures 2-6 As shown, this application also provides an AD acquisition module adapted to a capacitive voltage transformer.

[0058] Furthermore, the AD acquisition module includes: an AD acquisition chip U7, a linear regulator U6, and a crystal oscillator Y1.

[0059] In this application, the AD acquisition chip U7 is model AD7616H or ADS131, etc. In this embodiment, ADS131 is used as an example.

[0060] The AD acquisition chip U7 includes several sets of acquisition pins. Each set of acquisition pins includes a positive input pin and a negative input pin. The positive input pin is connected to the live wire of the CVT transformer, and the negative input pin is connected to the neutral wire of the CVT transformer. For example, in this embodiment, the AD acquisition chip U7, model ADS131M04IPWR, includes four sets of acquisition pins. One set of acquisition pins consists of AIP0P and AIP0N. AIP0P is connected to the live wire of the CVT transformer, and AIP0N is connected to the neutral wire of the CVT transformer. The other three sets of acquisition pins are similar and will not be described further.

[0061] A capacitor C37 is connected in parallel between the acquisition pins AIP0P and AIP0N. The live wire terminal CVTA of the CVT transformer (CVT A) is connected to the acquisition pin AIP0P after being connected in series with resistors R41 and R42. The neutral wire terminal CVTAGND of the CVT transformer is connected to the acquisition pin AIP0N after being connected in series with resistors R45 and R44. The two ends of resistor R43 are connected between resistors R41 and R42, and between resistors R45 and R44, respectively. The connection methods for the remaining CVT transformers are similar and will not be described further.

[0062] The AD acquisition chip U7 includes an analog ground pin AGND, which is connected to analog ground.

[0063] The AD acquisition chip U7 includes an analog voltage output pin AVDD, which is connected to the 3.3V analog operating voltage line VDD3.3V_AVDD. Capacitors C33 and C35 are connected in parallel between the analog voltage output pin AVDD and analog ground, acting as filters. This configuration helps smooth the power supply voltage, reduce voltage fluctuations and noise, thereby improving the stability and reliability of the circuit. Specifically, capacitor C35 is a high-frequency bypass capacitor with a capacitance of 1μF, used to bypass high-frequency interference signals introduced by the power supply; while capacitor C33 is used for filtering, and C35 has a capacitance of 0.1μF to further purify the power supply voltage.

[0064] The AD acquisition chip U7 includes a ground pin GND, which is connected to the ground terminal. A resistor R40 is connected in series between the ground terminal and the analog ground.

[0065] The AD acquisition chip U7 includes a digital voltage input pin DVDD, which connects to the 3.3V AD operating voltage line VDD3.3V_AD. This line connects to the AD power supply module, which provides the 3.3V AD operating voltage. Capacitors C34 and C35 are connected in parallel between the digital voltage input pin DVDD and ground, acting as filters. This configuration helps smooth the power supply voltage, reduce voltage fluctuations and noise, thereby improving circuit stability and reliability. Specifically, capacitor C36 is a high-frequency bypass capacitor with a capacitance of 1μF, used to bypass high-frequency interference signals introduced by the power supply; while capacitor C34 is used for filtering, with a capacitance of 0.1μF, to further purify the power supply voltage.

[0066] The AD acquisition chip U7 includes a clock signal input pin CLKIN, which is used to input a clock signal, so that each slave AD acquisition chip U7 can simultaneously acquire the CVT transformer fault signal.

[0067] The AD acquisition chip U7 includes a capacitor pin CAP, which is connected to the ground terminal. A capacitor C38 is connected in series between the capacitor pin CAP and the ground terminal.

[0068] In this application, the linear regulator U6 is model HE2210M533R, etc.

[0069] The linear regulator U6 is used to maintain voltage stability, protecting the AD acquisition module from voltage fluctuations and noise, thereby extending the lifespan and improving the performance of the AD acquisition module. The linear regulator U6 provides a stable output voltage and current by reducing the input voltage to the required level, ensuring that the load can operate normally regardless of voltage variations.

[0070] Linear regulator U6 includes a voltage input pin VIN, which is connected to the analog supply voltage AVCC. Linear regulator U6 also includes a ground pin GND, which is connected to analog ground. Linear regulator U6 includes an enable pin CE, which is also connected to the analog supply voltage AVCC. The linear regulator includes a voltage output pin VOUT, which outputs the analog operating voltage VDD3.3V_AVDD. Capacitors C31 and C32 are connected in parallel between the voltage output pin VOUT and analog ground, acting as filters. This configuration helps smooth the supply voltage, reduce voltage fluctuations and noise, thereby improving the stability and reliability of the circuit. Specifically, capacitor C31 is a high-frequency bypass capacitor with a capacitance of 22μF. C31 is a type B tantalum capacitor and is used to bypass high-frequency interference signals introduced by the power supply. Capacitor C32 is used for filtering; its capacitance is 0.1μF, further purifying the supply voltage.

[0071] The linear regulator U6HE2210M533R includes a high-performance voltage error amplifier (providing high regulation accuracy under transient conditions), an undervoltage lockout circuit (to prevent startup before the input voltage reaches 3.3V), an internally designed slow-start circuit (to limit inrush current), and a voltage feedforward circuit (to improve transient response).

[0072] It should be noted that "analog" refers to analog circuits and "digital" refers to digital circuits.

[0073] In this application, the crystal oscillator Y1 is model number 4.096M, etc.

[0074] Crystal oscillator Y1 is used to generate a highly stable oscillation frequency signal, providing a precise time reference for the AD acquisition chip. Crystal oscillator Y1 includes a voltage input pin VDD, which is connected to the 3.3V AD operating voltage line VDD3.3V_AD. A capacitor C42 is connected in series between the voltage input pin VDD and ground. Crystal oscillator Y1 includes a standby wake-up pin ST. Crystal oscillator Y1 includes a clock signal output pin CLK, which is connected to the clock signal input pin CLKIN of the AD acquisition chip. Crystal oscillator Y1 includes a ground pin GND, which is connected to the ground terminal.

[0075] The principle by which the AD acquisition module acquires fault signals from each CVT transformer is as follows:

[0076] The structure of a CVT transformer (capacitive voltage transformer) is as follows: Figure 7As shown, C1 consists of n1 capacitors of capacitance C connected in series, and C2 consists of n2 capacitors of capacitance C connected in series. The AD acquisition module detects the secondary voltage value and calculates the U2 value (the near-end voltage difference between C1 and C2) by a certain ratio, thereby determining the primary voltage value U1 (the far-end voltage difference between C1 and C2). By detecting the value of U2, it is determined whether capacitors C1 and C2 in the CVT transformer are damaged, whether the damage is specifically at C1 or C2, and the number of damaged capacitors.

[0077] Under normal conditions: U2 = U1 * n2 / (n1 + n2); (Formula 1)

[0078] If X capacitors are damaged in the case of C1: U2 = U1 * n2 / (n1 + n2 - X); (Formula 2)

[0079] If X capacitors are damaged by C2: U2 = U1 * (n2 - x) / (n1 + n2 - X); (Formula 3)

[0080] When X capacitors are damaged in C1: the voltage change rate K = (n1 + n2) / (n1 + n2 - X) - 1;

[0081] When X capacitors are damaged in C2: the voltage change rate K = [(n1+n2)*(n2-X)] / [(n1+n2-X)*n2]-1;

[0082] In summary, the following CVT transformer fault types are summarized as shown in Table 1:

[0083] Table 1. Fault Types of CVT Transformers

[0084]

[0085] Therefore, by determining the relationship between the secondary voltage U2 and its rated value under normal conditions, as well as the voltage change rate K, the specific CVT transformer fault can be identified.

[0086] The AD acquisition chip synchronously acquires analog signals, converts the analog signals into digital signals, and outputs the converted data to the slave MCU via the SPI serial port. The AD acquisition chip is triggered by the analog-to-digital conversion.

[0087] The AD acquisition module of this application improves the sampling accuracy of the AD acquisition module by using a linear regulator HE2210M533R; and improves the synchronization of the sampling data of each AD acquisition module by using a crystal oscillator Y1.

[0088] This application uses a 24-bit, 4-channel AD acquisition chip U7, which can accurately measure the voltage value on the secondary side of the CVT and ensure high accuracy of the equipment sampling.

[0089] like Figures 8-11 As shown, this application also provides an MCU control module adapted to a capacitive voltage transformer. The MCU control module includes a master MCU and a slave MCU, which communicate wirelessly or via wired connection.

[0090] Furthermore, the master MCU includes a master MCU chip and a master clock circuit; the slave MCU includes a slave MCU chip and a slave clock circuit.

[0091] This application also provides a clock chip module adapted to a capacitive voltage transformer, which includes a master clock circuit and a slave clock circuit. Both the master clock circuit and the slave clock circuit include a clock chip U14. In this application, the clock chip U14 is an RTC real-time clock chip of model RX80258.

[0092] The clock chip U14 includes a serial clock pin SCL, which is connected to the 3.3V MCU operating voltage line VDD3.3V_MCU. A resistor R79 is connected in series between the serial clock pin SCL and the 3.3V MCU operating voltage line VDD3.3V_MCU. In this application, the resistance of resistor R79 is 10KΩ. The serial clock pin SCL is used by the master MCU to control the data transmission of the slave MCU. When the SCL signal is high, the data on the data line is stable and can be sampled by the slave MCU. Alternatively, the serial clock pin SCL is used by the slave MCU to control the data transmission of the AD acquisition module. When the SCL signal is high, the data on the data line is stable and can be sampled by the AD acquisition module. During the period when SCL is low, the data on the data line can change to adapt to the next rising edge of SCL.

[0093] The clock chip U14 includes a serial data pin SDA, which is connected to the 3.3V MCU operating voltage line VDD3.3V_MCU. A resistor R80 is connected in series between the serial data pin SDA and the 3.3V MCU operating voltage line VDD3.3V_MCU. In this application, the resistance of resistor R80 is 10KΩ. The serial data pin SDA is responsible for serial data transmission between the host MCU and the slave MCU; alternatively, the serial data pin SDA is responsible for serial data transmission between the slave MCU and the AD acquisition chip.

[0094] The clock chip U14 includes a clock signal output pin FOUT, which is connected to the RTC_SCK line. The clock signal output pin FOUT generates clock pulses, which the host MCU sends to the slave MCU at a fixed rate during data transmission; alternatively, the slave MCU sends them to the AD acquisition module at a fixed rate. This clock pulse ensures that the sender and receiver perform data read or write operations at the correct time.

[0095] The clock chip U14 includes a voltage input pin VDD, which is connected to the operating voltage terminal VDD3.3V_MCU of the host MCU chip. A capacitor C71 is connected in series between the operating voltage terminal VDD3.3V_MCU of the host MCU chip and the ground terminal. In this application, the operating parameters of capacitor C71 are 0.1μF / 50V.

[0096] The clock chip U14 includes a ground pin GND, which is connected to the ground terminal.

[0097] The clock chip U14 includes an enable pin FOE, which is connected to the 3.3V MCU operating voltage line VDD3.3V_MCU. A resistor R81 is connected in series between the enable pin FOE and the 3.3V MCU operating voltage line VDD3.3V_MCU. In this application, the resistance of resistor R81 is 10KΩ.

[0098] The clock chip U14 includes an interrupt pin INT, which is connected to the 3.3V MCU operating voltage line VDD3.3V_MCU. A resistor R82 is connected in series between the interrupt pin INT and the 3.3V MCU operating voltage line VDD3.3V_MCU. In this application, the resistance of resistor R82 is 10KΩ.

[0099] Furthermore, both the host MCU and the slave MCU include a temperature compensation circuit, which includes a temperature-compensated crystal oscillator Y3. The temperature compensation circuit utilizes the change in crystal load reactance with temperature to compensate for the frequency-temperature characteristics of the crystal element, thereby reducing its frequency-temperature offset.

[0100] In this application, the temperature-compensated crystal oscillator Y3 is model TCXO-50M, etc.

[0101] The temperature-compensated crystal oscillator Y3 includes a power supply voltage pin VCC, which is connected to the 3.3V MCU operating voltage line VDD3.3V_MCU. A capacitor C80 is connected in series between the 3.3V MCU operating voltage line VDD3.3V_MCU and the ground terminal. The temperature-compensated crystal oscillator Y3 also includes a ground pin GND, which is grounded. Finally, the temperature-compensated crystal oscillator Y3 includes a clock signal output pin OUT, which is connected to the SYS_CLK line, thereby reducing the clock signal offset of the online monitoring device.

[0102] In this application, the host MCU chip and the slave MCU chip are both STM32L431RCT6, etc.

[0103] Both the master MCU chip and the slave MCU chip include the following pins:

[0104] Operating voltage pin VBAT: The operating voltage pin VBAT is connected to the 3.3V operating voltage VDD3.3V_MCU.

[0105] Clock signal input pin PC14-OSC32_IN: The clock signal input pin PC14-OSC32_IN is connected to the RTC_SCK line. The clock signal input pin PC14-OSC32_IN receives the clock pulse generated by the clock signal output pin FOUT through the RTC_SCK line.

[0106] Crystal oscillator connection pins PHO_OSC_IN and PHO_OSC_OUT: A crystal oscillator Y2 is connected in parallel between the crystal oscillator connection pins PHO_OSC_IN and PHO_OSC_OUT. Capacitors C66 and C68 are connected to ground at the two ends of crystal oscillator Y2, respectively. Crystal oscillator Y2 generates a highly stable oscillation frequency signal, providing a precise time base for the host / slave MCU chip.

[0107] MCU Reset Pin NRST: The MCU reset pin NRST is connected to the NRESET line and is used to reset the host MCU / slave MCU.

[0108] Wireless module reset pin PC1: Wireless module reset pin PC1 is connected to the ZIGB_RESET line. Wireless module reset pin PC1 is used to reset the host wireless module / slave wireless module.

[0109] AD power supply pin BAT_AD: The BAT_AD pin is used to connect the AD power module. It should be noted that the host MCU chip's AD power supply pin BAT_AD is not connected.

[0110] Slave output data pins PC2 and PC3: Slave output data pins PC2 and PC3 are connected to the 7616_MISOB line. Slave output data pins PC2 and PC3 are used for the slave to output data to the AD acquisition chip U7. When the model of AD acquisition chip U7 is AD7616H, slave output data pins PC2 and PC3 are used.

[0111] Analog ground pin VSSA / VREF-: The analog ground pin VSSA / VREF- is connected to the ground terminal.

[0112] Analog voltage input pin VDDA / VREF+: The analog voltage input pin VDDA / VREF+ is connected to the operating voltage terminal VDD3.3V_MCU.

[0113] Wake-up pin PA0: The wake-up pin PA0 is connected to the WAKE_up line. The wake-up pin PA0 of the master MCU chip is used to output the wake-up signal via the master pulse output, and the wake-up pin PA0 of the slave MCU chip is used to output the slave interrupt signal.

[0114] Synchronous sampling pin PA1: Synchronous sampling pin PA1 is connected to the Sync line. The synchronous sampling pin PA1 of the master MCU chip is used for master pulse output data, and the synchronous sampling pin PA1 of the slave MCU chip is used for slave interrupt output data.

[0115] Serial data transmit pin PA2: Serial data transmit pin PA2 is connected to the MCU_USART2_TX line. Serial data transmit pin PA2 is used to transmit master / slave serial data, specifically for the master to send serial data to the second group of slaves and for the second group of slaves to send serial data to the master.

[0116] Serial data receive pin PA3: Serial data receive pin PA3 is connected to the MCU_USART2_RX line. Serial data receive pin PA3 is used to receive serial data from the master / slave. Specifically, it is used for the master to receive serial data sent by the second group of slaves and for the second group of slaves to receive serial data sent by the master.

[0117] Ground pin VSS: Ground pin VSS is connected to the ground terminal.

[0118] Voltage input pin VDD: The voltage input pin VDD is connected to the operating voltage terminal VDD3.3V_MCU.

[0119] It should be noted that the grounding pin VSS and the voltage input pin VDD are set in 4 groups, corresponding to 1 group of master MCU chips and 3 groups of slave MCU chips respectively.

[0120] Serial current sampling pin PA4: The serial current sampling pin PA4 is connected to the SPI1_CS line and is used to detect the current of the serial data line.

[0121] Serial clock pin PA5: Serial clock pin PA5 is connected to the SPI1_SCLK line and is used for the slave device to receive the serial clock signal from the master device, or for the master device to receive the serial clock signal from the slave device.

[0122] Slave Serial Data Input Pin PA6: Slave serial data input pin PA6 connects to the SPI1_MISO line and is used for the slave MCU chip to input serial data from the AD acquisition chip U7. It should be noted that when the AD acquisition chip U7 is model ADS131, slave serial data input pin PA6 is used.

[0123] Slave serial data output pin PA7: Slave serial data output pin PA6 connects to the SPI1_MOSI line and is used by the slave MCU chip to output serial data to the AD acquisition chip U7. It should be noted that when the AD acquisition chip U7 is model ADS131, slave serial data output pin PA7 is used.

[0124] Serial data transmit pin PC4: Serial data transmit pin PC4 is connected to the MCU_USART3_TX line. Serial data transmit pin PC4 is used to transmit master / slave serial data, specifically for the master to send serial data to the third group of slaves and for the third group of slaves to send serial data to the master.

[0125] Serial data receive pin PC5: Serial data receive pin PC5 is connected to the MCU_USART3_RX line. Serial data receive pin PC5 is used to receive serial data from the master / slave. Specifically, it is used for the master to receive serial data sent by the third group of slaves and for the third group of slaves to receive serial data sent by the master.

[0126] AD acquisition chip reset pin PB0: AD acquisition chip reset pin PB0 is connected to the ADS131_RESET line. When the AD acquisition chip U7 is model ADS131, AD acquisition chip reset pin PB0 is used to reset the AD acquisition chip.

[0127] Data read status pin PB2: The data read status pin PB2 is connected to ADS131_DRDY. When the AD acquisition chip U7 is model ADS131, the data read status pin PB2 is used to: after the slave device completes data acquisition, the data read status pin PB2 will go low to notify the host MCU that the data is ready and can be read.

[0128] Serial clock pin PB10: The serial clock pin PB10 is connected to the 7616_SCLK line. When the AD acquisition chip U7 is model AD7616H, the serial clock pin PB10 is used to receive the serial clock signal from the AD acquisition chip U7.

[0129] Serial data pin PB11: Serial data pin PB11 is connected to the ROM_SDA line and is used for serial data transmission between the master and slave devices.

[0130] Wireless power module pin PB9: Pin PB9 connects to the ZIGB_POWER line, used to input power to the wireless power module via the ZIGB_POWER line. It should be noted that pin PB9 on the host MCU chip is not connected. The wireless power module is powered on when the AD power module voltage is greater than 7V, and powered off when the AD power module voltage is less than 6V.

[0131] AD power module pin PB8: Pin PB8 connects to the AD_POWER line and is used to input power to the AD power module through the AD_POWER line. It should be noted that pin PB8 on the host MCU chip is not connected. After the slave device wakes up, the AD power module is turned on. After the CVT fault information acquisition is complete, the AD power module is turned off.

[0132] Boot pins BOOT0 / PH3: By setting the state of boot pins BOOT0 / PH3, the boot mode after the host MCU chip / slave MCU chip is reset can be selected.

[0133] Serial data pin PB7: Serial data pin PB7 is connected to the RTC_SDA line, and Serial data pin PB7 is connected to the serial data pin SDA of the clock chip through the RTC_SDA line.

[0134] Serial clock pin PB6: Serial clock pin PB6 is connected to the RTC_SCL line, and Serial clock pin PB6 is connected to the serial clock pin SCL of the clock chip through the RTC_SCL line.

[0135] Clock interrupt pin PB5: Clock interrupt pin PB5 is connected to the RTC_INT line, and clock interrupt pin PB5 is connected to the interrupt pin INT of the clock chip through the RTC_INT line.

[0136] Clock enable pin PB4: The clock enable pin PB4 is connected to the RTC_FOE line, and the clock enable pin PB4 is connected to the enable pin FOE of the clock chip through the RTC_FOE line.

[0137] AD acquisition chip reset pin PB3: AD acquisition chip reset pin PB0 is connected to the 7616_RESET line. When the model of AD acquisition chip U7 is AD7616H, AD acquisition chip reset pin PB3 is used to reset AD acquisition chip.

[0138] PD2, the serial port data pin of the AD acquisition chip: The PD2 serial port data pin of the AD acquisition chip is connected to the 7616_SER1 line. When the model of the AD acquisition chip U7 is AD7616H, the PD2 serial port data pin of the AD acquisition chip is used to transmit the CVT fault data acquired by the AD acquisition chip U7 to the slave MCU chip.

[0139] Slave serial data output pin PC12: The slave serial data output pin PC12 connects to the 7616_MOSI line and is used by the slave MCU chip to output serial data to the AD acquisition chip U7. It should be noted that when the AD acquisition chip U7 is model AD7616H, the slave serial data output pin PC12 is used.

[0140] Slave Serial Data Input Pin PC11: The slave serial data input pin PC11 connects to the 7616_MISOA line and is used for the slave MCU chip to input serial data from the AD acquisition chip U7. It should be noted that when the AD acquisition chip U7 is model AD7616H, the slave serial data input pin PC11 is used.

[0141] It should be noted that when the AD acquisition chip U7 is model AD7616H, the slave MCU chip uses dual-channel serial data input.

[0142] Serial clock pin PC10: The serial clock pin PC10 is connected to the 7616_SCLK line. When the AD acquisition chip U7 is model AD7616H, the serial clock pin PC10 is used to receive the serial clock signal from the AD acquisition chip U7.

[0143] Serial current sampling pin PA15: The serial current sampling pin PA15 is connected to the 7616_CS line. When the AD acquisition chip U7 is model AD7616H, it is used to detect the current of one of the 7616 serial data lines.

[0144] Synchronous clock pin PA14: Synchronous clock pin PA14 is connected to the SWCLK line and is used to transmit clock signals to synchronize the data transmission process.

[0145] Serial communication pin PA13: Serial communication pin PA13 is connected to the SWDIO line. Serial communication pin PA13 can both send command data and receive information data returned by the chip.

[0146] LED pins PA12, PA11, and PC9: LED pins PA12, PA11, and PC9 are used to indicate fault signals for the three sets of CVTs monitored by the slave unit.

[0147] Serial data transmit pin PA10: Serial data transmit pin PA2 is connected to the MCU_USART1_TX line. Serial data transmit pin PA10 is used to transmit master / slave serial data. Specifically, it is used for the master to send serial data to the first group of slaves and for the first group of slaves to send serial data to the master.

[0148] Serial data receive pin PA9: Serial data receive pin PA9 is connected to the MCU_USART1_RX line. Serial data receive pin PA9 is used to receive serial data from the master / slave. Specifically, it is used for the master to receive serial data sent by the first group of slaves and for the first group of slaves to receive serial data sent by the master.

[0149] Digital-to-analog conversion pin PA8: The digital-to-analog conversion pin PA8 is connected to the 7616_CONVER line. When the AD acquisition chip U7 is model AD7616H, it is used for digital-to-analog conversion of the acquired signal.

[0150] Status feedback pin PC8: Status feedback pin PC8 is connected to the 7616_BUSY line. When the model of AD acquisition chip U7 is AD7616H, it is used for the processing status feedback of AD acquisition chip U7.

[0151] Synchronization voltage input pin PB14: The synchronization voltage input pin PB14 is connected to the 220_SYNC line and is used to input the synchronization voltage signal.

[0152] Clock signal transmission pin PB13: The clock signal transmission pin PB13 is connected to the ROM_SCL line and is used for clock signal transmission between the master and slave devices.

[0153] Serial current sampling pin PB12: The serial current sampling pin PB12 is connected to the 7616_CS line. When the AD acquisition chip U7 is model AD7616H, it is used to detect the current of the 7616 serial data line (second one).

[0154] like Figure 12 and Figure 13 As shown, the slave MCU further includes a slave power control circuit.

[0155] The slave power control circuit includes an AD battery control circuit, an MCU power control circuit, a wireless power control circuit, a first AD voltage conversion circuit, and a second AD voltage conversion circuit.

[0156] Among them, the AD battery control circuit is as follows Figure 14 As shown; the MCU power control circuit is as follows Figure 15 As shown; the wireless power control circuit is as follows Figure 16 As shown; the first AD voltage conversion circuit is as follows Figure 17 As shown; the second AD voltage conversion circuit is as follows Figure 18As shown.

[0157] The MCU power control circuit includes a linear regulator HE2210M533R; a wireless power control circuit; a first AD voltage conversion circuit including a linear regulator HE2210M550R; and a second AD voltage conversion circuit including a linear regulator HE2210M533R. Therefore, the slave power control circuit improves the voltage stability of the slave MCU, slave wireless module, AD acquisition module, and wireless power module.

[0158] like Figure 19 As shown, this application also provides a wired synchronization module adapted to a capacitive voltage transformer.

[0159] Furthermore, the online monitoring device includes a wired synchronization module, which is used to synchronize the clocks of the master and each slave device. Clock synchronization is achieved by connecting the clock-generating devices (in this application, the devices are: the master MCU chip and the slave MCU chip) to the SCL line. Each of these devices may have its own independent clock, and the frequency, period, phase, and duty cycle of each clock signal may be different. Due to the "wired AND" result, the low-level width of the actual clock generated on the SCL line is determined by the device with the longest low-level duration, while the high-level width is determined by the device with the shortest high-level duration.

[0160] The wired synchronization module includes: a synchronization current detection circuit and a timing circuit.

[0161] The synchronous current detection circuit includes a current detection chip U1. In this application, the current detection chip U1 is model REF3318AIDBZR, etc.

[0162] The current sensing chip U1 includes a signal input pin VI, which is connected to the 3.3V operating voltage synchronization signal line VDD3.3V_SYNC. The current sensing chip U1 also includes a signal output pin VO, which is connected to the current sensing signal output terminal VREF. Furthermore, the current sensing chip U1 includes a ground pin GND, which is connected to the ground terminal. A capacitor C1 is connected in series between the ground pin GND and the signal input pin VI, and a capacitor C2 is connected in series between the ground pin GND and the signal output pin VO.

[0163] The timing circuit includes connector J1, array resistors, reverse protection diode D1, operational amplifier comparator U2, and operational amplifier comparator U3.

[0164] In this application, connector J1 adopts a single-row 2-pin connector of model HDR1x2. The two interfaces of connector J1 are respectively connected to three array resistors and then connected to the two input terminals of operational amplifier comparator U2.

[0165] In this application, the reverse protection diode D1 is of the type BAT54S, etc. The reverse protection diode D1 and capacitor C5 are connected in parallel between the two input terminals 2 and 3 of the operational amplifier comparator U2.

[0166] In this application, the operational amplifier comparator U2 is model INA333AIDGKR, etc., and the operational amplifier comparator U2 is a single operational amplifier integrated chip; the operational amplifier comparator U3 is model ADA4891-2, etc., and the operational amplifier comparator U3 is a dual operational amplifier integrated chip.

[0167] The two input terminals 2 and 3 of operational amplifier comparator U2 are each connected to ground via a resistor connected in series. The positive voltage terminal 7 of operational amplifier comparator U2 is connected to the 3.3V operating voltage synchronization signal line VDD3.3V_SYNC, and is connected to ground via a capacitor C3 connected in series. The negative voltage terminal 4 of operational amplifier comparator U2 is grounded. A resistor R2 is connected in series between the battery terminal 1 and the normally closed contact terminal 8 of operational amplifier comparator U2. The battery terminal 5 of operational amplifier comparator U2 is connected to the current detection signal output terminal VREF via a resistor R6 connected in series. The output terminal 6 of operational amplifier comparator U2 is connected to the negative input terminal A2 of operational amplifier comparator U3 via a resistor R11 connected in series.

[0168] The positive input terminal A3 of operational amplifier comparator U3 is connected to the current detection signal output terminal VREF via a series resistor R13. The positive voltage terminal 8 of operational amplifier comparator U3 is connected to the 3.3V operating voltage synchronization signal line VDD3.3V_SYNC. The positive voltage terminal 8 of operational amplifier comparator U3 is grounded via a series capacitor C4; the negative voltage terminal 4 of operational amplifier comparator U3 is grounded. The output terminal A1 of operational amplifier comparator U3 is connected to the positive input terminal A3 via a series resistor R10. The output terminal A1 of operational amplifier comparator U3 is grounded via series resistors R1 and R4. The 220_SYNC line is connected between resistors R1 and R4 via a series resistor R3.

[0169] The wired synchronization module performs timing state transitions through logical operations of the timing circuit, thereby synchronizing the clocks (VDD3.3V_SYNC) of each slave device with the clock (220_SYNC) of the master device. Specifically, the wired synchronization module receives the master time reference signal (220VSYNC) and outputs time synchronization signals and time information (VDD3.3V_SYNC) to the slave devices according to the required time precision. This ensures that the slave clock signals are aligned and synchronized with the master clock signals, enabling the AD acquisition modules of each slave device to synchronously acquire fault signals from each set of CVT transformers.

[0170] Based on the above-mentioned online monitoring device for capacitive voltage transformers, this application also provides a wireless networking and communication method for capacitive voltage transformers, including:

[0171] Configure at least one master and multiple slave devices, with wireless communication between the master and the multiple slave devices;

[0172] The host and each slave device exchange information via wireless synchronization messages: the host converts the constructed Ethernet-format synchronization message into a wireless network-format message and transmits it to the slave device;

[0173] The host sends time setting commands to the slave device periodically by broadcasting wireless network format messages to the slave device.

[0174] The host converts the received wireless network packets into Ethernet format, determines the packet type, and extracts its key information for further logical processing.

[0175] The master broadcasts a wake-up command to the slave to wake it up; at other times, the slave is in sleep mode.

[0176] After the slave device disconnects or loses connection, the host will periodically wake up the slave device and reconnect it to the wireless network.

[0177] In this application, the host sends a time setting command to the slave device every 1 day.

[0178] Furthermore, in wireless network scenarios, the transmission of messages between the host and each slave device relies on the 802.11 protocol. At the data link layer, the 802.1AS messages required for path delay measurement and time synchronization measurement are encapsulated into 802.11 data frames for protocol transmission.

[0179] 802.1AS messages include:

[0180] (1) majorSdoId: occupies 4 bits.

[0181] (2) messageType: Occupies 4 bits and indicates the type of message. It is used to distinguish between event messages and ordinary messages.

[0182] Its most significant bit is 0 to represent an event message and 1 to represent a normal message.

[0183] (3) minorVersionPTP: Occupies 4 bits. For transmitted messages, this value is 1. For received messages, this value is 1.

[0184] The value was ignored.

[0185] (4) versionPTP: Occupies 4 bits and represents the version number of the protocol. The version number of gPTP messages is 2.

[0186] (5) messageLength: Occupies 16 bits and represents the total length of the message. This includes the length from the message header to the end of the message.

[0187] The next one.

[0188] (6) domainNumber: occupies 8 bits and represents the gPTP domain number of the message sending device.

[0189] (7) minorSdoId: Occupies 8 bits, this value is specified. If the received message does not contain one of the specified values,

[0190] Then it will be ignored.

[0191] (8) flags: occupies 16 bits, each bit of each node represents a characteristic of the network node.

[0192] (9) CorrectionField: Occupies 64 bits and represents the correction field.

[0193] (10) messageTypeSpecific: Occupies 32 bits and indicates the specific type of message.

[0194] (11) sourcePortIdentity: Occupies 80 bits. This value is the PTPPort of the PTP port that transmits PTP messages.

[0195] The identity attribute.

[0196] (12) sequenceId, occupying 16 bits, represents the sequence number. The sequence number increments by 1 each time a message of the same type appears.

[0197] When different messages have the same sequence number, it indicates that these messages are related. For example, the sequence numbers of Sync and Follow_Up messages are the same.

[0198] If the column numbers are the same, it means that the two frames are related, and the timing information carried in Follow_Up corresponds to this same sequence.

[0199] The Sync frame of number 1.

[0200] (13) controlField: occupies 8 bits, and its value is 0.

[0201] (14) logMessageInterval: occupies 8 bits and represents the message sending interval in logarithmic form.

[0202] Furthermore, to minimize interference from other wireless signals in the same frequency band, this application employs an FPGA+SDR structure to implement wireless message transmission in a specific frequency band. In the wireless message receiving section, an analog-to-digital converter directly connected to the SDR is designed first to handle the reception of the radio frequency signal. Secondly, OFDM is used to demodulate the data and convert the bitstream, recording the message reception time. Finally, the data and message reception time are sent to the host server for subsequent processing.

[0203] Furthermore, in the initial stage, the host server issues configuration information such as gating time slots to complete the configuration of the transmission queue gating list. Then, according to the configured gating, the transmission of the synchronization message data output by the host server is scheduled. Next, the data output rate is matched for the radio frequency signal and digital-to-analog conversion is completed. Finally, the wireless message is sent to the host wireless module through cross-clock domain transmission.

[0204] Furthermore, the host sends time setting commands to the slave device periodically via broadcast commands in the slave device's wireless network format message, including:

[0205] The master node receives and parses the status information messages reported by each slave node, extracts three decision attributes for master clock selection: link congestion coefficient, link topology, and clock source parameter set, and establishes a master clock selection model based on the received information.

[0206] The master node calculates the optimal weight values ​​corresponding to the three decision attributes based on the multi-attribute decision algorithm, substitutes them into the calculation to obtain the clock attribute values ​​of each node, compares them to obtain the best master clock node and generates a redundant clock sequence.

[0207] The host server periodically queries the optimal master clock node, sets a timeout threshold, and restarts the timeout count upon receiving a new status report message. If the synchronization centralized control node does not receive any new report information within the timeout count threshold, it assumes that the master clock node has unexpectedly failed, updates the master clock node information and redundant clock sequences, and distributes them to each slave node.

[0208] The system monitors whether any new time-sensitive nodes have joined the network. If a new node has joined, it receives and calculates the clock attribute value of that node, compares it with the original master clock node and redundant clock sequences, and updates the above information.

[0209] Furthermore, the host server determines whether the input data packet is a synchronization packet. If it is not a synchronization packet, it is directly output to the subsequent switch function module. If it is a synchronization packet, the corresponding synchronization information is recorded or extracted according to the specific synchronization packet type.

[0210] Furthermore, the host server receives the redundant clock sequence list from the master node, confirms the optimal master clock identifier, and updates its local redundant clock sequence list. The synchronization messages sent by the slave nodes include status information messages containing their own clock source parameters, link topology, link congestion, and other network information, which are reported to the master node.

[0211] Furthermore, this application adopts a master-node request-slave-node response mode, sending or responding to delay request messages, and calculating the link delay values ​​of adjacent nodes considering the adjacent frequency ratio and link asymmetry. A Kalman filter algorithm is used to filter the measured values ​​to reduce synchronization errors. Simultaneously, link congestion is estimated by sending link probe packets, and the link congestion coefficient of adjacent links of the measured node is determined by comparing the difference between the packet departure interval and the arrival interval to see if it exceeds a time threshold.

[0212] Furthermore, the host constructs or forwards synchronization information messages based on the local port role. If all ports are master ports, a two-step method is used to construct the synchronization message and send the follow-up message to the other nodes. If a port is a slave clock port and the other ports are master ports, the host receives the synchronization message, calculates and corrects the local synchronization clock deviation, adds the local dwell time to the synchronization message correction field, and forwards it to the other slave clock ports. In other cases, the host only receives the synchronization message and does not perform any forwarding operation.

[0213] The wireless networking and communication method for capacitive voltage transformers proposed in this application, along with the related technical implementation details, brings the following significant benefits:

[0214] 1. Improve monitoring efficiency and accuracy:

[0215] By configuring the master unit and multiple slave units for wireless communication, real-time monitoring of capacitive voltage transformers (CVTs) is achieved, significantly improving monitoring efficiency and accuracy. The master unit can periodically send time setting commands to the slave units, ensuring time synchronization of all devices in the network, thereby guaranteeing the real-time nature and accuracy of the monitoring data.

[0216] 2. Reduce communication interference and energy consumption:

[0217] Employing an FPGA+SDR architecture to achieve wireless message transmission in a specific frequency band effectively reduces interference from other wireless signals in the same band, improving communication stability and reliability. Simultaneously, the master unit broadcasts a wake-up command to the slave unit to wake it up, and keeps the slave unit in sleep mode at other times, significantly reducing energy consumption.

[0218] 3. Optimize master clock selection and redundancy mechanism:

[0219] The host receives and parses the status information messages reported by each slave node, establishes a master clock selection model, and calculates the optimal weight value based on a multi-attribute decision algorithm to select the best master clock node. Simultaneously, a redundant clock sequence is established. When the master clock node fails, the host can quickly update the master clock node information and the redundant clock sequence and distribute them to each slave node, ensuring network stability and reliability.

[0220] 4. Improve synchronization accuracy and anti-interference capability:

[0221] This application adopts a master-node request-slave-node response model, sending or responding to delay request messages, and calculating the link delay values ​​of adjacent nodes considering the adjacent frequency ratio and link asymmetry. Simultaneously, a Kalman filter algorithm is used to filter the measured values, further reducing synchronization errors. Furthermore, link congestion is estimated by sending link probe packets, and the communication strategy is adjusted based on the link congestion coefficient, improving the network's anti-interference capability.

[0222] 5. Flexibility and scalability:

[0223] The wireless networking and communication method described in this application offers high flexibility and scalability. The host can dynamically update the master clock node information and redundant clock sequences based on whether new time-sensitive nodes join the network. Simultaneously, slave nodes can also perform corresponding operations based on commands from the host, enabling dynamic adjustment and expansion of the network.

[0224] 6. Reduce maintenance costs:

[0225] By enabling wireless networking and communication for CVTs, the wiring and maintenance work required for wired connections are reduced, thus lowering maintenance costs. Simultaneously, the ability to monitor the CVT's operating status in real time allows for the timely detection and handling of potential problems, reducing downtime and repair costs due to equipment failures.

[0226] In summary, the wireless networking and communication method for capacitive voltage transformers proposed in this application has many beneficial effects, including improving monitoring efficiency and accuracy, reducing communication interference and energy consumption, optimizing master clock selection and redundancy mechanisms, improving synchronization accuracy and anti-interference capability, enhancing flexibility and scalability, and reducing maintenance costs.

[0227] Based on the above-mentioned online monitoring device for capacitive voltage transformers, this application provides an online monitoring method for capacitive voltage transformers, which includes:

[0228] Configure at least one master and multiple slaves, with wireless and / or wired communication between the master and the multiple slaves;

[0229] Each slave unit includes a slave MCU and an AD acquisition module. The slave MCU drives the AD acquisition module to collect fault signals of each CVT transformer. Each AD acquisition module starts collecting CVT transformer fault signal data at the same time, ensuring the consistency and synchronization of the CVT transformer fault signal data acquisition time.

[0230] The AD acquisition module transmits the CVT transformer fault signal data to the slave MCU. Each slave MCU transmits the CVT transformer fault signal data to the host via wireless and / or wired signal transmission.

[0231] The host reads and saves all CVT transformer fault signal data from the slave devices;

[0232] The master compares the CVT transformer fault signal data of multiple slave devices at the same time, and compares the historical CVT transformer fault signal data of the same slave device. Based on the data performance, the master analyzes the data and determines the fault point.

[0233] The host computer issues alarm information based on the fault location.

[0234] With the above settings, the online monitoring method for capacitive voltage transformers of this application can realize the acquisition of fault signals from multiple CVT transformers.

[0235] As one implementation method, each AD acquisition module simultaneously starts acquiring CVT transformer fault signal data, including: the AD acquisition module detects the secondary side voltage value, calculates the near-end voltage difference U2 value of the two capacitors C1 and C2 of the CVT transformer, and thus determines the far-end voltage difference U1 value of C1 and C2 on the primary side.

[0236] The host computer uses the value of U2 to determine whether capacitors C1 and C2 in the CVT transformer are damaged, whether the damage is specifically at C1 or C2, and the number of damaged capacitors.

[0237] Furthermore, the host computer determines the specific CVT transformer fault by judging the relationship between the secondary voltage U2 and its rated value under normal conditions, as well as the voltage change rate K.

[0238] When there is no output of secondary voltage U2, it is determined that the primary and secondary windings of the intermediate transformer are open or short-circuited.

[0239] When the secondary voltage U2 decreases, it is determined that capacitor C2 is broken down;

[0240] When the secondary voltage U2 increases, it is determined that capacitor C1 is broken down;

[0241] When the waveform of the secondary voltage U2 is distorted, it is judged that the CVT transformer is heavily polluted, the line has high harmonic content, frequent reclosing, and the neutral point voltage is rising.

[0242] This application provides monitoring data obtained through the online monitoring method of the above-mentioned capacitive voltage transformer, such as... Figure 20 As shown.

[0243] As an alternative implementation, each of the A, B, and C phases of the CVT transformer is connected to a current transformer. The value of the three-phase leakage current is transmitted through the current transformers. A resistor is connected in parallel to the three current transformers, and the three current transformers are grounded through this resistor. A capacitor is connected in parallel next to this resistor to ensure the safety of the detection circuit.

[0244] Because one capacitor in the C2 capacitor divider of the CVT has broken down, the capacitance of C2 has increased by 4.35% compared to its rated value (the C2 capacitor divider consists of 23 identical components connected in series; calculations show that the breakdown of one component increases the capacitance by 4.3%). This causes a change in the capacitor division ratio, resulting in a drop in the CVT secondary voltage. Therefore, monitoring the changes in the CVT secondary voltage or the resistance U0 of the series resistors connected to the three-phase current transformers is more sensitive.

[0245] Furthermore, since three-phase voltage fluctuations or imbalances can affect the measurement, correction parameters can be added to the measurement system. By simultaneously measuring the three-phase current and voltage, the coefficients kA, kB, and kC of each phase can be calculated. The current values ​​of the three phases are then multiplied by 1 / kA, 1 / kB, and 1 / kC respectively, and the leakage current vectors under the rated voltage are added together, thereby eliminating the influence caused by three-phase voltage fluctuations or imbalances.

[0246] Furthermore, if the three-phase voltage imbalance of the CVT is found to exceed 3%, and the voltage of other windings (CVT generally has 3 windings a1x1, a2x2, afxf) is compared, if the trend of change is consistent, the defect should be reported. At the same time, the change in capacitance should be observed. If the change rate exceeds 4%, the power should be cut off and the CVT should be taken out of operation.

[0247] Furthermore, by collecting the capacitance and dielectric loss factors of the CVT online, and comparing the trend of these indicators with those of other equipment on the same busbar and in the same phase, if the values ​​continue to increase over a certain period, it indicates that there is a problem with the CVT insulation.

[0248] In summary, the online monitoring method for capacitive voltage transformers of this application can analyze the insulation defects of the CVT when there is a short circuit fault in the capacitive voltage divider of the CVT and the capacitance and dielectric loss factor change significantly during online monitoring. This can be achieved by combining the rate of change of capacitance with the secondary voltage curve of the CVT and the three-phase changes for comprehensive judgment.

[0249] Furthermore, in actual operation, the heat generated in areas with insulation defects usually increases. By using infrared thermography to monitor the temperature changes of the CVT, and in conjunction with online fault diagnosis, the monitoring of the CVT's heat generation can be strengthened, effectively preventing accidents from occurring.

[0250] The online monitoring method and implementation of the capacitive voltage transformer in this application bring the following significant benefits:

[0251] 1. Real-time monitoring and fault early warning:

[0252] By setting up a master unit and multiple slave units, real-time monitoring of capacitive voltage transformers (CVTs) is achieved, enabling timely detection of CVT anomalies and providing early warning information to maintenance personnel, thus preventing power grid accidents caused by equipment failures.

[0253] 2. High-precision data acquisition:

[0254] The AD acquisition module was used to simultaneously acquire CVT transformer fault signal data, ensuring the time consistency and synchronization of data acquisition and improving the accuracy and reliability of the data.

[0255] 3. Intelligent fault analysis:

[0256] The master unit can compare the CVT transformer fault signal data of multiple slave units at the same time, as well as the historical CVT transformer fault signal data of the same slave unit. Through data analysis, the fault point is determined and an alarm message is issued, thus realizing intelligent fault analysis.

[0257] 4. Accurate fault location:

[0258] By detecting the secondary side voltage value, calculating the near-end voltage difference U2 of the two capacitors C1 and C2 of the CVT transformer, and judging the far-end voltage difference U1 of C1 and C2 on the primary side, the fault location of the CVT transformer can be accurately determined, including whether capacitors C1 and C2 are damaged, the specific location of the damage, and the number of damaged capacitors.

[0259] 5. Multiple fault diagnosis criteria:

[0260] In addition to judging faults by voltage values, a comprehensive judgment can be made by combining multiple parameters such as voltage change rate K and voltage U0 of the series resistance after the three-phase current transformers are interconnected, which improves the accuracy of fault judgment.

[0261] 6. Eliminate the effects of three-phase voltage fluctuations:

[0262] By incorporating correction parameters into the measurement system and simultaneously measuring the three-phase current and voltage, the coefficients of each phase are calculated, thereby eliminating the influence of three-phase voltage fluctuations or imbalances and improving the accuracy of the measurement.

[0263] 7. Comprehensive assessment of insulation defects:

[0264] By collecting CVT capacitance and dielectric loss factors online, and combining them with CVT secondary voltage curves and three-phase changes, insulation defects of CVT can be comprehensively judged, improving the reliability and accuracy of fault diagnosis.

[0265] 8. Infrared temperature measurement-assisted monitoring:

[0266] By using infrared thermography to monitor CVT temperature changes and combining this with online fault diagnosis, the monitoring of CVT operation and heat generation has been strengthened, effectively preventing accidents from occurring.

[0267] 9. Reduce maintenance costs:

[0268] Through real-time monitoring and intelligent fault analysis, potential problems can be identified and addressed in a timely manner, reducing downtime and maintenance costs caused by equipment failure.

[0269] 10. Improve power grid stability:

[0270] It enables real-time monitoring and fault early warning of CVT, improves the stability and reliability of the power grid, and ensures the safe operation of the power grid.

[0271] In summary, the online monitoring method and implementation of the capacitive voltage transformer of this application have many beneficial effects, which not only improve monitoring efficiency and accuracy, but also reduce maintenance costs and improve the stability and reliability of the power grid.

[0272] It should be noted that the terms "first," "second," and similar terms used in this application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates at least two. Unless otherwise stated, terms such as "front," "back," "left," "right," "lower," and / or "upper" are for illustrative purposes only and are not limited to a location or spatial orientation. Terms such as "comprising" or "including" indicate that the elements or objects preceding "comprising" encompass the elements or objects listed following "comprising" or "including" and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0273] The singular forms “a,” “the,” and “the” used in this application specification and appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0274] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. An AD acquisition module adapted to a capacitive voltage transformer, wherein a slave MCU is connected to the AD acquisition module through an SPI line used for serial communication between the slave MCU and the AD acquisition module, and the AD acquisition module is connected to a plurality of CVT transformers and used to acquire fault signals of each CVT transformer. Characterized in that, the AD acquisition module comprises an AD acquisition chip U7, a linear voltage stabilizer U6 and a crystal oscillator Y1, the linear voltage stabilizer U6 is connected to the AD acquisition chip U7, the crystal oscillator Y1 is connected to the AD acquisition chip U7, the AD acquisition chip U7 comprises a plurality of groups of acquisition pins, each group of acquisition pins comprises a positive input pin and a negative input pin, the positive input pin is connected to a live wire of a CVT transformer, and the negative input pin is connected to a zero wire of the CVT transformer.

2. The AD acquisition module adapted to a capacitive voltage transformer according to claim 1, characterized in that, The AD acquisition chip U7 comprises an analog ground pin AGND connected to an analog ground, the AD acquisition chip U7 comprises an analog voltage output pin AVDD connected to a 3.3V analog working voltage line VDD3.3V_AVDD, the capacitor C33 and the capacitor C35 are connected in parallel between the analog voltage output pin AVDD and the analog ground, the AD acquisition chip U7 comprises a ground pin GND connected to a ground end, and the ground end and the analog ground are connected in series through a resistor R40, the AD acquisition chip U7 comprises a digital voltage input pin DVDD connected to a 3.3V AD working voltage line VDD3.3V_AD, the 3.3V AD working voltage line VDD3.3V_AD is connected to an AD power module, the capacitor C34 and the capacitor C35 are connected in parallel between the digital voltage input pin DVDD and the ground end, the AD acquisition chip U7 comprises a clock signal input pin CLKIN, and the AD acquisition chip U7 comprises a capacitor pin CAP connected to the ground end, and the capacitor pin CAP and the ground end are connected in series through a capacitor C38.

3. The AD acquisition module adapted to a capacitive voltage transformer according to claim 1 or 2, characterized in that, The AD acquisition chip U7 is of an AD7616H or ADS131 type.

4. The AD acquisition module adapted to a capacitive voltage transformer of claim 1, wherein, The linear voltage stabilizer U6 comprises a voltage input pin VIN connected to an analog power supply voltage AVCC, the linear voltage stabilizer U6 comprises a ground pin GND connected to the analog ground, the linear voltage stabilizer U6 comprises an enable pin CE connected to the analog power supply voltage AVCC, the linear voltage stabilizer comprises a voltage output pin VOUT outputting an analog working voltage VDD3.3V_AVDD, and the capacitor C31 and the capacitor C32 are connected in parallel between the voltage output pin VOUT and the analog ground.

5. The AD acquisition module adapted to a capacitive voltage transformer according to claim 1 or 4, characterized in that, The linear voltage stabilizer U6 is of an HE2210M533R type.

6. The AD acquisition module adapted to a capacitive voltage transformer of claim 1, wherein, The crystal oscillator Y1 includes a voltage input pin VDD connected with a 3.3V AD working voltage line VDD3.3V_AD, and a capacitor C42 connected in series between the voltage input pin VDD and a ground terminal; the crystal oscillator Y1 includes a standby wake-up pin ST; the crystal oscillator Y1 includes a clock signal output pin CLK connected with a clock signal input pin CLKIN of the AD acquisition chip U7; the crystal oscillator Y1 includes a ground pin GND connected with the ground terminal.

7. The AD acquisition module adapted to a capacitive voltage transformer according to claim 1 or 6, characterized in that, The model of the crystal oscillator Y1 is 4.096M.

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