Digital signal amplification circuit

Abstract

The utility model discloses a digital signal amplification circuit, and relates to the technical field of digital signal control, the digital signal amplification circuit comprises a voltage stabilizing circuit and a signal enhancement circuit, an input end of the voltage stabilizing circuit is connected with a voltage input end and is used for receiving a starting voltage, and an output end of the voltage stabilizing circuit is connected with an input end of the signal enhancement circuit and is used for providing a stable voltage reference; the signal enhancement circuit comprises a signal input end, a voltage division module, a signal transmission module and a signal output end. The signal input end is connected with the signal transmission module to input a high-frequency digital signal, the voltage dividing module is connected with the signal transmission module, the amplitude of the high-frequency digital signal is increased by adjusting the resistance value of the voltage dividing module, and the signal output end is connected with the signal transmission module to output the amplified digital signal to a load. The signal strength is enhanced by dynamically adjusting the output amplitude, it is ensured that the signal strength is still higher than the threshold value of the receiving end after long-distance transmission, and misjudgment is avoided; the simple design of the MOS tube and the resistor is adopted to replace the traditional repeater, so that the cost and the circuit complexity are reduced.

Description

Technical Field

[0001] This application relates to the field of digital signal processing, and in particular to a digital signal amplifier circuit. Background Technology

[0002] High-frequency signals are affected by impedance and parasitic capacitance on transmission lines, leading to signal attenuation and waveform distortion. Impedance mismatch causes signal reflection, while parasitic capacitance, together with the line resistance, forms a low-pass filter, further attenuating high-frequency components. When the signal amplitude drops to a certain level (e.g., half of its maximum amplitude), the receiver may fail to correctly identify a high level, misinterpreting it as a low level, thus triggering control anomalies.

[0003] While traditional repeater solutions can extend signal transmission distance, their drawbacks are also quite significant. They substantially increase hardware costs, complicate circuitry, and require additional power supply modules and signal shaping circuits. In multi-node systems, they can also lead to cascading failure risks, such as signal interference and delays, affecting the stability and reliability of the entire system, and are relatively expensive.

[0004] A low-cost circuit needs to be designed to address the problem of high-frequency digital signals being easily distorted and attenuated during long-distance transmission. Utility Model Content

[0005] In order to enable distortion-free transmission of high-frequency digital signals and enhance signal amplitude, this application provides a digital signal amplifier circuit.

[0006] This application provides a digital signal amplifier circuit, which adopts the following technical solution:

[0007] A digital signal amplification circuit includes: a voltage regulator circuit and a signal enhancement circuit. The input terminal of the voltage regulator circuit is connected to a voltage input terminal to receive a startup voltage. The output terminal of the voltage regulator circuit is connected to the input terminal of the signal enhancement circuit to provide a stable voltage reference and ensure the stable operating voltage of the signal enhancement circuit. The voltage regulator circuit and the signal enhancement circuit share a common ground. The signal enhancement circuit includes: a signal input terminal, a voltage divider module, a signal transmission module, and a signal output terminal. The signal input terminal is connected to the signal transmission module to input a high-frequency digital signal. The voltage divider module is connected to the signal transmission module to increase the amplitude of the high-frequency digital signal by adjusting the resistance value of the voltage divider module. The signal output terminal is connected to the signal transmission module to output the amplified digital signal to the load.

[0008] By adopting the above technical solution, the output amplitude is dynamically increased by adjusting the voltage divider module to compensate for voltage attenuation during long-distance transmission. Increasing the resistance value of the voltage divider resistor increases the voltage value divided by the voltage divider resistor, thereby increasing the amplitude of the high-frequency digital signal at the signal output terminal.

[0009] Optionally, the voltage regulator circuit includes: a constant voltage controller, a first capacitor and a second capacitor. The input terminal of the constant voltage controller is connected to the voltage input terminal. One end of the first capacitor is connected to the input terminal of the constant voltage controller, and the other end of the first capacitor is grounded. The output terminal of the constant voltage controller is connected to the second capacitor, and the other end of the second capacitor is grounded. The constant voltage controller is also grounded.

[0010] By adopting the above technical solution, the operating voltage of the amplifier circuit is ensured to be stable, avoiding the impact of power supply fluctuations on signal quality. The first capacitor is used for input filtering to suppress power supply noise, and the second capacitor reduces output ripple.

[0011] Optionally, the voltage divider module includes: a first resistor and a second resistor, the first resistor being connected to the output terminal of the constant voltage controller, the first resistor and the second resistor being connected in series, the second resistor being grounded, and the voltage divider node being between the first resistor and the second resistor.

[0012] By adopting the above technical solution, the first resistor and the second resistor form a voltage divider network. The amplitude of the output signal can be changed by adjusting the resistance value of the second resistor. By adjusting the resistance value of the second resistor, different transmission distances and load conditions can be adapted.

[0013] Optionally, the signal transmission module includes: an N-channel MOSFET and a P-channel MOSFET. The signal input terminal is connected to one end of a third resistor, and the other end of the third resistor is connected to the gate of the N-channel MOSFET. A sixth resistor is connected in parallel between the gate and source of the N-channel MOSFET. The source of the N-channel MOSFET is grounded. The drain of the N-channel MOSFET is connected to the gate of the P-channel MOSFET. A fifth resistor is connected in parallel between the gate and source of the P-channel MOSFET. The source of the P-channel MOSFET is connected to a voltage divider node.

[0014] By adopting the above technical solution, when the input is high, the gate of the N-channel MOSFET is pulled high, the source is grounded, the drain voltage is close to 0V, the N-channel MOSFET is turned on, the voltage divider node is pulled down to low level through the fifth resistor, the gate of the P-channel MOSFET is pulled low, the source is connected to the voltage divider node, the drain output voltage is the divided voltage value, and the output is high level; when the input is low, the gate of the N-channel MOSFET is cut off, the drain of the N-channel MOSFET is floating, the gate of the P-channel MOSFET is pulled high by the voltage divider node, the P-channel MOSFET is cut off, and the output is low level; the fifth resistor avoids the voltage divider network being affected by the floating state of the drain of the N-channel MOSFET, keeping the source voltage of the P-channel MOSFET determined by the pure voltage divider network, ensuring a stable low output level.

[0015] Optionally, a fourth resistor is connected in series with the drain of the P-channel MOSFET, the fourth resistor is grounded, and the signal output terminal is connected between the drain of the P-channel MOSFET and the fourth resistor.

[0016] By adopting the above technical solution, the P-channel MOSFET current limiting protection limits the current when the PMOS is on, preventing the device from overheating and being damaged. It forms a voltage divider network with the on-resistance of the P-channel MOSFET to determine the drain output voltage. When the P-channel MOSFET is off, the drain voltage is pulled down to ground potential through the resistor to avoid floating.

[0017] Optionally, the first capacitor may be a small-capacity ceramic capacitor, and the second capacitor may be a large-capacity electrolytic capacitor.

[0018] By adopting the above technical solutions, high-frequency noise, such as switching power supply noise, is filtered out, and low-frequency ripple, such as power frequency interference, is suppressed, thus covering the full-band filtering requirements.

[0019] Optionally, the first resistor is a fixed resistor, and the second resistor is an adjustable resistor.

[0020] By adopting the above technical solution, the voltage division ratio is dynamically adjusted according to the transmission distance, and the resistance value of the second resistor is adjusted to adapt to different transmission distances and load conditions.

[0021] In summary, this application includes at least one of the following beneficial effects:

[0022] 1. By actively adjusting the output amplitude, the signal is ensured to remain above the high-level threshold at the receiving end after transmission, thus enhancing the anti-attenuation capability of the digital signal amplifier circuit;

[0023] 2. By adjusting the resistance value of the voltage divider, it can be adapted to different transmission distances and load conditions, increasing the flexibility of circuit use;

[0024] 3. No complex signal shaping or relay circuits are required, resulting in low cost and high reliability. Attached Figure Description

[0025] Figure 1 This is a block diagram of one implementation of a digital signal amplifier circuit;

[0026] Figure 2 This is a schematic diagram of the circuit structure of one implementation of a digital signal amplifier circuit;

[0027] Figure 3 This is a circuit schematic diagram of an embodiment of a digital signal amplifier circuit;

[0028] Explanation of reference numerals in the attached diagram: 1. Voltage regulator circuit; 2. Signal enhancement circuit; 3. Voltage divider module; 4. Signal transmission module. Detailed Implementation

[0029] The following combination Figures 1 to 3 This application will be described in further detail.

[0030] This application discloses a digital signal amplification circuit, such as... Figure 1As shown, the digital signal amplification circuit includes a voltage regulator circuit 1 and a signal enhancement circuit 2. High-frequency digital signals are prone to signal attenuation and waveform distortion during long-distance transmission. When the signal amplitude is lower than the load's identifiable threshold, the load may misinterpret it as a low level, triggering control abnormalities. The digital signal amplification circuit uses the voltage regulator circuit 1 to receive the power supply's startup voltage, suppressing power fluctuations and high-frequency noise. The signal enhancement circuit 2 dynamically amplifies the signal amplitude, compensates for transmission losses, effectively restores signal integrity, and ensures reliable identification of high and low level thresholds, thereby avoiding false triggering and improving system stability.

[0031] like Figure 2 As shown, the voltage regulator circuit 1 includes a constant voltage controller and a filter capacitor. The filter capacitor is connected in parallel at the input and output terminals of the constant voltage controller to filter out high-frequency noise from the power supply and absorb low-frequency ripple from the load. The signal enhancement circuit 2 includes a voltage divider module 3 and a signal transmission module 4. The voltage divider module 3 dynamically adjusts the output signal amplitude through the formed voltage divider network. The change in resistance value directly changes the voltage at the voltage divider node, thereby flexibly controlling the amplitude of the high-level output. The signal transmission module 4 realizes signal switching and amplification based on the complementary switching characteristics of N-channel and P-channel MOSFETs. Through the coordinated operation of the fast switching of the MOSFETs and the voltage divider adjustment, the signal enhancement function is achieved.

[0032] like Figure 3 In this embodiment, the input terminal Vin of the constant voltage controller U1 is connected to the positive terminal of the external power supply and the positive terminal of the first capacitor C1. The output terminal is connected to the positive terminal of the second capacitor C2 and one end of the resistor R1 of the voltage divider module 3, with its ground terminal GND. The positive terminal of the first capacitor C1 is connected to the input terminal of U1, and the negative terminal of the first capacitor C1 is connected to the common ground GND. The positive terminal of the second capacitor C2 is connected to the output terminal of U1, and the negative terminal of the second capacitor C2 is connected to the common ground GND. The voltage divider module 3 includes a first resistor R1 and a second resistor R2. One end of the first resistor R1 is connected to the output terminal of U1, and the other end is connected to the voltage divider node and one end of the second resistor R2. The other end of the second resistor R2 is connected to the common ground. One end of the third resistor R3 is connected to the signal input terminal Signal. IN, the other end is connected to the gate of N-channel MOSFET Q1; the source of N-channel MOSFET Q1 is connected to common ground GND, the drain is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to the gate of P-channel MOSFET Q2; the two ends of the sixth resistor R6 are connected across the gate and source of N-channel MOSFET Q1, the gate of P-channel MOSFET Q2 is connected to the other end of the fifth resistor R5, the source is connected to the voltage divider node, the drain is connected to one end of the fourth resistor R4 and the signal output terminal Signal OUT, one end of the fourth resistor R4 is connected to the drain of P-channel MOSFET Q2, the other end is connected to common ground.

[0033] The implementation principle of a digital signal amplifier circuit in this application embodiment is as follows: The voltage regulator circuit 1 consists of a constant voltage controller U1, an input filter capacitor C1, and an output filter capacitor C2; the constant voltage controller U1 converts the input voltage into a stable output voltage through an internal reference voltage and feedback mechanism; the input filter capacitor C1 is connected in parallel to the input terminal of the constant voltage controller U1 to filter out high-frequency power supply noise, such as switching noise; the output filter capacitor C2 is connected in parallel to the output terminal of the constant voltage controller U1 to absorb low-frequency ripple and ensure voltage purity.

[0034] The voltage divider module 3 consists of a fixed resistor R1 and an adjustable resistor R2. By adjusting the resistance value of R2, the voltage at the voltage divider node is changed, thereby indirectly controlling the output high-level amplitude.

[0035] Signal transmission module 4 consists of an N-channel MOSFET Q1, a P-channel MOSFET Q2, and gate drive resistors R5 and R6. When the input signal IN is high (Signal IN = 1), the gate voltage of Q1 is pulled high, Q1 conducts, and the drain is grounded (≈0V). The gate of Q2 is pulled low through R5, Q2 conducts, and the source is connected to the voltage divider node, connecting to the drain. The output voltage is the voltage divider node voltage, and the signal output terminal Signal OUT is high. When the input signal IN is low (Signal IN = 0), Q1 is cut off, the drain is floating, the gate of Q2 is pulled high by the voltage divider R1 / R2, Q2 is cut off, and the output terminal is pulled down to 0V through R4. The signal output terminal Signal OUT is low. R3 limits the gate current of Q1 to prevent overvoltage damage, R5 suppresses the gate oscillation of Q2 and improves switching stability, and R6 provides a discharge circuit for the gate of Q1 to accelerate turn-off. When Q2 is on, the current path is a voltage divider node, with Q2, R4, GND, and the fourth resistor R4 providing current limiting protection; when Q2 is off, R4 forces the output terminal to 0V to prevent floating.

[0036] The above are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A digital signal amplifying circuit, characterized by comprising: include: A voltage regulator circuit (1) and a signal enhancement circuit (2) are provided. The input terminal of the voltage regulator circuit (1) is connected to the voltage input terminal to receive the start-up voltage. The output terminal of the voltage regulator circuit (1) is connected to the input terminal of the signal enhancement circuit (2) to provide a stable voltage reference and ensure that the operating voltage of the signal enhancement circuit (2) is stable. The voltage regulator circuit (1) and the signal enhancement circuit (2) share a common ground. The signal enhancement circuit (2) includes a signal input terminal, a voltage divider module (3), a signal transmission module (4), and a signal output terminal. The signal input terminal is connected to the signal transmission module (4) to input a high-frequency digital signal. The voltage divider module (3) is connected to the signal transmission module (4). The amplitude of the high-frequency digital signal is increased by adjusting the resistance value of the voltage divider module (3). The signal output terminal is connected to the signal transmission module (4) to output an amplified digital signal to the load.

2. A digital signal amplifying circuit according to claim 1, wherein The voltage regulator circuit (1) includes: a constant voltage controller, a first capacitor and a second capacitor. The input terminal of the constant voltage controller is connected to the voltage input terminal. One end of the first capacitor is connected to the input terminal of the constant voltage controller, and the other end of the first capacitor is grounded. The output terminal of the constant voltage controller is connected to the second capacitor, and the other end of the second capacitor is grounded. The constant voltage controller is grounded.

3. A digital signal amplifying circuit according to claim 2, wherein The voltage divider module (3) includes: a first resistor and a second resistor. The first resistor is connected to the output terminal of the constant voltage controller. The first resistor and the second resistor are connected in series. The second resistor is grounded. There is a voltage divider node between the first resistor and the second resistor.

4. A digital signal amplifying circuit according to claim 3, wherein The signal transmission module (4) includes an N-channel MOS transistor and a P-channel MOS transistor. The signal input terminal is connected to one end of a third resistor, and the other end of the third resistor is connected to the gate of the N-channel MOS transistor. A sixth resistor is connected in parallel between the gate and source of the N-channel MOS transistor. The source of the N-channel MOS transistor is grounded. The drain of the N-channel MOS transistor is connected to the gate of the P-channel MOS transistor. A fifth resistor is connected in parallel between the gate and source of the P-channel MOS transistor. The source of the P-channel MOS transistor is connected to the voltage divider node.

5. A digital signal amplifying circuit according to claim 4, wherein The drain of the P-channel MOSFET is connected in series with a fourth resistor, which is grounded. The drain of the P-channel MOSFET and the fourth resistor are connected to the signal output terminal.

6. A digital signal amplifying circuit according to claim 2, wherein The first capacitor is a small-capacity ceramic capacitor, and the second capacitor is a large-capacity electrolytic capacitor.

7. A digital signal amplifying circuit according to claim 3, wherein The first resistor is a fixed resistor, and the second resistor is an adjustable resistor.

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