Interlocking drive circuit of string type inverter and inverter

Abstract

A primary side of an upper bridge arm isolation optocoupler is connected with an upper bridge arm pulse width modulation signal generator and a lower bridge arm pulse width modulation signal generator, and a secondary side of the upper bridge arm isolation optocoupler is connected with an upper bridge arm secondary side driving power supply through an upper bridge arm push-pull amplifier. The upper bridge arm secondary side driving power supply is connected with the upper bridge arm secondary side filtering capacitor; the primary side of the lower bridge arm isolation optocoupler is connected with a lower bridge arm pulse width modulation signal generator and an upper bridge arm pulse width modulation signal generator, the secondary side of the lower bridge arm isolation optocoupler is connected with a lower bridge arm secondary side driving power supply through a lower bridge arm push-pull amplifier, and the lower bridge arm secondary side driving power supply is connected with a lower bridge arm secondary side filter capacitor; the upper bridge arm pulse width modulation signal generator and the lower bridge arm pulse width modulation signal generator are arranged in an interlocking manner; an upper bridge arm inductor is arranged between the upper bridge arm pulse width modulation signal generator and the upper bridge arm isolation optocoupler; and a lower bridge arm inductor is arranged between the lower bridge arm pulse width modulation signal generator and the lower bridge arm isolation optocoupler.

Description

Technical Field

[0001] This utility model belongs to the technical field of string inverters, specifically relating to an interlock drive circuit and an inverter for a string inverter. Background Technology

[0002] Considering low cost and configuration flexibility, string inverters used in large ground power plants often employ isolated optocouplers for their internal power stage IGBT (Insulated Gate Bipolar Transistor) drivers, supplemented by push-pull totem poles (or emitter followers) composed of external vertical transistors to enhance drive current capability and achieve fast switching control of IGBT devices.

[0003] In widely used optocouplers for drive circuits, the primary-side PWM (Pulse-Width Modulation) signal is mostly generated by a digital controller. After passing through a level conversion chip to amplify the amplitude signal, it is sent to the primary side of the optocoupler. Furthermore, the PWM drive signal typically shares a common GND (Ground). During the high-voltage, high-current hard-switching operation of string inverters, the change in the commutation path generates a complex electromagnetic field environment with high intensity and rich harmonic content. This field acts on the common reference GND plane of the optocoupler's primary-side drive signal through capacitive / inductive coupling or radio frequency interference, resulting in extremely high-amplitude common-mode "ground bounce" noise. The combined effect of this noise can cause switching devices that should be complementary in timing (e.g., half-bus bridge arm pairs in a three-level active midpoint clamp topology, forming complementary switching pairs) to be in a common state with simultaneously high drive levels. This directly leads to a shoot-through of the half-bus, causing a short circuit and potentially causing the inverter to fail.

[0004] In existing drive solutions, the primary-side signal of the optocoupler, relative to the analog signal reference plane (analog reference ground), exhibits extremely strong ground bounce noise on the GND network of the low-voltage control side (primary-side drive signal) under complex application scenarios such as high voltage (1500VDC on the DC side, 800VAC level for the inverter), high power (300+kW level), and hard switching (high di / dt and dv / dt due to commutation). Furthermore, the large area of ​​the traces makes it extremely easy to pick up electromagnetic field interference coupled from the power loop, resulting in a high content of common-mode signal noise in the PWM signal relative to GND. This reduces the signal-to-noise ratio of the primary-side signal to some extent and increases the risk of a half-bus short circuit caused by the simultaneous conduction of switches that should have complementary timing. Utility Model Content

[0005] The purpose of this invention is to overcome the problem that the timing of complementary switches in a string inverter topology cannot operate reliably, and to propose an interlock drive circuit and an inverter for a string inverter.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, this utility model provides an interlocked drive circuit for a string inverter, including an upper arm isolation optocoupler Opto1, an upper arm pulse width modulation signal generator PWM1, an upper arm secondary drive power supply, an upper arm secondary filter capacitor, a lower arm isolation optocoupler Opto2, a lower arm pulse width modulation signal generator PWM2, a lower arm secondary drive power supply, and a lower arm secondary filter capacitor.

[0008] The primary side of the upper bridge arm isolation optocoupler Opto1 is connected to the output terminal of the upper bridge arm pulse width modulation signal generator PWM1 and the output terminal of the lower bridge arm pulse width modulation signal generator PWM2. The secondary side of the upper bridge arm isolation optocoupler Opto1 is connected to the upper bridge arm drive power supply through the upper bridge arm push-pull amplifier. The upper bridge arm drive power supply is connected to the upper bridge arm secondary side filter capacitor.

[0009] The primary side of the lower bridge arm isolation optocoupler Opto2 is connected to the output terminal of the lower bridge arm pulse width modulation signal generator PWM2 and the output terminal of the upper bridge arm pulse width modulation signal generator PWM1. The secondary side of the lower bridge arm isolation optocoupler Opto2 is connected to the lower bridge arm secondary side drive power supply through the lower bridge arm push-pull amplifier. The lower bridge arm secondary side drive power supply is connected to the lower bridge arm secondary side filter capacitor.

[0010] The output terminal of the upper arm pulse width modulation signal generator PWM1 is interlocked with the output terminal of the lower arm pulse width modulation signal generator PWM2; an upper arm inductor L1 and a first current-limiting resistor R1 for the primary side signal of the upper arm isolation optocoupler Opto1 are provided between the output terminal of the upper arm pulse width modulation signal generator PWM1 and the upper arm isolation optocoupler Opto2; a lower arm inductor L2 and a third current-limiting resistor R3 for the primary side signal of the lower arm isolation optocoupler Opto2 are provided between the output terminal of the lower arm pulse width modulation signal generator PWM2 and the lower arm isolation optocoupler Opto2.

[0011] A second current-limiting resistor R2 is provided between the output terminals of the upper bridge arm isolation optocoupler Opto1 and the lower bridge arm pulse width modulation signal generator PWM2, and a fourth current-limiting resistor R4 is provided between the output terminals of the lower bridge arm isolation optocoupler Opto2 and the upper bridge arm pulse width modulation signal generator PWM1.

[0012] Furthermore, both the upper bridge arm inductor L1 and the lower bridge arm inductor L2 are made of ferrite beads.

[0013] Furthermore, the upper bridge arm pulse width modulation signal generator PWM1 is connected to one end of the upper bridge arm inductor L1 and one end of the fourth current limiting resistor R4 of the primary side signal of the lower bridge arm isolation optocoupler, respectively, and the other end of the upper bridge arm inductor L1 is connected to one end of the first current limiting resistor R1 of the primary side signal of the upper bridge arm isolation optocoupler.

[0014] Furthermore, the lower bridge arm pulse width modulation signal generator PWM2 is connected to one end of the lower bridge arm inductor L2 and one end of the second current limiting resistor R2 of the primary side signal of the upper bridge arm isolation optocoupler, respectively, and the other end of the lower bridge arm inductor L2 is connected to one end of the third current limiting resistor R3 of the primary side signal of the lower bridge arm isolation optocoupler.

[0015] Furthermore, the other end of the first current-limiting resistor R1 of the primary side signal of the upper bridge arm isolation optocoupler is connected to the other end of the second current-limiting resistor R2 of the primary side signal of the upper bridge arm isolation optocoupler through the primary side filter capacitor C1 of the upper bridge arm; the primary side filter capacitor C1 of the upper bridge arm is connected in parallel with the primary side of the upper bridge arm isolation optocoupler Opto1.

[0016] Furthermore, the other end of the third current-limiting resistor R3 of the primary side signal of the lower bridge arm isolation optocoupler is connected to the other end of the fourth current-limiting resistor R4 of the primary side signal of the lower bridge arm isolation optocoupler through the primary side filter capacitor C4 of the lower bridge arm; the primary side filter capacitor C4 of the lower bridge arm is connected in parallel with the primary side of the lower bridge arm isolation optocoupler Opto2.

[0017] Furthermore, the upper bridge arm push-pull amplifier includes an upper bridge arm isolation optocoupler secondary side NPN transistor Q1 and an upper bridge arm isolation optocoupler secondary side PNP transistor Q2;

[0018] The lower arm push-pull amplifier includes a lower arm isolation optocoupler secondary side NPN transistor Q3 and a lower arm isolation optocoupler secondary side PNP transistor Q4.

[0019] Furthermore, the upper bridge arm secondary side filter capacitor includes a second filter capacitor C2 and a third filter capacitor C3, which are disposed between the positive and negative terminals of the upper bridge arm drive power supply.

[0020] Furthermore, the lower bridge arm secondary side filter capacitor includes a fifth filter capacitor C5 and a sixth filter capacitor C6, which are disposed between the positive and negative terminals of the lower bridge arm drive power supply.

[0021] Secondly, this utility model provides an inverter that uses the interlock drive circuit of a string inverter described above.

[0022] Compared with the prior art, the present invention has the following beneficial technical effects:

[0023] This invention proposes an interlocked drive circuit for a string inverter. The dual interlocking mechanism of logic interlocking and timing interlocking ensures safe operation. The logic interlocking design of the PWM1 / PWM2 signal generators physically blocks the direct path between the upper and lower bridge arms, avoiding the short-circuit risk caused by simultaneous conduction of the switching transistors and reducing the bridge arm direct-path failure rate. The inductors L1 / L2 and the primary side of the optocoupler form a delay network timing interlock, generating a nanosecond-level dead time during signal switching to prevent false turn-on caused by reverse recovery of the body diode of the switching transistor. Compared to existing non-interlocked drive circuits, this invention's interlocked drive circuit scheme does not add any additional sub-components. It simply improves the PWM reference signal of the primary side of the optocoupler from the existing GND reference to two complementary PWM signals that reference each other and are coupled into a "quasi-differential" form. The implementation is simple and highly reliable. By coupling the PWM signals of the primary side of the optocoupler, which should be timing-complementary, into a "quasi-differential" form, it ensures that only when one signal is high and the other is low will the corresponding primary side of the optocoupler be forward biased and the PWM information transmitted from the primary side to the secondary side. Attached Figure Description

[0024] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of the present invention in any way. Furthermore, the shapes and proportions of the components in the drawings are merely schematic to aid in understanding the present invention and do not specifically limit the shapes and proportions of the components. In the drawings:

[0025] Figure 1 This invention relates to the ANPC circuit structure configuration of an interlock drive circuit for a string inverter.

[0026] Figure 2 This is a schematic diagram of an existing non-interlocked drive scheme implementation.

[0027] Figure 3 This is a schematic diagram of the interlock drive circuit of a string inverter according to the present invention.

[0028] Figure 4 This is a measured effect diagram of the interlock drive board under independent inverter operation of this utility model.

[0029] Figure 5 This is a measured effect diagram of the interlock drive board under grid-connected operating conditions with pure active power. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0031] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only embodiments.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0034] Example 1

[0035] See Figure 3 An interlock drive circuit for a string inverter includes an upper arm isolation optocoupler Opto1, an upper arm pulse width modulation signal generator PWM1, an upper arm secondary drive power supply, an upper arm secondary filter capacitor, a lower arm isolation optocoupler Opto2, a lower arm pulse width modulation signal generator PWM2, a lower arm secondary drive power supply, and a lower arm secondary filter capacitor.

[0036] The primary side of the upper bridge arm isolation optocoupler Opto1 is connected to the output terminal of the upper bridge arm pulse width modulation signal generator PWM1 and the output terminal of the lower bridge arm pulse width modulation signal generator PWM2. The secondary side of the upper bridge arm isolation optocoupler Opto1 is connected to the upper bridge arm drive power supply through the upper bridge arm push-pull amplifier. The upper bridge arm drive power supply is connected to the upper bridge arm secondary side filter capacitor.

[0037] The primary side of the lower bridge arm isolation optocoupler Opto2 is connected to the output of the lower bridge arm pulse width modulation signal generator PWM2 and the output of the upper bridge arm pulse width modulation signal generator PWM1. The secondary side of the lower bridge arm isolation optocoupler Opto2 is connected to the lower bridge arm secondary side drive power supply through the lower bridge arm push-pull amplifier. The lower bridge arm secondary side drive power supply is connected to the lower bridge arm secondary side filter capacitor.

[0038] The output of the upper arm pulse width modulation signal generator PWM1 is interlocked with the output of the lower arm pulse width modulation signal generator PWM2; an upper arm inductor L1 and a first current-limiting resistor R1 for the primary side signal of the upper arm isolation optocoupler Opto1 are set between the output of the upper arm pulse width modulation signal generator PWM1 and the upper arm isolation optocoupler Opto2; a lower arm inductor L2 and a third current-limiting resistor R3 for the primary side signal of the lower arm isolation optocoupler Opto2 are set between the output of the lower arm pulse width modulation signal generator PWM2 and the lower arm isolation optocoupler Opto2.

[0039] A second current-limiting resistor R2 is set between the output terminals of the upper bridge arm isolation optocoupler Opto1 and the lower bridge arm pulse width modulation signal generator PWM2, and a fourth current-limiting resistor R4 is set between the output terminals of the lower bridge arm isolation optocoupler Opto2 and the upper bridge arm pulse width modulation signal generator PWM1.

[0040] This invention uses a low-cost hardware solution to achieve reliable timing of complementary switching transistors in a string inverter topology, avoiding the problem of inverter failure caused by short circuits in the transistors due to ground bounce noise or strong EMI (Electromagnetic Interference) noise crosstalk, which could lead to a half-bus short circuit.

[0041] Both the upper arm inductor L1 and the lower arm inductor L2 use ferrite beads. The upper arm pulse width modulation (PWM) signal generator PWM1 is connected to one end of the upper arm inductor L1 and one end of the fourth current-limiting resistor R4 on the primary side of the lower arm isolation optocoupler. The other end of the upper arm inductor L1 is connected to one end of the first current-limiting resistor R1 on the primary side of the upper arm isolation optocoupler. The lower arm PWM signal generator PWM2 is connected to one end of the lower arm inductor L2 and one end of the second current-limiting resistor R2 on the primary side of the upper arm isolation optocoupler. The other end of the lower arm inductor L2 is connected to one end of the third current-limiting resistor R3 on the primary side of the lower arm isolation optocoupler.

[0042] The other end of the first current-limiting resistor R1 on the primary side of the upper bridge arm isolation optocoupler is connected to the other end of the second current-limiting resistor R2 on the primary side of the upper bridge arm isolation optocoupler through the primary-side filter capacitor C1; the primary-side filter capacitor C1 is connected in parallel with the primary side of the upper bridge arm isolation optocoupler Opto1. The other end of the third current-limiting resistor R3 on the primary side of the lower bridge arm isolation optocoupler is connected to the other end of the fourth current-limiting resistor R4 on the primary side of the lower bridge arm isolation optocoupler through the primary-side filter capacitor C4; the primary-side filter capacitor C4 is connected in parallel with the primary side of the lower bridge arm isolation optocoupler Opto2.

[0043] The upper bridge arm push-pull amplifier includes an upper bridge arm isolation optocoupler secondary side NPN transistor Q1 and an upper bridge arm isolation optocoupler secondary side PNP transistor Q2; the lower bridge arm push-pull amplifier includes a lower bridge arm isolation optocoupler secondary side NPN transistor Q3 and a lower bridge arm isolation optocoupler secondary side PNP transistor Q4.

[0044] The upper bridge arm secondary filter capacitors include a second filter capacitor C2 and a third filter capacitor C3, which are positioned between the positive and negative terminals of the upper bridge arm drive power supply; the lower bridge arm secondary filter capacitors include a fifth filter capacitor C5 and a sixth filter capacitor C6, which are positioned between the positive and negative terminals of the lower bridge arm drive power supply.

[0045] This embodiment significantly improves the inverter's operational stability and conversion efficiency under complex operating conditions through signal integrity design, electromagnetic compatibility processing, and thermal management optimization, making it particularly suitable for scenarios requiring high-reliability power conversion, such as photovoltaic power generation.

[0046] Example 2

[0047] This embodiment provides an inverter that uses the interlock drive circuit of a string inverter described in Embodiment 1.

[0048] Example 3

[0049] This invention proposes an interlocked drive circuit for string inverters. The interlocked drive scheme is applicable to topologies composed of "quasi-half-bridges" as sub-structural units, such as Active Neutral Point Clamped (ANPC) or I-Type Neutral Point Clamped (I-NPC). Its basic characteristic is that the upper and lower switches of the half-bridge structure are always complementary in conduction, and there is a certain dead time. The switching sequence should maintain the logic of "off first, then on". The ANPC circuit structure is used as an example for illustration:

[0050] like Figure 1 As shown, the A-phase inverter unit will be used as an example for explanation:

[0051] C1 / C2 are the positive and negative half-DC bus filter capacitors, respectively, to achieve power decoupling on the AC and DC sides and instantaneous energy buffering;

[0052] T1 / T5 and T4 / T6 are complementary switch pairs of "quasi-half-bridge" bridge arm structures for the positive and negative half-buses, respectively, and operate in high-frequency switching state;

[0053] T2 / T3 are power frequency commutation half-bridge arms, realizing energy commutation on the inverter side;

[0054] Lf and Cf form an LC low-pass filter unit to achieve current smoothing and pulsating energy buffering on the inverter side.

[0055] The interlocking drive scheme described in this utility model specifically refers to the interlocking of drive signals between pairs of T1 / T5, T4 / T6, and T2 / T3.

[0056] like Figure 2 The existing non-interlocked drive scheme implementation method shown is similar to Figure 3 This invention compares two implementation schemes of the interlock drive scheme.

[0057] Figure 2 The non-interlocked drive scheme mainly includes the following parts:

[0058] The primary side of the optocoupler consists of signal current limiting resistors R1~R4, filter capacitors C1 / C4, isolation optocouplers Opto1 / Opto2, a push-pull totem pole current amplifier stage formed by cascading NPN transistors Q1 / Q3 and PNP transistors Q2 / Q4 on the secondary side of the optocoupler, and filter capacitors C2 / C3 / C5 / C6 for driving positive and negative power supplies.

[0059] For non-interlocked drive schemes, the PWM signal on the primary side of the optocoupler is relative to the common reference ground plane GND of all PWM signals.

[0060] like Figure 3 As shown, the interlocked drive scheme adds two ferrite beads, L1 and L2, compared to the non-interlocked scheme. These are used to filter out high-frequency drive signal noise. Furthermore, the interlocked drive scheme couples the PWM drive signals of the two IGBT switching devices, which should have been time-complementary "quasi-half-bridge" configurations, into a "quasi-differential" form. Only when there is a potential difference between the two signals will one of the optocouplers activate. This fundamentally reduces the risk of the two PWM signals being simultaneously high due to erroneous high-level output from the MCU (Microcontroller Unit) or ground bounce noise interference, causing the switching transistors to shoot through.

[0061] Specifically, under the two driving schemes, the primary-side input PWM signal and the secondary-side output drive V GEThe truth table correspondences between signals are shown in Tables 1 and 2 below:

[0062] Table 1. Truth Table of Existing Non-Interlocked Driver Board Outputs

[0063]

[0064] Table 2. Output Truth Table of the Interlock Drive Board of this Utility Model

[0065]

[0066] As can be seen from the comparison of the truth tables of the two driving schemes above, the interlocked driving scheme of this utility model changes the input / output logic correspondence of the existing non-interlocked driving scheme. The interlocked driving board can avoid the phenomenon that the two driving signals on the primary side of the optocoupler may be high at the same time due to the high noise picked up by the transmission link, which may cause the secondary side to respond at the same time and cause the half-bridge arm to shoot through.

[0067] The advantages of this solution are illustrated by the practical application test results of the interlock drive solution:

[0068] Ch1 Channel 1: Primary side drive PWM1 signal (relative to GND) of inverter A-phase T1 transistor, 10V / div;

[0069] Ch2 Channel 2: Primary side drive PWM2 signal (relative to GND) of inverter phase A T5 transistor, 10V / div;

[0070] Math1 Channel M1: Mathematical subtraction operation between Channel 1 and Channel 2 (PWM1-PWM2), 10V / div;

[0071] Ch3 Channel 3: A-phase inverter T1 and T5 drive differential signals (PWM1-PWM2), 10V / div;

[0072] Ch4 Channel 4: Secondary drive signal of A-phase inverter T1 transistor (V GE1 ), 10V / div;

[0073] Ch5 Channel 5: A-phase inverter T5 tube secondary drive signal (V GE2 ), 10V / div;

[0074] Channel 7 (Ch7): A-phase inverter inductor current waveform (i) L-A ), 200, 500A / div;

[0075] Figure 4 The maximum power point voltage Vmp = 950V, and the fill factor FF = 0.8; Figure 5The maximum power point voltage Vmp = 950V, fill factor FF = 0.8, and rated power is 300kW; based on the above theoretical analysis and... Figure 4 , Figure 5 The measured waveforms show that Channel 1 and Channel 2 are the primary-side drive signals of the optocouplers relative to the GND reference for ANPC complementary switch T1 and ANPC complementary switch T5, respectively. It is easy to see that they exhibit relatively rich ground bounce glitch common-mode noise.

[0076] Compared to channels M1 and 3, the differential signals T1 and T5, which are obtained through mathematical calculations or direct measurements, show that their common-mode noise content is greatly reduced, significantly improving the signal-to-noise ratio of the primary-side driving signals.

[0077] Compared with existing non-interlocked drive schemes, the interlocked drive scheme of this utility model can greatly optimize the signal-to-noise ratio of the drive signal and reduce the serious failure of the inverter that may be caused by the MCU's mis-transmitted waves or excessive ground bounce noise amplitude leading to the shoot-through short circuit of the IGBT pair in the half-bridge configuration.

[0078] The solution presented in this utility model requires relatively little hardware modification compared to existing technical solutions and has the lowest implementation difficulty. Possible variations include, but are not limited to: interlocking solutions implemented in the form of logic gate circuits; and solutions based on other dedicated drivers (integrating active clamping, short-circuit protection, and other functions).

[0079] Many embodiments and applications beyond the provided examples will be apparent to those skilled in the art upon reading the foregoing description. Therefore, the scope of this teaching should not be determined by reference to the foregoing description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including disclosures of utility model applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed utility model subject matter.

[0080] The above content provides a further detailed description of this utility model. It should not be considered that the specific embodiments of this utility model are limited to this. For those skilled in the art, several simple deductions or substitutions can be made without departing from the concept of this utility model, and all of these should be considered to fall within the defined protection scope of this utility model.

Claims

1. An interlock drive circuit for a string inverter, characterized in that, It includes an upper bridge arm isolation optocoupler Opto1, an upper bridge arm pulse width modulation signal generator PWM1, an upper bridge arm secondary drive power supply, an upper bridge arm secondary filter capacitor, a lower bridge arm isolation optocoupler Opto2, a lower bridge arm pulse width modulation signal generator PWM2, a lower bridge arm secondary drive power supply, and a lower bridge arm secondary filter capacitor. The primary side of the upper bridge arm isolation optocoupler Opto1 is connected to the output terminal of the upper bridge arm pulse width modulation signal generator PWM1 and the output terminal of the lower bridge arm pulse width modulation signal generator PWM2. The secondary side of the upper bridge arm isolation optocoupler Opto1 is connected to the upper bridge arm secondary side drive power supply through the upper bridge arm push-pull amplifier. The upper bridge arm secondary side drive power supply is connected to the upper bridge arm secondary side filter capacitor. The primary side of the lower bridge arm isolation optocoupler Opto2 is connected to the output terminal of the lower bridge arm pulse width modulation signal generator PWM2 and the output terminal of the upper bridge arm pulse width modulation signal generator PWM1. The secondary side of the lower bridge arm isolation optocoupler Opto2 is connected to the lower bridge arm secondary side drive power supply through the lower bridge arm push-pull amplifier. The lower bridge arm secondary side drive power supply is connected to the lower bridge arm secondary side filter capacitor. The output terminal of the upper arm pulse width modulation signal generator PWM1 is interlocked with the output terminal of the lower arm pulse width modulation signal generator PWM2; an upper arm inductor L1 and a first current-limiting resistor R1 for the primary side signal of the upper arm isolation optocoupler Opto1 are provided between the output terminal of the upper arm pulse width modulation signal generator PWM1 and the upper arm isolation optocoupler Opto2; a lower arm inductor L2 and a third current-limiting resistor R3 for the primary side signal of the lower arm isolation optocoupler Opto2 are provided between the output terminal of the lower arm pulse width modulation signal generator PWM2 and the lower arm isolation optocoupler Opto2. A second current-limiting resistor R2 is provided between the output terminals of the upper bridge arm isolation optocoupler Opto1 and the lower bridge arm pulse width modulation signal generator PWM2, and a fourth current-limiting resistor R4 is provided between the output terminals of the lower bridge arm isolation optocoupler Opto2 and the upper bridge arm pulse width modulation signal generator PWM1.

2. The interlock drive circuit for a string inverter according to claim 1, characterized in that, Both the upper bridge arm inductor L1 and the lower bridge arm inductor L2 are made of ferrite beads.

3. The interlock drive circuit for a string inverter according to claim 1, characterized in that, The upper arm pulse width modulation signal generator PWM1 is connected to one end of the upper arm inductor L1 and one end of the fourth current limiting resistor R4 of the primary side signal of the lower arm isolation optocoupler. The other end of the upper arm inductor L1 is connected to one end of the first current limiting resistor R1 of the primary side signal of the upper arm isolation optocoupler.

4. The interlock drive circuit for a string inverter according to claim 1, characterized in that, The lower arm pulse width modulation signal generator PWM2 is connected to one end of the lower arm inductor L2 and one end of the second current limiting resistor R2 of the primary side signal of the upper arm isolation optocoupler. The other end of the lower arm inductor L2 is connected to one end of the third current limiting resistor R3 of the primary side signal of the lower arm isolation optocoupler.

5. The interlock drive circuit for a string inverter according to claim 1, characterized in that, The other end of the first current-limiting resistor R1 of the primary side signal of the upper bridge arm isolation optocoupler is connected to the other end of the second current-limiting resistor R2 of the primary side signal of the upper bridge arm isolation optocoupler through the primary side filter capacitor C1 of the upper bridge arm; the primary side filter capacitor C1 of the upper bridge arm is connected in parallel with the primary side of the upper bridge arm isolation optocoupler Opto1.

6. The interlock drive circuit for a string inverter according to claim 1, characterized in that, The other end of the third current-limiting resistor R3 of the primary side signal of the lower bridge arm isolation optocoupler is connected to the other end of the fourth current-limiting resistor R4 of the primary side signal of the lower bridge arm isolation optocoupler through the primary side filter capacitor C4 of the lower bridge arm; the primary side filter capacitor C4 of the lower bridge arm is connected in parallel with the primary side of the lower bridge arm isolation optocoupler Opto2.

7. The interlock drive circuit for a string inverter according to claim 1, characterized in that, The upper bridge arm push-pull amplifier includes an upper bridge arm isolation optocoupler secondary side NPN transistor Q1 and an upper bridge arm isolation optocoupler secondary side PNP transistor Q2; The lower arm push-pull amplifier includes a lower arm isolation optocoupler secondary side NPN transistor Q3 and a lower arm isolation optocoupler secondary side PNP transistor Q4.

8. The interlock drive circuit for a string inverter according to claim 1, characterized in that, The upper bridge arm secondary side filter capacitor includes a second filter capacitor C2 and a third filter capacitor C3, which are disposed between the positive and negative terminals of the upper bridge arm drive power supply.

9. The interlock drive circuit for a string inverter according to claim 1, characterized in that, The lower bridge arm secondary side filter capacitor includes a fifth filter capacitor C5 and a sixth filter capacitor C6, which are disposed between the positive and negative terminals of the lower bridge arm drive power supply.

10. An inverter, characterized in that, The interlock drive circuit of a string inverter as described in any one of claims 1-9 is used.

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