Low-power pulse transformer simulation circuit

Abstract

The utility model provides a small-power pulse transformer simulation circuit which comprises a square wave power source, the output end of the square wave power source is connected to the input end of a pi-type equivalent circuit through a blocking capacitor C1, and the pi-type equivalent circuit is connected with a resistive load Rload through a field effect transistor JFET driving amplification circuit; the output end of a square wave power supply is connected with a pi-type equivalent circuit of a low-power pulse transformer, the output end of the equivalent circuit of the low-power pulse transformer is connected with an MOS tube driving amplification circuit, and finally, a load is connected to the output end of the amplification circuit. The simulation circuit model is simple, effective and short in simulation time, and can be flexibly applied to application circuits of various transformers.

Description

Technical Field

[0001] This utility model relates to a simulation circuit for a low-power pulse transformer. Background Technology

[0002] Existing low-power pulse transformers are designed using theoretical calculations, often requiring multiple schemes for verification and debugging. The most ideal scheme is selected based on actual output results, or a 3D model of the transformer is built using electromagnetic field principles for structural and electromagnetic field simulation. However, due to the inaccurate calculation of waveform parameters, ideal theoretical calculation results are not obtained. Problems frequently arise during the design process where waveform parameters such as rise / fall times and overshoot / dropout cannot be accurately calculated. Furthermore, the load connected to the transformer varies in different application circuits, significantly complicating theoretical calculations. This results in poor matching between the designed transformer and the actual application circuit, meaning it does not operate at its optimal state in actual operation. While the method of building a 3D transformer model using electromagnetic field principles is suitable for simulating high-power transformers with significant heat generation, the modeling is very difficult. Moreover, the model built using electromagnetic field principles consumes enormous system resources, making it difficult to integrate into larger system-level simulations within the application circuit, thus limiting its practicality. Utility Model Content

[0003] To solve the above-mentioned technical problems, this utility model provides a low-power pulse transformer simulation circuit.

[0004] This utility model is achieved through the following technical solution.

[0005] This utility model provides a low-power pulse transformer simulation circuit, including a square wave power source, whose output terminal is connected to the input terminal of a π-type equivalent circuit through a DC blocking capacitor C1. The π-type equivalent circuit is connected to a resistive load Rload through a field-effect transistor JFET driving amplifier circuit.

[0006] The π-type equivalent circuit includes an ideal transformer T. The primary input terminal of the ideal transformer T is connected to one end of the primary leakage inductance Llp. The other end of the primary leakage inductance Llp is connected in series with a DC blocking capacitor C1, and then connected in series with a primary loss resistor Rp and a primary interlayer capacitor Cdp before being grounded.

[0007] The secondary output terminal of an ideal transformer T is connected in series with the secondary leakage inductance Lls, the secondary loss resistor Rs, and the secondary interlayer capacitance Cds before being grounded.

[0008] The field-effect transistor (JFET) drive amplifier circuit includes a field-effect transistor (JFET). The gate of the JFET is connected to the secondary leakage inductance Lls through a secondary loss resistor Rs and grounded through a pull-down resistor R1. The source of the JFET is connected to a DC voltage source Vcc through a current-limiting resistor R2, and the drain is grounded through a parallel current-limiting resistor R3 and a bypass capacitor C3.

[0009] One end of the resistive load Rload is connected to the source of the field-effect transistor JFET through capacitor C4, and the other end is grounded.

[0010] The secondary output terminal of the ideal transformer T is also connected in parallel with the secondary interlayer capacitance Cds.

[0011] The primary input terminal of the ideal transformer T is also connected in parallel with a magnetic loss resistor Rc and a magnetizing inductance Lp.

[0012] The beneficial effects of this utility model are as follows: a π-type equivalent circuit of a small-power pulse transformer is connected to the output terminal of the square wave power supply, a MOS transistor drive amplifier circuit is connected to the output terminal of the small-power pulse transformer equivalent circuit, and finally a load is connected to the output terminal of the amplifier circuit; this makes the simulation circuit model simple and effective, the simulation time short, and it can be flexibly applied to various transformer application circuits. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the circuit principle of this utility model. Detailed Implementation

[0014] The technical solution of this utility model is further described below, but the scope of protection is not limited to what is described.

[0015] This invention provides a low-power pulse transformer simulation circuit. An adjustable square wave waveform is established using a mathematical model, and then converted into a dimensional square wave analog signal using a digital-to-analog converter. This signal is input to the control terminal of a controlled voltage source, forming a power-type square wave power supply with constant and adjustable current / voltage. A π-type equivalent circuit of a low-power pulse transformer is connected to the output terminal of the square wave power supply. A MOS transistor drive amplifier circuit is connected to the output terminal of the equivalent circuit of the low-power pulse transformer. Finally, a load is connected to the output terminal of the amplifier circuit.

[0016] The specific simulation circuit includes a square wave power source, whose output is connected to the input of a π-type equivalent circuit through a DC blocking capacitor C1. The π-type equivalent circuit is connected to a resistive load Rload through a field-effect transistor (JFET) driving amplifier circuit.

[0017] The π-type equivalent circuit includes an ideal transformer T. The primary input terminal of the ideal transformer T is connected to one end of the primary leakage inductance Llp. The other end of the primary leakage inductance Llp is connected in series with a DC blocking capacitor C1, and then connected in series with a primary loss resistor Rp and a primary interlayer capacitor Cdp before being grounded.

[0018] The secondary output terminal of an ideal transformer T is connected in series with the secondary leakage inductance Lls, the secondary loss resistor Rs, and the secondary interlayer capacitance Cds before being grounded.

[0019] The field-effect transistor (JFET) drive amplifier circuit includes a field-effect transistor (JFET). The gate of the JFET is connected to the secondary leakage inductance Lls through a secondary loss resistor Rs and grounded through a pull-down resistor R1. The source of the JFET is connected to a DC voltage source Vcc through a current-limiting resistor R2, and the drain is grounded through a parallel current-limiting resistor R3 and a bypass capacitor C3.

[0020] One end of the resistive load Rload is connected to the source of the field-effect transistor JFET through capacitor C4, and the other end is grounded.

[0021] The secondary output terminal of the ideal transformer T is also connected in parallel with the secondary interlayer capacitance Cds.

[0022] The primary input terminal of the ideal transformer T is also connected in parallel with a magnetic loss resistor Rc and a magnetizing inductance Lp.

[0023] like Figure 1 As shown, a simulation circuit of a small-power pulse transformer includes a source square wave power supply, which generates a square wave of constant amplitude to provide power to the circuit; capacitor C1 to isolate the DC component of the power supply; Cdp, the interlayer capacitance between the primary windings of the transformer; Cds, the interlayer capacitance between the secondary windings of the transformer; Rp, the primary loss resistor; Rs, the secondary loss resistor; Llp and Lls, the leakage inductance generated on the primary and secondary windings respectively; Lp, the primary magnetizing inductance; Rc, the resistance generated by magnetic loss; and T, the ideal transformer. Together, they constitute the π-type equivalent circuit of the small-power pulse transformer, playing the role of isolation drive. The secondary winding of the equivalent transformer is connected to a JFET switching amplifier circuit. When the equivalent transformer outputs a low level, the JFET is cut off, and the voltage across the load resistor is 0V. When the equivalent transformer outputs a high level, the JFET is turned on, and the voltage across the load resistor is Vcc*R3 / R2+R3.

[0024] By setting parameters such as transformer interlayer capacitance, loss resistance, and leakage inductance turns ratio, and waveform parameters at position V1, the transformer can be better matched with the JFET amplifier circuit, achieving the goal of rapid transformer parameter design. Simultaneously, it can be integrated into circuits of different applications for system simulation.

Claims

1. A low-power pulse transformer simulation circuit, characterized in that: The circuit includes a square wave power source, whose output is connected to the input of a π-type equivalent circuit via a DC blocking capacitor C1. The π-type equivalent circuit is connected to a resistive load Rload via a field-effect transistor (JFET) driving amplifier circuit. The π-type equivalent circuit includes an ideal transformer T. The primary input terminal of the ideal transformer T is connected to one end of the primary leakage inductance Llp. The other end of the primary leakage inductance Llp is connected in series with a DC blocking capacitor C1, and then connected in series with a primary loss resistor Rp and a primary interlayer capacitor Cdp before being grounded. The secondary output terminal of an ideal transformer T is connected in series with the secondary leakage inductance Lls, the secondary loss resistor Rs, and the secondary interlayer capacitance Cds before being grounded.

2. The low-power pulse transformer simulation circuit as described in claim 1, characterized in that: The field-effect transistor (JFET) drive amplifier circuit includes a field-effect transistor (JFET). The gate of the JFET is connected to the secondary leakage inductance Lls through a secondary loss resistor Rs and grounded through a pull-down resistor R1. The source of the JFET is connected to a DC voltage source Vcc through a current-limiting resistor R2, and the drain is grounded through a parallel current-limiting resistor R3 and a bypass capacitor C3.

3. The low-power pulse transformer simulation circuit as described in claim 1, characterized in that: One end of the resistive load Rload is connected to the source of the field-effect transistor JFET through capacitor C4, and the other end is grounded.

4. The low-power pulse transformer simulation circuit as described in claim 1, characterized in that: The secondary output terminal of the ideal transformer T is also connected in parallel with the secondary interlayer capacitance Cds.

5. The low-power pulse transformer simulation circuit as described in claim 1, characterized in that: The primary input terminal of the ideal transformer T is also connected in parallel with a magnetic loss resistor Rc and a magnetizing inductance Lp.

Images