Non-doped non-capacitance dynamic random access memory
By using a doped and capacitor-free dynamic random access memory structure, and leveraging a heterogeneous gate structure and improved manufacturing process, the problem of low sensing margin and hold time in 1T-DRAM was solved, achieving higher sensing margin and hold time, while reducing static power consumption and process complexity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- LANZHOU JIAOTONG UNIV
- Filing Date
- 2025-05-14
- Publication Date
- 2026-04-28
AI Technical Summary
Existing 1T-DRAM based on multi-source heterogate structures has low sensing margin and hold time, and suffers from doping fluctuations and high process complexity during manufacturing.
The structure employs an undoped and capacitor-free dynamic random access memory (DRAM) structure, including a silicon substrate, a storage window, an N-type window, electrodes, and a gate electrode. The electric field strength is enhanced by utilizing a heterogeneous gate structure, and the material properties are improved through molecular beam epitaxy and rapid thermal annealing. A dual-source drain electrode and a dielectric layer are used to achieve a uniform hole distribution.
It improves sensing margin and hold time, enhances memory performance, and reduces static power consumption and process complexity.
Smart Images
Figure CN224178515U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to an undoped and capacitor-free dynamic random access memory. Background Technology
[0002] Traditional Dynamic Random Access Memory (DRAM) consists of a transistor and a capacitor (1T1C). Its read mechanism involves charging the bit lines using the capacitor. However, as device size continues to shrink, electromagnetic interference easily occurs between adjacent cells, leading to electromagnetic coupling effects and information loss during data retrieval. To address these issues and improve the integration density of DRAM, capacitor-free DRAM (1T-DRAM) design has attracted significant research attention. Current 1T-DRAM in the industry typically uses metal-oxide-semiconductor field-effect transistors (MOSFETs) to store charge.
[0003] However, MOSFETs have high off-state leakage current, resulting in significant static power consumption in 1T DRAM based on them. Furthermore, with increasing chip integration, the feature size of MOSFETs is approaching its physical limits. To continue Moore's Law, research into new structures, materials, or principles of devices is urgently needed. Tunneling field-effect transistors (TFETs), based on a band-to-band tunneling mechanism, have lower off-state current (…). I off ) and subthreshold swing ( SS avg This can effectively solve the related problems faced by MOSFETs, among which, low I off It can reduce the read "0" current of 1T-DRAM ( I R0 ( ) and static power consumption. Therefore, 1T-DRAM based on TFET has attracted attention. However, due to the inherent material properties of Si, the low on-state current ( I on The low cost of silicon-based TFETs is a major constraint on their development. I on It will affect the sensing margin (SM) of 1T-DRAM.
[0004] To overcome this problem, researchers have proposed a novel method with N + 1T-DRAM with doped layer structure can greatly improve the SM and hold time (RT) of the device because the N-type window can adjust the energy band at the tunnel junction, thereby reducing the lateral tunneling distance and enhancing the lateral electric field at the tunnel junction.
[0005] However, when manufacturing such 1T-DRAM devices, the source region, drain region, and N-type window need to be implanted with ions. As the feature size of such devices shrinks, random doping fluctuations will occur, a high thermal budget will be required, and it will be difficult to form steep junctions in the source / channel region and drain / channel region, which will cause degradation of device characteristics.
[0006] Existing technology employs a 1T-DRAM based on a planar dual-gate TFET. Gate electrode 1 uses band-to-band tunneling to regulate the read mechanism, while gate electrode 2 creates and maintains a window for storage near the drain region. It achieves a response time (RT) greater than 1.5 seconds at 85°C, but suffers from low latency. I on This results in an SM with a current of only 140 nA and a total gate length of 750 nm, far exceeding the current nanometer-scale TFET size. Furthermore, doping can lead to random doping fluctuations and high thermal budgets during manufacturing. Another type of undoped 1T-DRAM, based on charge plasma, employs an misaligned dual-gate architecture, allowing for the formation of P-type MOSFETs without doping. + Source region and N + The drain region avoids many problems such as the high-temperature annealing process required after ion implantation, which is used to improve the tunneling rate (SM) and reduce process complexity. However, the SM of this structure still cannot reach the μA level, and the read current ratio (RT) cannot reach the second level. A 1T-DRAM based on a multi-source heterogate structure uses four Ge-pockets to improve the tunneling rate, thereby improving SM and RT. However, this method increases process complexity, and its read current ratio (...) I R1 / I R0 The ratio is only 4.4, which is not on the order of magnitude. Utility Model Content
[0007] This invention provides an undoped and capacitor-free dynamic random access memory (DRAM) to solve the technical problem of low sensing margin and hold time in existing 1T-DRAM based on multi-source heterogeneous gate structures, which is difficult to improve. It achieves the goal of improving the sensing margin and hold time of the undoped and capacitor-free DRAM and improving storage performance.
[0008] This utility model provides an undoped, capacitor-free dynamic random access memory, comprising:
[0009] A silicon substrate, with a first U-shaped groove and a second U-shaped groove symmetrically formed on the left and right edge regions;
[0010] A storage window is embedded on the surface of the silicon substrate, and the storage window is close to the second U-shaped groove;
[0011] An N-type window is embedded on the surface of the silicon substrate where the memory window is located. The N-type window is close to the first U-shaped groove, and an intrinsic channel region is provided between the N-type window and the memory window.
[0012] The electrode includes a source and a drain. The source is disposed in the first U-shaped groove, the drain is disposed in the second U-shaped groove, a drain region is disposed between the drain and the storage window, and a source region is disposed between the source and the N-type window.
[0013] A gate electrode is embedded at the upper and lower edges of the silicon substrate, and the electrode is electrically connected to the gate electrode;
[0014] The dielectric layer covers the locations where the N-type window, electrodes, source region, and gate electrode are disposed.
[0015] According to the present invention, an undoped and capacitor-free dynamic random access memory is provided, wherein the storage window is disposed on the right side of the intrinsic channel region, the space between the storage window and the drain is the drain region, the N-type window is disposed on the left side of the intrinsic channel region, and the space between the N-type window and the source is the source region.
[0016] According to the present invention, a doped and capacitor-free dynamic random access memory is provided, wherein the drain is a metal hafnium, the source is a metal platinum, the vertical length of the drain and the source are matched with the width of the silicon substrate, and there is a gap between the drain and the source and the gate electrode.
[0017] According to the present invention, a doped and capacitor-free dynamic random access memory (DRAM) is provided, wherein the dielectric layer includes a first dielectric layer and a second dielectric layer, and the gate electrode includes a first gate electrode, a second gate electrode, and a third gate electrode. The first dielectric layer covers the source and the source region, the second dielectric layer covers the N-type window and the first gate electrode, the first dielectric layer covers the second gate electrode and one side of the memory window, the second dielectric layer covers the third gate electrode, and the first dielectric layer covers the drain region and the drain electrode. Two of each of the first and second gate electrodes are provided. The first gate electrode is disposed at both ends of the second dielectric layer on both sides of the N-type window, and the second gate electrode is disposed to the right of the first gate electrode. The length of the first gate electrode is less than that of the second gate electrode, and the length of the first gate electrode is less than the length of the second dielectric layer near the N-type window but greater than half the length of the second dielectric layer. The length of the first gate electrode is equal to the length of the N-type window. The third gate electrode is disposed at the upper end of the second dielectric layer near the memory window. There is a gap between the source and the first gate electrode, a gap between the second gate electrode and the third gate electrode, and a gap between the third gate electrode and the drain electrode.
[0018] According to the present invention, an undoped and capacitor-free dynamic random access memory is provided, wherein the first dielectric layer is silicon dioxide, the second dielectric layer is hafnium dioxide, the first gate electrode is zinc, the second gate electrode is gallium, and the third gate electrode is copper.
[0019] According to the present invention, an undoped and capacitor-free dynamic random access memory is provided, wherein the intrinsic channel region, source region and drain region are made of silicon, the storage window is made of SiGe, and the thickness of the first dielectric layer and the second dielectric layer is 1 to 3 nm.
[0020] The beneficial effects of this utility model are:
[0021] This invention provides an undoped, capacitor-free dynamic random access memory (DRAM) with a dual-source-drain electrode, resulting in a more uniform hole distribution in the source region. A second dielectric layer is employed under the gate electrode to enhance the electric field strength in the source / intrinsic channel region and the memory window / drain region, thereby providing higher sensing margin and hold time. Changing the gate electrode to a heterogeneous gate structure induces an N-type window in the underlying channel, reducing the lateral tunneling distance at the source / channel tunneling junction and enhancing the electron tunneling rate, thus leading to higher sensing margin. This invention solves the technical problem of low sensing margin and hold time in existing 1T-DRAMs based on multi-source heterogeneous gate structures, which is difficult to improve, achieving the goal of improving the sensing margin and hold time of undoped, capacitor-free DRAM and enhancing memory performance.
[0022] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0024] Figure 1 This is a schematic diagram of a doped, capacitor-free dynamic random access memory.
[0025] Figure label:
[0026] 1. Storage window; 2. N-type window; 3. Electrode; 301. Source; 302. Drain; 4. Source region; 5. Drain region; 6. Gate electrode; 601. First gate electrode; 602. Second gate electrode; 603. Third gate electrode; 7. Dielectric layer; 701. First dielectric layer; 702. Second dielectric layer; 8. Intrinsic channel region. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0028] In the description of the embodiments of this utility model, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this utility model and simplifying the description, and do not indicate or imply that the mechanism or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this utility model. In addition, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0029] In the description of the embodiments of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this utility model based on the specific circumstances.
[0030] In this embodiment of the utility model, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0031] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0032] The following is combined with Figure 1 The embodiments shown illustrate the technical solution of this utility model:
[0033] This invention provides an undoped, capacitor-free dynamic random access memory (DRAM), comprising: a silicon substrate, wherein a first U-shaped groove and a second U-shaped groove are symmetrically formed on the left and right edges of the silicon substrate; a storage window 1, embedded on the surface of the silicon substrate, the storage window 1 being close to the second U-shaped groove; an N-type window 2, embedded on the surface of the silicon substrate where the storage window 1 is provided, the N-type window 2 being close to the first U-shaped groove, and an intrinsic channel region 8 being provided between the N-type window 2 and the storage window 1; an electrode 3, including a source electrode 301 and a drain electrode 302, the source electrode 301 being disposed in the first U-shaped groove, the drain electrode 302 being disposed in the second U-shaped groove, a drain region 5 being provided between the drain electrode 302 and the storage window 1, and a source region 4 being provided between the source electrode 301 and the N-type window 2; a gate electrode 6, embedded at the upper and lower edges of the silicon substrate, the electrode 3 and the gate electrode 6 being electrically connected; and a dielectric layer 7, covering the positions where the N-type window 2, the electrode 3, the source region 4 and the gate electrode 6 are provided.
[0034] It is understood that the present invention provides an undoped and capacitor-free dynamic random access memory (DRAM), which has dual source and drain electrodes 3, thereby making the hole distribution in the source region 4 more uniform; and a second dielectric layer 702 is used under the gate electrode 6 to enhance the electric field strength between the source region 4 and the intrinsic channel region 8 and between the storage window 1 and the drain region 5, thereby giving the present invention higher sensing margin and retention time.
[0035] In this invention, the silicon substrate consists of a silicon wafer and a silicon-on-insulator (SOI) wafer bonded together by plasma-assisted bonding. Annealing the bonded silicon wafer before use can improve the bonding strength. The TiN adhesion layer bonds the source electrode 301 and the first dielectric layer 701, which helps to improve the interfacial bonding force, effectively blocks direct leakage current channels, and prevents electrical contact failure.
[0036] To effectively reduce the formation of relaxation layers and lattice defects, a gradient SiGe storage window 1 buffer layer can be grown using molecular beam epitaxy, specific impurity atoms can be injected, and then rapid thermal annealing can be performed. During the growth of the SiGe layer, the formation of relaxation layers can be monitored in real time using high-energy electron diffraction. The gate electrode 6 is the gate metal electrode.
[0037] According to the present invention, a doped and capacitor-free dynamic random access memory is provided, wherein the storage window 1 is located on the right side of the intrinsic channel region 8, the storage window 1 and the drain 302 are located as the drain region 5, the N-type window 2 is located on the left side of the intrinsic channel region 8, and the N-type window 2 and the source 301 are located as the source region 4.
[0038] According to the present invention, a doped and capacitor-free dynamic random access memory is provided, wherein the drain 302 is made of hafnium metal and the source 301 is made of platinum metal. The vertical lengths of the drain 302 and the source 301 are matched with the width of the silicon substrate, and there is a gap between the drain 302 and the source 301 and the gate electrode 6.
[0039] According to the present invention, a doped and capacitor-free dynamic random access memory (DRAM) is provided, wherein the dielectric layer 7 includes a first dielectric layer 701 and a second dielectric layer 702, the gate electrode 6 includes a first gate electrode 601, a second gate electrode 602 and a third gate electrode 603, the first dielectric layer 701 covers the source electrode 301 and the source region 4, the second dielectric layer 702 covers the N-type window 2 and the first gate electrode 601, the first dielectric layer 701 covers the second gate electrode 602 and one side of the memory window 1, the second dielectric layer 702 covers the third gate electrode 603, the first dielectric layer 701 covers the drain region 5 and the drain electrode 302, and two of each of the first gate electrode 601 and the second gate electrode 602 are provided, the first gate electrode 601 being disposed in the N-type window 4. At both ends of the second dielectric layer 702 on both sides of window 2, the second gate electrode 602 is disposed to the right of the first gate electrode 601. The length of the first gate electrode 601 is less than that of the second gate electrode 602. The length of the first gate electrode 601 is less than the length of the second dielectric layer 702 near the N-type window 2, but greater than half the length of the second dielectric layer 702. The length of the first gate electrode 601 is equal to the length of the N-type window 2. The third gate electrode 603 is disposed at the upper end of the second dielectric layer 702 near the storage window 1. There is a gap between the source electrode 301 and the first gate electrode 601, a gap between the second gate electrode 602 and the third gate electrode 603, and a gap between the third gate electrode 603 and the drain electrode 302.
[0040] According to the present invention, an undoped and capacitor-free dynamic random access memory is provided, wherein the first dielectric layer 701 is silicon dioxide, the second dielectric layer 702 is hafnium dioxide, the first gate electrode 601 is zinc, the second gate electrode 602 is gallium, and the third gate electrode 603 is copper.
[0041] This invention employs hafnium dioxide (HfO2) dielectric material under the gate electrode 3 to enhance the electric field strength between the source / channel and between the SiGe memory window 1 / drain region 5, thereby enabling the invention to achieve higher SM and RT.
[0042] According to the present invention, the intrinsic channel region 8, source region 4 and drain region 5 are made of silicon, the storage window 1 is made of SiGe, and the thickness of the first dielectric layer 701 and the second dielectric layer 702 is 1 to 3 nm.
[0043] In this invention, the gate electrode 3 is changed to a heterogeneous gate structure, which can induce an N-type window 2 in its lower channel, reduce the lateral tunneling distance at the source / channel tunneling junction, thereby enhancing the electron tunneling rate at this location, and thus resulting in a higher sensing margin in the technical solution provided in this application.
[0044] The second dielectric layer 702 is selected as hafnium dioxide to enhance the electric field strength between the source region 4 and the N-type window 2, as well as between the storage window 1 and the drain region 5, aiming to further improve the storage performance of the device. The material of the storage window 1 is selected as SiGe, utilizing the valence band offset characteristics of SiGe and Si to act as a barrier to block hole movement, constructing more efficient hole storage to improve sensing margin and retention time.
[0045] The fabrication method of the undoped, capacitor-free dynamic random access memory provided by this utility model is as follows:
[0046] The silicon wafer and silicon-on-insulator (SOI) wafer were cleaned using the industry standard wet cleaning process (RCA). Then, platinum (Pt) was sputtered onto the surface of the silicon wafer as the source 301 and covered with an adhesion layer of titanium nitride (TiN). Finally, a thick layer of SiO2 was deposited on the SOI wafer.
[0047] The silicon wafer adhesion layer and the SOI silicon dioxide side are bonded together using plasma-assisted bonding technology, and the bonded silicon wafer is annealed to improve the bonding strength, thus obtaining a silicon substrate.
[0048] The designed pattern is transferred to the surface of the bonded silicon wafer using photoresist and a mask, and the active region is etched out using reactive ion etching (RIE) process, which serves as the source region 4, N-type window 2 and intrinsic channel region 8 of the memory. Subsequently, the RCA process is used to remove photoresist residue, etching byproducts and surface contaminants.
[0049] SiGe memory material layer and intrinsic silicon layer are grown sequentially, which are used as memory window 1 and drain region 5, respectively. Source region 4 is formed by etching away the excess parts on both sides after growing silicon layer using reactive ion etching (RIE) process to form groove part. Drain region 5 is formed by growing silicon layer directly in groove.
[0050] Atomic layer deposition technology is used to deposit source and gate metal electrodes, SiO2 and HfO2 dielectric layers on both sides of a silicon substrate, and RIE process is used to etch these two dielectric layers. The source electrode 301 is on the silicon dioxide dielectric layer and the drain electrode 302 is below the silicon dioxide dielectric layer.
[0051] Two U-shaped grooves are etched using the RIE process, followed by the deposition of a drain 302 metal electrode and a SiO2 dielectric layer. Finally, the contact points, electrode 3, and gate electrode 6 are connected to prepare an undoped, capacitor-free dynamic random access memory.
[0052] The working principle of this invention is as follows: For the "1" write operation, a negative bias is applied to the third gate electrode 603, causing bidirectional tunneling of electrons and holes between the storage window 1 and the drain region 5. This accumulates a large number of holes in the storage window 1, maintaining the hole concentration while maintaining the "1" state. For the "1" read operation, a positive bias is applied to the first gate electrode 601 to control band tunneling between the source region 4 and the N-type window 2. This allows a large number of electrons to tunnel from the valence band of the source region 4 to the conduction band of the N-type window 2 and flow to the drain region 5, thus forming a "1" read current. In contrast to the "1" write operation, the "0" write operation is achieved by applying a positive bias to the third gate electrode 603 to eliminate the holes stored in the storage window 1 from the potential well. For the "0" read operation, band tunneling between the storage window 1 and the drain region 5 is relied upon, and the channel barrier under the third gate electrode 603 prevents electrons tunneling from the source region 4 from flowing to the drain region 5, thereby achieving a low "0" read current.
[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.
Claims
1. A doped, capacitor-free dynamic random access memory, characterized in that, include: A silicon substrate, with a first U-shaped groove and a second U-shaped groove symmetrically formed on the left and right edge regions; A storage window (1) is embedded on the surface of the silicon substrate, and the storage window (1) is close to the second U-shaped groove; An N-type window (2) is embedded on the surface of the silicon substrate on which the storage window (1) is provided. The N-type window (2) is close to the first U-shaped groove. An intrinsic channel region (8) is provided between the N-type window (2) and the storage window (1). The electrode (3) includes a source (301) and a drain (302). The source (301) is disposed in the first U-shaped groove, and the drain (302) is disposed in the second U-shaped groove. A drain region (5) is disposed between the drain (302) and the storage window (1), and a source region (4) is disposed between the source (301) and the N-type window (2). A gate electrode (6) is embedded at the upper and lower edges of the silicon substrate, and the electrode (3) is electrically connected to the gate electrode (6). The dielectric layer (7) covers the positions where the N-type window (2), electrode (3), source region (4) and gate electrode (6) are located.
2. The undoped, capacitor-free dynamic random access memory according to claim 1, characterized in that: The storage window (1) is located on the right side of the intrinsic channel region (8), and the storage window (1) and the drain (302) form the drain region (5). The N-type window (2) is located on the left side of the intrinsic channel region (8), and the N-type window (2) and the source (301) form the source region (4).
3. The undoped, capacitor-free dynamic random access memory according to claim 2, characterized in that: The drain (302) is made of hafnium metal, the source (301) is made of platinum metal, the vertical lengths of the drain (302) and the source (301) are matched with the width of the silicon substrate, and there is a gap between the drain (302) and the source (301) and the gate electrode (6).
4. The undoped, capacitor-free dynamic random access memory according to claim 3, characterized in that: The dielectric layer (7) includes a first dielectric layer (701) and a second dielectric layer (702). The gate electrode (6) includes a first gate electrode (601), a second gate electrode (602), and a third gate electrode (603). The first dielectric layer (701) covers the source electrode (301) and the source region (4). The second dielectric layer (702) covers the N-type window (2) and the first gate electrode (601). The first dielectric layer (701) covers the second gate electrode (602) and one side of the storage window (1). The second dielectric layer (702) covers the third gate electrode (603). The first dielectric layer (701) covers the drain region (5) and the drain electrode (302). Two of each of the first gate electrode (601) and the second gate electrode (602) are provided. The first gate electrode (601) is provided on both sides of the second dielectric layer (702) of the N-type window (2). At both ends of the first gate electrode (602), the second gate electrode (602) is disposed to the right of the first gate electrode (601). The length of the first gate electrode (601) is less than that of the second gate electrode (602). The length of the first gate electrode (601) is less than that of the second dielectric layer (702) near the N-type window (2) and greater than half the length of the second dielectric layer (702). The length of the first gate electrode (601) is equal to the length of the N-type window (2). The third gate electrode (603) is disposed at the upper end of the second dielectric layer (702) near the storage window (1). There is a gap between the source electrode (301) and the first gate electrode (601). There is a gap between the second gate electrode (602) and the third gate electrode (603). There is a gap between the third gate electrode (603) and the drain electrode (302).
5. The undoped, capacitor-free dynamic random access memory according to claim 4, characterized in that: The first dielectric layer (701) is silicon dioxide, the second dielectric layer (702) is hafnium dioxide, the first gate electrode (601) is zinc, the second gate electrode (602) is gallium, and the third gate electrode (603) is copper.
6. The undoped, capacitor-free dynamic random access memory according to claim 4, characterized in that: The intrinsic channel region (8), source region (4) and drain region (5) are made of silicon, the storage window (1) is made of SiGe, and the thickness of the first dielectric layer (701) and the second dielectric layer (702) is 1 to 3 nm.