Chip packaging structure, light bar structure and display equipment
By setting chip pins and circuit pins on the chip body and substrate, and achieving electrical connection through the connection part, the problems of chip packaging complexity and excessive size in the prior art are solved, enabling wider application.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BEIJING XIANXIN TECH CO LTD
- Filing Date
- 2025-05-29
- Publication Date
- 2026-04-28
AI Technical Summary
In existing LED strip structures, due to the small chip size, the spacing between chip pins is usually less than 100μm, making it difficult to process and mount on the circuit board. This results in a complex packaging process, consumes more materials, and the packaged chip size is much larger than the initial size, occupying a large volume, and some components cannot be arranged closely.
By providing chip pins on the chip body and circuit pins on the substrate, and connecting the chip pins and circuit pins through a connector, the packaging process is simplified, and the consumption of packaging materials and process complexity are reduced.
It simplifies the chip packaging process, reduces the chip's footprint and the amount of packaging materials used, and expands the application range of chip packaging structures.
Smart Images
Figure CN224178543U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to a chip packaging structure, a light strip structure, and a display device. Background Technology
[0002] In recent years, the development of display devices in the display field has been quite rapid. These devices can display various information such as text, images, and videos. As an important component of display devices, LED strips are widely used in televisions, monitors, and laptops.
[0003] With the development of display technology, packaging technology is also constantly advancing to support smaller, higher-density, and more efficient LED strip structures. These LED strip structures can include chips, and chip packaging is the process of physically protecting and electrically connecting the chips. Packaging technology has a significant impact on the performance, reliability, and lifespan of the chips.
[0004] In existing LED strip structures, due to the small chip size and pin spacing (typically less than 100μm), it's difficult to fabricate and mount the chips onto a circuit board. Therefore, complex processes, equipment, and manpower are required for chip packaging, consuming significant amounts of packaging materials to create larger-pitched connection pins for circuit board mounting. Consequently, the packaged chip size is much larger than its initial size, occupying a larger volume and rendering some closely spaced devices unusable. Utility Model Content
[0005] This application provides a chip packaging structure, a light strip structure, and a display device. By providing chip pins on the chip body and circuit pins on the substrate, and connecting the chip pins and circuit pins through a connecting part, the chip packaging process is simplified, the processing between the chip and the circuit board is facilitated, the volume occupied by the chip, the consumption of packaging materials, and the complexity of the process are reduced, making the chip packaging structure more widely applicable.
[0006] In a first aspect, embodiments of this application provide a chip packaging structure, including:
[0007] The chip body has multiple chip pins;
[0008] The substrate is located on one side of the chip body. The substrate has a first side and a second side facing each other. The first side is attached to the chip body, and the second side has multiple circuit pins.
[0009] The connector has one end connected to a chip pin along at least a portion of the substrate surface, and the other end connected to a circuit pin.
[0010] The chip packaging structure provided in the first aspect of this application includes a chip body, a substrate, and a connection portion. The chip body has multiple chip pins. The substrate is located on one side of the chip body and has opposing first and second surfaces. The first surface is attached to the chip body, and the second surface has multiple circuit pins. One end of the connection portion is connected to the chip pins along at least a portion of the surface of the substrate, and the other end of the connection portion is connected to the circuit pins. Thus, the chip packaging structure provided in this application simplifies the chip packaging process by providing chip pins on the chip body and circuit pins on the substrate, and connecting the chip pins and circuit pins through the connection portion. This facilitates the processing between the chip and the circuit board, reduces the volume occupied by the chip, the consumption of packaging materials, and the complexity of the process, making the chip packaging structure more widely applicable.
[0011] In one possible implementation, the orthogonal projection of the substrate toward the chip body completely covers the chip body.
[0012] In one possible implementation, the first surface of the substrate includes a first region and a second region surrounding the periphery of the first region.
[0013] The chip body and the first region are bonded together.
[0014] In one possible implementation, the substrate has a plurality of vias, and the vias are provided with corresponding circuit pins;
[0015] The connector is connected to the circuit pins through a via.
[0016] In one possible implementation, the via wall is provided with a conductive layer, one end of which is connected to the connection portion and the other end of which is connected to the circuit pin.
[0017] In one possible implementation, the connecting portion is disposed around the outer periphery of the substrate along the second region and is connected to the circuit pin.
[0018] In one possible implementation, it further includes: an insulating layer;
[0019] An insulating layer covers a second region on the first side of the substrate and the second side of the substrate.
[0020] In one possible implementation, multiple chip pins are arranged along the outer periphery of the chip body;
[0021] Multiple circuit pins are arranged along the outer periphery of the second side of the substrate.
[0022] Secondly, embodiments of this application provide a light strip structure, including:
[0023] Circuit board;
[0024] Light-emitting diode;
[0025] The chip packaging structure and the light-emitting diode are both electrically connected to the circuit board.
[0026] Thirdly, embodiments of this application provide a display device including a plurality of the above-described light strip structures.
[0027] It should be understood that the second and third aspects of this application correspond to the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, so they will not be described again.
[0028] In addition to the technical problems solved by this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions as described above, other technical problems solved by the chip packaging structure, light bar structure, and display device provided by this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific embodiments. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments of this application or the prior art will be briefly introduced below. Obviously, the drawings described below are only a part of the embodiments of this application. These drawings and text descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1 This is a front view of a chip packaging structure provided in an embodiment of this application;
[0031] Figure 2 This is a top view of a chip packaging structure provided in an embodiment of this application;
[0032] Figure 3 A front view of another chip packaging structure provided in an embodiment of this application;
[0033] Figure 4 A top view of another chip packaging structure provided in this application embodiment;
[0034] Figure 5 This is a schematic diagram of the light strip structure provided in an embodiment of this application.
[0035] Explanation of reference numerals in the attached figures:
[0036] 100-Chip package structure;
[0037] 200 - Chip body; 210 - Chip pins;
[0038] 300 - Substrate; 310 - First surface; 311 - First region; 312 - Second region; 320 - Second surface; 321 - Circuit pin; 330 - Via; 331 - Conductive layer;
[0039] 400 - Connecting part;
[0040] 500 - Insulation layer;
[0041] 600 - Adhesive components;
[0042] 700-LED strip structure;
[0043] 800 - Circuit board. Detailed Implementation
[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0045] This application provides a display device, which is an electronic device used to present visual information and is widely used in various consumer electronics, computing devices, and professional applications. For example, a display device can be a television, smartphone screen, tablet screen, projector, or computer monitor.
[0046] The display device may include multiple light strip structures. A light strip structure typically refers to a device consisting of a series of chips arranged on a circuit board to provide linear illumination.
[0047] As described in the background section, in existing LED strip structures, due to the small chip size and pin spacing (typically less than 100μm), it is difficult to fabricate and mount the chips onto a circuit board. Therefore, complex processes, equipment, and manpower are required for chip packaging, consuming significant amounts of packaging materials to create larger-pitched connection pins for circuit board mounting. Consequently, the packaged chip size is much larger than its initial size, occupying a larger volume and rendering some closely spaced devices unusable.
[0048] To address the aforementioned technical problems, embodiments of this application provide a chip packaging structure, a light strip structure, and a display device. The chip packaging structure provided in the first aspect of this application includes a chip body, a substrate, and a connecting portion. The chip body has multiple chip pins. The substrate is located on one side of the chip body and has opposing first and second surfaces. The first surface is attached to the chip body, and the second surface has multiple circuit pins. One end of the connecting portion connects to the chip pins along at least a portion of the substrate surface, and the other end of the connecting portion connects to the circuit pins. Thus, the chip packaging structure provided in this application simplifies the chip packaging process by providing chip pins on the chip body and circuit pins on the substrate, and connecting the chip pins and circuit pins through the connecting portion. This facilitates the processing between the chip and the circuit board, reduces the volume occupied by the chip, the consumption of packaging materials, and the complexity of the process, making the chip packaging structure more widely applicable.
[0049] The light strip structure provided in the second aspect of this application includes a circuit board, a light-emitting diode (LED), and the aforementioned chip package structure. Both the chip package structure and the LED are electrically connected to the circuit board.
[0050] The display device provided in the third aspect of this application includes a plurality of the above-described light strip structures.
[0051] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0052] This application provides a chip packaging structure, a light strip structure, and a display device. By providing chip pins on the chip body and circuit pins on the substrate, and connecting the chip pins and circuit pins through a connecting part, the chip packaging process is simplified, the processing between the chip and the circuit board is facilitated, and the volume occupied by the chip, the consumption of packaging materials, and the complexity of the process are reduced, making the chip packaging structure more widely applicable. The specific structures of the chip packaging structure, light strip structure, and display device provided in this application embodiment are described below with reference to the accompanying drawings.
[0053] refer to Figure 1 The first aspect of this application provides a chip packaging structure 100. The chip packaging structure 100 includes a chip body 200, a substrate 300, and a connection portion 400. In one possible implementation, such as... Figure 2As shown, the chip body 200 may have chip pins 210. The number of chip pins 210 can be several, and this embodiment of the application does not limit this. The substrate 300 may be located on one side of the chip body 200, and the chip body 200 and the substrate 300 may be electrically connected through several chip pins 210.
[0054] Continue to refer to Figure 1 Based on the above embodiments, the substrate 300 may have a first surface 310 and a second surface 320, wherein the first surface 310 and the second surface 320 may be disposed opposite to each other. It is understood that the chip body 200 may be located on one side of the first surface 310 of the substrate 300, and the first surface 310 may be attached to the chip body 200. The chip body 200 is fixedly connected to the first surface 310 of the substrate 300 through a plurality of chip pins 210. Additionally, the second surface 320 of the substrate 300 may have circuit pins 321, and the number of circuit pins 321 may be plurality; this embodiment of the application does not limit the number of such pins.
[0055] Continue to refer to Figure 1 Based on the above embodiments, in one possible implementation, one end of the connection portion 400 may extend along at least a portion of the surface of the substrate 300 and connect to the chip pin 210, while the other end of the connection portion 400 may connect to the circuit pin 321, thereby achieving an electrical connection between the chip pin 210 and the circuit pin 321. In this way, the chip body 200 can be directly connected to the circuit pin 321 through the connection portion 400, reducing the volume occupied by the chip, the consumption of packaging materials, and the complexity of the process, thus simplifying the chip packaging process.
[0056] Exemplarily, the substrate 300 can be made of glass, and this embodiment of the application is not limited thereto. It is understood that by using glass as the main encapsulation material, the substrate 300 has a stable dielectric constant. The dielectric constant of glass is approximately 5.5, with minimal variation with frequency, ensuring signal transmission consistency and reducing phase noise. Glass also has a low coefficient of thermal expansion, allowing for a high degree of matching between the glass and the chip, preventing chip cracking caused by thermal stress, and is suitable for direct chip mounting. Glass also has an ultra-flat surface, with a surface roughness typically less than 1 μm, meeting the device's precision requirements for the substrate 300. It also has microvia processing capabilities; microvias smaller than 50 μm can be achieved through laser drilling, supporting 10 μm linewidth / spacing for high-density wiring. Furthermore, glass offers advantages such as corrosion resistance, high temperature resistance, and low cost. It is resistant to acid, alkali, and organic solvent corrosion, suitable for harsh environments, and can withstand multiple high-temperature reflow soldering cycles. Using glass as a material results in low cost and a small application area, avoiding the fragility issues associated with large-area applications.
[0057] It is understood that the connecting part 400 can be made of a metallic material. For example, the connecting part 400 can be made of copper, but this embodiment is not limited thereto. In this way, the connecting part 400 has conductive properties, enabling electrical connection and signal conduction.
[0058] It is also understood that chip pin 210 can be made of a metallic material. Exemplarily, chip pin 210 can be made of copper or aluminum, and this embodiment is not limited thereto. In this way, chip pin 210 has conductive properties, enabling electrical connection and signal transmission.
[0059] Accordingly, circuit pin 321 can also be made of a metallic material. For example, circuit pin 321 can be made of a copper alloy and tin-plated on its surface; however, this embodiment is not limited thereto. In this way, circuit pin 321 has conductive properties, enabling electrical connection and signal transmission.
[0060] Continue to refer to Figure 2 Based on the above embodiments, in one possible implementation, the orthographic projection of the substrate 300 toward the chip body 200 can completely cover the chip body 200. This ensures that the area of the substrate 300 is always greater than or equal to the area of the chip body 200.
[0061] Because the chip body 200 has a small area, the spacing between the chip pins 210 is also small, making it inconvenient for subsequent surface mount processing with the circuit board 800. In this embodiment, the area of the substrate 300 is greater than or equal to the area of the chip body 200. Correspondingly, the spacing between the circuit pins 321 is larger. The electrical connection between the chip pins 210 and the circuit pins 321 is achieved through the connecting portion 400, which facilitates surface mount processing between the chip body 200 and the circuit board 800, simplifying the chip packaging process.
[0062] Continue to refer to Figure 2 Based on the above embodiments, in one possible implementation, a plurality of chip pins 210 can be arranged along the outer periphery of the chip body 200, so that the plurality of chip pins 210 can be arranged around the outer periphery of the chip body 200, and the plurality of chip pins 210 are spaced apart.
[0063] Accordingly, in one possible implementation, a plurality of circuit pins 321 may be arranged along the outer periphery of the second surface 320 of the substrate 300, so that the plurality of circuit pins 321 can be arranged around the outer periphery of the substrate 300, and the plurality of circuit pins 321 are spaced apart.
[0064] Continue to refer to Figure 1 Based on the above embodiments, the first surface 310 of the substrate 300 may further include a first region 311 and a second region 312. The second region 312 may surround the outer periphery of the first region 311. In this embodiment, the first region 311 may be located inside the second region 312, and the chip body 200 may be attached to the first region 311. In one possible implementation, the orthographic projection of the first region 311 toward the chip body 200 can completely cover the chip body 200, and the second region 312 may be attached along the outer periphery of the first region 311 and the chip body 200.
[0065] Continue to refer to Figure 1 Based on the above embodiments, the chip package structure 100 may further include an insulating layer 500. In one possible implementation, the insulating layer 500 may cover the second region 312 of the first surface 310 of the substrate 300 and the second surface 320 of the substrate 300. It should be noted that the insulating layer 500 on the second surface 320 of the substrate 300 should be positioned to avoid the circuit pin 321, thereby facilitating electrical connection between the circuit pin 321 and other components.
[0066] It is understood that the insulating layer 500 can protect the substrate 300 and its internal connection circuits. Exemplarily, the insulating layer 500 can be made of a thin-film insulating material, and this application embodiment is not limited thereto.
[0067] Continue to refer to Figure 1 as well as Figure 2 Based on the above embodiments, in one possible implementation, vias 330 may be formed on the substrate 300. The number of vias 330 can be several, and this application embodiment does not limit the number. It is understood that the number of vias 330 is the same as the number of circuit pins 321, and each via 330 corresponds to each circuit pin 321. In this application embodiment, the vias 330 can be arranged to extend along the height direction of the substrate 300. The connecting portion 400 can be electrically connected to the circuit pin 321 through the vias 330.
[0068] Continue to refer to Figure 1 as well as Figure 2Based on the above embodiments, in one possible implementation, a conductive layer 331 may be provided on the wall of the via 330, and the conductive layer 331 may be attached to the wall of the via 330. In this embodiment, one end of the conductive layer 331 may be connected to the connection portion 400, and the other end of the conductive layer 331 may be connected to the circuit pin 321. In this way, the chip body 200 can be connected to one end of the connection portion 400 through the chip pin 210, and the other end of the connection portion 400 is connected to the conductive layer 331. The conductive layer 331 is then connected to the circuit pin 321, thereby enabling the chip body 200 and the circuit pin 321 to be electrically connected.
[0069] For example, copper can be electroplated on the wall of the via 330 to form a conductive layer 331, and this embodiment of the application is not limited thereto. In this way, the conductive layer 331 on the wall of the via has conductive properties, which can enable electrical connection and realize signal transmission.
[0070] Understandably, by creating vias 330 on the substrate 300, the length of the traces is reduced, thereby saving costs. Furthermore, placing the circuit traces inside the substrate 300 also helps to prevent them from touching other components, thus avoiding any impact on them.
[0071] refer to Figure 3 as well as Figure 4 In another possible implementation, the connecting portion 400 may be disposed around the outer periphery of the substrate 300 along the second region 312 of the substrate 300 and connected to the circuit pin 321. It is understood that the connecting portion 400 may extend along the second region 312 of the substrate 300, bend and extend along the side of the substrate 300, and then bend and extend along the second surface 320 of the substrate 300 to the location of the circuit pin 321, thereby achieving electrical connection with the circuit pin 321. In this way, the chip body 200 can be connected to one end of the connecting portion 400 via the chip pin 210, and the other end of the connecting portion 400 can be connected to the circuit pin 321, thereby achieving electrical connection between the chip body 200 and the circuit pin 321.
[0072] Understandably, by connecting the connecting part 400 around the substrate 300, the operation is simple and the processing difficulty is reduced.
[0073] Continue to refer to Figure 2 as well as Figure 4Based on the above embodiments, in one possible implementation, the chip body 200 can also be fixedly connected to the substrate 300 via an adhesive 600. In this embodiment, the chip body 200 can be bonded to the first region 311 of the first surface 310 of the substrate 300 via the adhesive 600. Exemplarily, the adhesive 600 can be an insulating adhesive, and this embodiment is not limited thereto.
[0074] It is understood that, by way of example, the chip package structure 100 provided in this application embodiment can be a driver chip structure. Of course, in some other embodiments, the chip package structure 100 can also be a chip structure with other performance characteristics, and this application embodiment does not impose any limitations here. By simplifying the chip packaging process, the manufactured driver chip structure is smaller in size, thereby saving a lot of space and facilitating the application of the chip package structure 100.
[0075] refer to Figure 5 A second aspect of this application provides a light strip structure 700. The light strip structure 700 may include a circuit board 800, a light-emitting diode (LED) (not shown), and the aforementioned chip package structure 100. In one possible implementation, the LED may be located on one side of the chip package structure 100, and the LED may be connected to the chip package structure 100. Furthermore, both the chip package structure 100 and the LED may be electrically connected to the circuit board 800.
[0076] Continue to refer to Figure 5 Based on the above embodiments, in one possible implementation, the circuit pins 321 of the chip package structure 100 can be electrically connected to the circuit board 800, thereby fixing the chip package structure 100 to the circuit board 800.
[0077] Understandably, the circuit board 800 can provide power to the chip package structure 100 and the light-emitting diode, the chip package structure 100 can drive the light-emitting diode to emit light, and the chip package structure 100 can also control the brightness of the light-emitting diode and monitor various performance aspects such as whether the light-emitting diode is short-circuited.
[0078] In one possible implementation, for example, the circuit board 800 may include a single-layer aluminum substrate, an epoxy fiberglass board, a glass substrate, or the like. The circuit board 800 may be formed by stacking single-layer aluminum substrates, epoxy fiberglass boards, and glass substrates.
[0079] Continue to refer to Figure 5Based on the above embodiments, by employing surface mount technology, the chip package structure 100 can be fixedly connected to the circuit board 800. In this embodiment, the chip package structure 100 allows the circuit board 800 to adopt a single-layer structure, reducing its thickness compared to a stacked circuit board 800 and further saving space.
[0080] It is understood that the chip packaging structure 100 provided in this application embodiment can achieve a smaller packaging area, thereby achieving a high-density placement on the circuit board 800, which makes the overall appearance of the light strip structure 700 narrower and can also save materials on the circuit board 800, thereby saving costs.
[0081] A third aspect of this application provides a display device (not shown in the figures). This display device may include the aforementioned light strip structure 700. In one possible implementation, the number of light strip structures 700 may be plurality of them, and this application embodiment does not impose a limitation thereon. In this application embodiment, plurality of light strip structures 700 may be fixedly connected.
[0082] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0083] It should be noted that phrases such as "in specific implementations," "in some embodiments," "in this embodiment," and "exemplarily" in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.
[0084] Generally speaking, terms should be understood at least in part by their use in context. For example, at least in part by context, the term "one or more" as used in the text can be used to describe any feature, structure, or characteristic of the singular meaning, or a combination of features, structures, or characteristics of the plural meaning. Similarly, at least in part by context, terms such as "a" or "the" can also be understood to convey either singular or plural usage.
[0085] It should be readily understood that “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on something” but also “on something” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “on something” but also “on something” without an intermediate feature or layer therebetween (i.e., directly on something).
[0086] Furthermore, for ease of explanation, spatially relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature relative to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.
[0087] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.
Claims
1. A chip packaging structure, characterized in that, include: The chip body (200) has a plurality of chip pins (210); A substrate (300) is located on one side of the chip body (200). The substrate (300) has a first surface (310) and a second surface (320) facing each other. The first surface (310) is attached to the chip body (200), and the second surface (320) has a plurality of circuit pins (321). A connection portion (400) has one end connected to a chip pin (210) along at least a portion of the surface of the substrate (300), and the other end connected to a circuit pin (321).
2. The chip packaging structure according to claim 1, characterized in that, The orthographic projection of the substrate (300) toward the chip body (200) completely covers the chip body (200).
3. The chip packaging structure according to claim 2, characterized in that, The first surface (310) of the substrate (300) includes a first region (311) and a second region (312) surrounding the outer periphery of the first region (311). The chip body (200) and the first region (311) are attached together.
4. The chip packaging structure according to any one of claims 1-3, characterized in that, The substrate (300) has a plurality of vias (330), and the vias (330) are correspondingly provided with the circuit pins (321); The connecting part (400) is connected to the circuit pin (321) through the via (330).
5. The chip packaging structure according to claim 4, characterized in that, The via (330) has a conductive layer (331) on its wall. One end of the conductive layer (331) is connected to the connection part (400), and the other end of the conductive layer (331) is connected to the circuit pin (321).
6. The chip packaging structure according to claim 3, characterized in that, The connecting portion (400) is disposed around the outer periphery of the substrate (300) along the second region (312) and is connected to the circuit pin (321).
7. The chip packaging structure according to claim 3, characterized in that, Also includes: Insulation layer (500); The insulating layer (500) covers the second region (312) of the first side (310) of the substrate (300) and the second side (320) of the substrate (300).
8. The chip packaging structure according to any one of claims 1-3, characterized in that, Multiple chip pins (210) are arranged along the outer periphery of the chip body (200); Multiple circuit pins (321) are arranged along the outer periphery of the second side (320) of the substrate (300).
9. A light strip structure, characterized in that, include: Circuit board (800); Light-emitting diode; And the chip packaging structure (100) according to any one of claims 1-8 above, wherein the chip packaging structure (100) and the light-emitting diode are both electrically connected to the circuit board (800).
10. A display device, characterized in that, It includes multiple light bar structures (700) as described in claim 9 above.