Vertical junction field effect transistor
By designing a vertical junction field-effect transistor and using a combination of doped semiconductors with specific thickness and structure, the problems of large area occupation and insufficient voltage withstand of horizontal junction field-effect transistors have been solved, achieving reliability and cost-effectiveness in high-voltage applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- WISETOP TECHNOLOGY CO LTD
- Filing Date
- 2025-04-23
- Publication Date
- 2026-05-01
AI Technical Summary
Existing horizontally junction field-effect transistors occupy a large surface area and are difficult to withstand high voltage, thus failing to meet the requirements of high-voltage applications.
The design of a vertical junction field-effect transistor employs a combination of a first-doped semiconductor structure, a second-doped semiconductor structure, and a third-doped semiconductor structure. The thickness of the protrusions ranges from 15 micrometers to 50 micrometers. The third-doped semiconductor structure is flush with the protrusions to form a thick depletion region, increasing the electric field distribution distance and reducing the etching depth requirement.
This enables high voltage tolerance on a smaller surface area, improves gate-source breakdown voltage and reverse withstand voltage characteristics, and reduces process difficulty and cost.
Smart Images
Figure CN224192337U_ABST
Abstract
Description
Vertical junction field-effect transistor Technical Field
[0001] This application relates to a vertical junction field-effect transistor. Background Technology
[0002] A junction field-effect transistor (JFET) is a voltage-controlled transistor with a source, drain, and gate. JFETs typically use the gate-source voltage to control the current between the source and drain. JFETs are available in N-channel and P-channel types. In an N-channel JFET, applying a negative voltage between the gate and source expands the depletion region within the channel, reducing the effective channel width and thus decreasing the current. Conversely, a decrease in the absolute value of the negative voltage or the application of a positive voltage shrinks the depletion region, increasing the effective channel width and thus increasing the current. Due to their high input impedance and low noise characteristics, JFETs are widely used in high input impedance amplifiers, low noise amplifiers, differential amplifiers, constant current sources, and analog switches.
[0003] Typical junction field-effect transistors (FETs) are horizontal junction field-effect transistors, where the channel is parallel to the surface of the semiconductor substrate, and the main flow direction of current between the source and drain is horizontal. The fabrication process for this type of junction field-effect transistor is relatively mature.
[0004] However, because the main current flow direction of a horizontally junction field-effect transistor (MOSFET) is horizontal, it occupies a larger surface area. Furthermore, the higher the operating voltage a horizontally junction MOSFET can withstand, the larger the surface area it occupies.
[0005] In view of this, how to design a junction field-effect transistor that occupies a small surface area and can withstand high voltage is one of the problems that urgently need to be solved. Summary of the Invention
[0006] This application provides a vertical junction field-effect transistor that can occupy a small surface area and withstand high voltage.
[0007] This application provides a vertical junction field-effect transistor, comprising: a first doped semiconductor structure; a second doped semiconductor structure including a layer and protrusions protruding from the layer, wherein the doping type of the second doped semiconductor structure is the same as that of the first doped semiconductor structure; and a third doped semiconductor structure disposed on both sides of the protrusions and disposed on the layer, wherein the doping type of the third doped semiconductor structure is different from that of the first doped semiconductor structure; wherein the thickness of the protrusions is greater than 15 micrometers and less than or equal to 50 micrometers.
[0008] In one embodiment, the convex pillar further includes: a first convex pillar body; and a second convex pillar body, stacked on the first convex pillar body, such that the total thickness of the first convex pillar body and the second convex pillar body is greater than 15 micrometers and less than or equal to 50 micrometers; wherein the crystal forms of the first convex pillar body and the second convex pillar body are different.
[0009] In one embodiment, the protrusion further includes: a first protrusion body; and a second protrusion body, stacked on the first protrusion body, such that the total thickness of the first protrusion body and the second protrusion body is greater than 15 micrometers and less than or equal to 50 micrometers; wherein the first protrusion body is formed by a first deposition process, and the second protrusion body is formed by a second deposition process.
[0010] In one embodiment, the thickness of the third doped semiconductor structure is less than the thickness of the protrusion.
[0011] In one embodiment, the top of the third doped semiconductor structure is flush with the top of the protrusion.
[0012] In one embodiment, the third-doped semiconductor structure includes: a first substrate; and an extension protruding from the first substrate. The crystal form of the first substrate and the crystal form of the extension are the same.
[0013] In one embodiment, the third doped semiconductor structure includes: a first substrate; and a second substrate stacked on the first substrate; wherein the crystal forms of the first substrate and the second substrate are different.
[0014] In one embodiment, the third doped semiconductor structure includes: a first substrate; and
[0015] A second substrate is stacked on a first substrate; wherein the first substrate is formed by a doping process and the second substrate is formed by a deposition process.
[0016] In one embodiment, the thickness of the first doped semiconductor structure is greater than or equal to 50 micrometers and less than or equal to 100 micrometers.
[0017] In one embodiment, the doping concentration of the first doped semiconductor structure is greater than the doping concentration of the second doped semiconductor structure.
[0018] In summary, the thickness of the first doped semiconductor structure of the vertical junction field-effect transistor (VJT) of this application is greater than or equal to 50 micrometers and less than or equal to 100 micrometers; and the doping concentration of the first doped semiconductor structure is greater than the doping concentration of the second doped semiconductor structure. Therefore, the VJT exhibits a higher gate-source breakdown voltage. In high-voltage applications, the VJT's channels can effectively control current and prevent device damage.
[0019] Furthermore, the thickness of the protrusions of the vertical junction field-effect transistor (DFET) of this application is greater than 15 micrometers and less than or equal to 50 micrometers, giving the DFET a depletion region with a depth greater than 15 micrometers and less than or equal to 50 micrometers. The deeper depletion region increases the electric field distribution distance within the DFET's channels, preventing excessively large local electric fields from causing DFET breakdown.
[0020] Furthermore, the top of the third doped semiconductor structure of the vertical junction field-effect transistor (VJT) of this application can be flush with the top of the protrusion to form a thicker depletion region. A thicker depletion region can trap a longer conductive channel. Therefore, the VJT exhibits excellent reverse breakdown voltage characteristics, thereby improving its operating range.
[0021] Furthermore, the vertical junction field-effect transistor of this application also includes a first protrusion and a second protrusion, which reduces the etching depth requirement. The thickness is supplemented by the second protrusion, making the total thickness of the first and second protrusions greater than 15 micrometers and less than or equal to 50 micrometers. This reduces the manufacturing difficulty and cost of the vertical junction field-effect transistor. Attached Figure Description
[0022] Details of one or more embodiments of the subject matter described herein are set forth in the following drawings and description. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims, wherein:
[0023] Figure 1 is a schematic diagram of a vertical junction field-effect transistor according to the first embodiment of this application.
[0024] Figure 2A is a schematic diagram of the variation state of the third doped semiconductor structure of the vertical junction field-effect transistor of the first embodiment of this application.
[0025] Figure 2B is a schematic diagram of another variation of the third-doped semiconductor structure of the vertical junction field-effect transistor of the first embodiment of this application.
[0026] Figure 3 is a schematic diagram of a vertical junction field-effect transistor according to the second embodiment of this application.
[0027] Figure 4A is a schematic diagram of the variation state of the third doped semiconductor structure of the vertical junction field-effect transistor of the second embodiment of this application.
[0028] Figure 4B is a schematic diagram of another variation of the third doped semiconductor structure of the vertical junction field-effect transistor of the second embodiment of this application.
[0029] Figures 5A to 5F are schematic diagrams illustrating the manufacturing method of the vertical junction field-effect transistor of this application.
[0030] Explanation of reference numerals in the attached figures:
[0031] 1: Vertical junction field-effect transistor;
[0032] 1A: Vertical junction field-effect transistor;
[0033] 1B: Vertical junction field-effect transistor;
[0034] 1C: Vertical junction field-effect transistor;
[0035] 1D: Vertical junction field-effect transistor;
[0036] 1E: Vertical junction field-effect transistor;
[0037] 11: First-doped semiconductor structure;
[0038] 12: Second-doped semiconductor structure;
[0039] 13: Third-doped semiconductor structure;
[0040] 121: Layers;
[0041] 122: Convex column;
[0042] 131: First matrix;
[0043] 132: Second matrix;
[0044] 133: Extension;
[0045] 1221: First convex cylinder;
[0046] 1222: Second convex cylinder;
[0047] H122: Thickness;
[0048] H11: Thickness;
[0049] H13: Thickness. Detailed Implementation
[0050] The detailed description and technical content of this application are illustrated below with reference to the accompanying drawings. However, the accompanying drawings are provided for reference and illustration only and are not intended to limit this application.
[0051] As used herein, terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or parts, which should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Unless the context clearly indicates otherwise, the use of terms such as "first," "second," and "third" herein does not imply any order or sequence.
[0052] Figure 1 is a schematic diagram of a vertical junction field-effect transistor according to the first embodiment of this application. Referring to Figure 1, the vertical junction field-effect transistor 1 of this embodiment includes a first doped semiconductor structure 11, a second doped semiconductor structure 12, and a third doped semiconductor structure 13.
[0053] The doping type of the first doped semiconductor structure 11 can be P-type or N-type. In this embodiment, the doping type of the first doped semiconductor structure 11 is N-type, but this is not a limitation. The shape of the first doped semiconductor structure 11 can be, for example, a cube, cuboid, disc, cylinder, or other three-dimensional shape. The material of the first doped semiconductor structure 11 can be, for example, monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon. Monocrystalline silicon (Mono-Si) is composed of a single crystal, and the atomic arrangement inside the crystal has a high degree of long-range order, with no grain boundaries. The advantage of monocrystalline silicon is that it has the highest electron mobility and conductivity, making it suitable for high-efficiency optoelectronic devices and semiconductor devices. Polycrystalline silicon (Poly-Si) is composed of multiple grains, and grain boundaries exist between the grains. The advantage of polycrystalline silicon is its lower manufacturing cost. Microcrystalline silicon (μc-Si) is between monocrystalline and polycrystalline, and has a micron-scale grain structure. The advantages of microcrystalline silicon materials include high electrical conductivity and low manufacturing cost. Amorphous silicon (a-Si) materials lack long-range atomic order. The advantages of amorphous silicon materials include low manufacturing cost and excellent light absorption properties in certain optoelectronic devices.
[0054] In one embodiment, the thickness H11 of the first doped semiconductor structure 11 is greater than or equal to 50 micrometers and less than or equal to 100 micrometers. The thickness H11 may be, for example, the distance from the top to the bottom of the first doped semiconductor structure 11, but is not limiting.
[0055] The second doped semiconductor structure 12 includes a layer 121 and protrusions 122 protruding from the layer 121. The doping type of the second doped semiconductor structure 12 is the same as that of the first doped semiconductor structure 11. The shape of the layer 121 can be, for example, a cube, cuboid, disc, cylinder, or other three-dimensional shape. The shape of the protrusions 122 can also be, for example, a cube, cuboid, disc, cylinder, or other three-dimensional shape. The protrusions 122 can, for example, protrude from the center of one side of the layer 121 or from another location. In this embodiment, the doping type of both the first doped semiconductor structure 11 and the second doped semiconductor structure 12 is N-type. In other embodiments, the doping type of both the first doped semiconductor structure 11 and the second doped semiconductor structure 12 can be P-type. The material of the second doped semiconductor structure 12 can be, for example, monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon.
[0056] In one embodiment, the doping concentration of the first doped semiconductor structure 11 is greater than the doping concentration of the second doped semiconductor structure 12. Doping concentration refers to the number of specific impurity atoms introduced into the first doped semiconductor structure 11 or the second doped semiconductor structure 12. Doping concentration is typically expressed as atoms per cubic centimeter (atoms / cm³). 3 () indicates that the conductivity of a semiconductor can be adjusted by varying the doping concentration, thereby affecting the performance and application of the device.
[0057] The third doped semiconductor structure 13 is disposed on both sides of the protrusion 122 and on the layer 121. The doping type of the third doped semiconductor structure 13 is different from that of the first doped semiconductor structure 11. The shape of the third doped semiconductor structure 13 can be, for example, a three-dimensional ring such as a circular ring or a square ring, fitted onto the protrusion 122 and in contact with the layer 121. Alternatively, the shape of the third doped semiconductor structure 13 can be, for example, a set of cubes or a set of cuboids, respectively disposed on both sides of the protrusion 122 and respectively in contact with the layer 121. In this embodiment, the doping types of the first doped semiconductor structure 11 and the second doped semiconductor structure 12 are both N-type, and the doping type of the third doped semiconductor structure 13 is both P-type. The material of the third doped semiconductor structure 13 can be, for example, monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon, or a combination thereof.
[0058] In one embodiment, the thickness H13 of the third doped semiconductor structure 13 is less than the thickness H122 of the protrusion 122. The thickness H13 can be, for example, the distance from the top to the bottom of the third doped semiconductor structure 13, but is not limiting. The thickness H122 can be, for example, the distance from the top to the bottom of the protrusion 122, but is not limiting.
[0059] Figure 2A is a schematic diagram of a variation of the third-doped semiconductor structure of the vertical junction field-effect transistor according to the first embodiment of this application. Referring to Figure 2A, the top of the third-doped semiconductor structure 13 can be flush with the top of the protrusion 122. In other words, the top of the third-doped semiconductor structure 13 can be substantially coplanar with the top of the protrusion 122. In other words, the thickness H13 of the third-doped semiconductor structure 13 is substantially equal to the thickness H122 of the protrusion 122.
[0060] The third doped semiconductor structure 13 may include a first substrate 131 and an extension 133.
[0061] The first substrate 131 can be, for example, a three-dimensional ring such as a circular ring or a square ring, fitted onto the protrusion 122 and in contact with the layer 121. The third doped semiconductor structure 13 can be, for example, a set of cubes or a set of cuboids, etc., respectively disposed on both sides of the protrusion 122 and respectively in contact with the layer 121.
[0062] An extension 133 protrudes from the first substrate 131. The shape of the extension 133 may be, for example, a three-dimensional ring such as a circular ring or a square ring, fitted onto the protrusion 122 and protruding from one side of the first substrate 131. The shape of the third doped semiconductor structure 13 may be, for example, a set of cubes, a set of cuboids, or other three-dimensional shapes respectively disposed on both sides of the protrusion 122 and protruding from one side of the first substrate 131.
[0063] The first substrate 131 and the extension 133 have the same crystal form. For example, the materials of the first substrate 131 and the extension 133 are both monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon, and the crystal arrangement is the same. In one embodiment, the first substrate 131 and the extension 133 are both fabricated using the same doping process. The doping concentration of the first substrate 131 and the doping concentration of the extension 133 can be the same or different.
[0064] Figure 2B is a schematic diagram of another variation of the third-doped semiconductor structure of the vertical junction field-effect transistor according to the first embodiment of this application. Referring to Figure 2B, the third-doped semiconductor structure 13 may include a first substrate 131 and a second substrate 132.
[0065] The first substrate 131 can be, for example, a three-dimensional ring such as a circular ring or a square ring, fitted onto the protrusion 122 and in contact with the layer 121. The third doped semiconductor structure 13 can be, for example, a set of cubes or a set of cuboids, etc., respectively disposed on both sides of the protrusion 122 and respectively in contact with the layer 121.
[0066] The second substrate 132 may be stacked on the first substrate 131. The shape of the second substrate 132 may be, for example, a three-dimensional ring such as a circular ring or a square ring, which is fitted onto the protrusion 122 and contacts the first substrate 131. The shape of the third doped semiconductor structure 13 may be, for example, a set of cubes, a set of cuboids, or other three-dimensional shapes respectively disposed on both sides of the protrusion 122 and respectively contacting the first substrate 131.
[0067] The first substrate 131 can be fabricated, for example, by a doping process, and the second substrate 132 can be fabricated, for example, by a deposition process. Since the doping depth of the doping process has its limits, the thickness of the first substrate 131 also has its limits. By filling the second substrate 132 with a deposition process, the total thickness of the first substrate 131 and the second substrate 132, which have the same doping type, can be increased.
[0068] The crystal forms of the first substrate 131 and the second substrate 132 can be different. For example, the material of the first substrate 131 is monocrystalline silicon, and the material of the second substrate 132 is polycrystalline silicon. Or, for example, the materials of the first substrate 131 and the second substrate 132 are both polycrystalline silicon, but the arrangement of their crystal forms is different.
[0069] Returning to Figure 1, the thickness H122 of the protrusion 122 is greater than 15 micrometers and less than or equal to 50 micrometers, and the third doped semiconductor structure 13 is disposed on the layer 121. In other words, the distance between the top of the protrusion 122 of the second doped semiconductor structure 12 and the bottom of the third doped semiconductor structure 13 is greater than 15 micrometers and less than or equal to 50 micrometers. Therefore, the vertical junction field-effect transistor 1 has a depletion region with a depth greater than 15 micrometers and less than or equal to 50 micrometers.
[0070] As described above, in this embodiment, the thickness H11 of the first doped semiconductor structure 11 of the vertical junction field-effect transistor 1 is greater than or equal to 50 micrometers and less than or equal to 100 micrometers; and the doping concentration of the first doped semiconductor structure 11 is greater than the doping concentration of the second doped semiconductor structure 12. Therefore, the vertical junction field-effect transistor 1 has a higher gate-source breakdown voltage. In high-voltage applications, the channel of the vertical junction field-effect transistor 1 can effectively control the current and prevent device damage.
[0071] Furthermore, in this embodiment, the thickness H122 of the protrusion 122 of the vertical junction field-effect transistor 1 is greater than 15 micrometers and less than or equal to 50 micrometers, giving the vertical junction field-effect transistor 1 a depletion region with a depth greater than 15 micrometers and less than or equal to 50 micrometers. The deeper depletion region increases the electric field distribution distance within the channel of the vertical junction field-effect transistor 1, preventing excessively large local electric fields from causing breakdown of the vertical junction field-effect transistor 1.
[0072] Furthermore, in this embodiment, the top of the third doped semiconductor structure 13 of the vertical junction field-effect transistors 1A and 1B can be flush with the top of the protrusion 122 to form a thicker depletion region. The thicker depletion region can clamp a longer conductive channel. Therefore, the vertical junction field-effect transistors 1A and 1B have excellent reverse breakdown voltage characteristics, thereby improving the operating range.
[0073] Figure 3 is a schematic diagram of a vertical junction field-effect transistor according to the second embodiment of this application. Referring to Figure 3, the difference between the vertical junction field-effect transistor 1C of the second embodiment and the vertical junction field-effect transistor 1 of the second embodiment (as shown in Figure 1) is that the protrusion 122 further includes a first protrusion 1221 and a second protrusion 1222. The first doped semiconductor structure 11 and the third doped semiconductor structure 13 of the second embodiment are similar to those of the first embodiment and will not be described again here.
[0074] The shape of the first convex cylinder 1221 can be, for example, a cube, cuboid, disc, cylinder, or other three-dimensional shape.
[0075] The second convex pillar 1222 is stacked on the first convex pillar 1221, such that the total thickness of the first convex pillar 1221 and the second convex pillar 1222 is greater than 15 micrometers and less than or equal to 50 micrometers. The shape of the second convex pillar 1222 can be a three-dimensional shape such as a cube, cuboid, disc, or cylinder, and it is in contact with the first convex pillar 1221.
[0076] The first protrusion 1221 can be left by first depositing a first deposition process and then removing the unwanted material through processes such as photolithography and etching. The second protrusion 1222 can be deposited on the first protrusion 1221 by a second deposition process.
[0077] The crystal forms of the first convex pillar 1221 and the second convex pillar 1222 can be different. For example, the material of the first convex pillar 1221 is monocrystalline silicon, and the material of the second convex pillar 1222 is polycrystalline silicon. Or, for example, the materials of the first convex pillar 1221 and the second convex pillar 1222 are both polycrystalline silicon, but the arrangement of the crystal forms is different.
[0078] Figure 4A is a schematic diagram of a variation of the third doped semiconductor structure of the vertical junction field-effect transistor according to the second embodiment of this application. Referring to Figures 2A and 4A, the variation of the third doped semiconductor structure 13 in the second embodiment can also have a similar variation to that in the first embodiment. The top of the third doped semiconductor structure 13 can be flush with the top of the protrusion 122. The third doped semiconductor structure 13 may include a first substrate 131 and an extension 133. The first substrate 131 protrudes. The first substrate 131 and the extension 133 can have the same crystal form.
[0079] Figure 4B is a schematic diagram of another variation of the third-doped semiconductor structure of the vertical junction field-effect transistor according to the second embodiment of this application. Referring to Figures 2B and 4B, the variation of the third-doped semiconductor structure 13 in the second embodiment can also have a similar variation to the third-doped semiconductor structure 13 in the first embodiment. The third-doped semiconductor structure 13 may include a first substrate 131 and a second substrate 132. The first substrate 131 and the second substrate 132 may be stacked on the first substrate 131. The crystal forms of the first substrate 131 and the second substrate 132 may be different. The first substrate 131 is fabricated by a doping process, and the second substrate 132 is fabricated by a deposition process.
[0080] As described above, the vertical junction field-effect transistors 1C, 1D, and 1E of this embodiment, in addition to possessing the functions of vertical junction field-effect transistors 1, 1A, and 1B, also reduce the etching depth requirement because the protrusion 122 includes a first protrusion 1221 and a second protrusion 1222. Furthermore, the thickness is supplemented by the second protrusion 1222, ensuring that the total thickness of the first protrusion 1221 and the second protrusion 1222 is greater than 15 micrometers and less than or equal to 50 micrometers. Therefore, the manufacturing process difficulty and cost of the vertical junction field-effect transistors 1C, 1D, and 1E are lower than those of the vertical junction field-effect transistors 1, 1A, and 1B.
[0081] Figures 5A to 5F are schematic diagrams illustrating the manufacturing method of the vertical junction field-effect transistor (PDFET) of this application. Referring first to Figure 5A, several PDFETs 1 can be manufactured in batches, and then cut along the schematic diagrams of line segments AA' and BB' to form a single PDFET 1. Referring next to Figures 5B to 5F, several PDFETs 1A, 1B, 1C, 1D, and 1E can be manufactured in batches, and then cut along the schematic diagrams of line segments AA' and BB' to form a single PDFET 1A, 1B, 1C, 1D, and 1E.
[0082] In summary, the thickness of the first doped semiconductor structure of the vertical junction field-effect transistor (VJT) of this application is greater than or equal to 50 micrometers and less than or equal to 100 micrometers; and the doping concentration of the first doped semiconductor structure is greater than the doping concentration of the second doped semiconductor structure. Therefore, the VJT exhibits a higher gate-source breakdown voltage. In high-voltage applications, the VJT's channels can effectively control current and prevent device damage.
[0083] Furthermore, the thickness of the protrusions of the vertical junction field-effect transistor (DFET) of this application is greater than 15 micrometers and less than or equal to 50 micrometers, giving the DFET a depletion region with a depth greater than 15 micrometers and less than or equal to 50 micrometers. The deeper depletion region increases the electric field distribution distance within the DFET's channels, preventing excessively large local electric fields from causing DFET breakdown.
[0084] Furthermore, the top of the third doped semiconductor structure of the vertical junction field-effect transistor (VJT) of this application can be flush with the top of the protrusion to form a thicker depletion region. A thicker depletion region can trap a longer conductive channel. Therefore, the VJT exhibits excellent reverse breakdown voltage characteristics, thereby improving its operating range.
[0085] Furthermore, the vertical junction field-effect transistor of this application also includes a first protrusion and a second protrusion, which reduces the etching depth requirement. The thickness is supplemented by the second protrusion, making the total thickness of the first and second protrusions greater than 15 micrometers and less than or equal to 50 micrometers. This reduces the manufacturing difficulty and cost of the vertical junction field-effect transistor.
[0086] Unless otherwise defined, terms such as "substantially" and "approximately" are used to describe and narrate minor changes. When used in the context of an event or situation, these terms may include the exact moment the event or situation occurred, or an approximate point in time from which it occurred. For example, when used in the context of a number, these terms may include a specific range of variation that is less than or equal to that number.
[0087] The foregoing outlines components of several embodiments to enable those skilled in the art to better understand the concepts of the embodiments described herein. Those skilled in the art should understand that the embodiments described herein can be used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or benefits as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this application, and various changes, substitutions, and other options can be made therein without departing from the spirit and scope of this application. Therefore, the scope of protection of this application shall be determined by the appended claims.
Claims
1. A vertical junction field-effect transistor, comprising: First doped semiconductor structure; The second doped semiconductor structure includes a layer and protrusions protruding from the layer, the doping type of the second doped semiconductor structure being the same as that of the first doped semiconductor structure; and a third doped semiconductor structure disposed on both sides of the protrusions and on the layer, the doping type of the third doped semiconductor structure being different from that of the first doped semiconductor structure; wherein the thickness of the protrusions is greater than 15 micrometers and less than or equal to 50 micrometers.
2. The vertical junction field-effect transistor according to claim 1, wherein, The protrusion further includes: a first protrusion body; and a second protrusion body, which is stacked on the first protrusion body, such that the total thickness of the first protrusion body and the second protrusion body is greater than 15 micrometers and less than or equal to 50 micrometers; wherein the crystal form of the first protrusion body and the crystal form of the second protrusion body are different.
3. The vertical junction field-effect transistor according to claim 1, wherein, The protrusion further includes: a first protrusion body; and a second protrusion body, stacked on the first protrusion body, such that the total thickness of the first protrusion body and the second protrusion body is greater than 15 micrometers and less than or equal to 50 micrometers; wherein the first protrusion body is formed by a first deposition process, and the second protrusion body is formed by a second deposition process.
4. The vertical junction field-effect transistor according to claim 1, wherein, The thickness of the third doped semiconductor structure is less than the thickness of the protrusion.
5. The vertical junction field-effect transistor according to claim 1, wherein, The top of the third doped semiconductor structure is flush with the top of the protrusion.
6. The vertical junction field-effect transistor according to claim 5, wherein, The third doped semiconductor structure includes: a first substrate; and an extension protruding from the first substrate; wherein the crystal form of the first substrate and the crystal form of the extension are the same.
7. The vertical junction field-effect transistor according to claim 5, wherein, The third doped semiconductor structure includes: a first substrate; and a second substrate stacked on the first substrate; wherein the crystal forms of the first substrate and the second substrate are different.
8. The vertical junction field-effect transistor according to claim 5, wherein, The third doped semiconductor structure includes: a first substrate; and a second substrate stacked on the first substrate; wherein the first substrate is formed by a doping process and the second substrate is formed by a deposition process.
9. The vertical junction field-effect transistor according to claim 1, wherein, The thickness of the first doped semiconductor structure is greater than or equal to 50 micrometers and less than or equal to 100 micrometers.
10. The vertical junction field-effect transistor according to claim 1, wherein, The doping concentration of the first doped semiconductor structure is greater than that of the second doped semiconductor structure.