Display device

Abstract

The utility model provides a high-precision display device which is provided with a special-shaped display area and is high in occupancy rate of the display area. A display device includes a substrate, a gate line driving circuit, a signal line driving circuit, a plurality of gate lines, and a plurality of video signal lines. The substrate has a display region in which a plurality of pixels are disposed, and a bezel region surrounding the display region, and the display region has a polygonal shape having n vertices. The gate line driving circuit and the signal line driving circuit are located on the bezel area. A plurality of gate lines extend from the gate line driving circuit to the display area. A plurality of image signal lines extend from the signal line driving circuit to the display area and intersect the plurality of gate lines. Each of the plurality of pixels includes a transistor having a first gate electrode, a semiconductor film on the first gate electrode, and a second gate electrode on the semiconductor film. Other features are detailed in the specification.

Description

Technical Field

[0001] One embodiment of this utility model relates to a display device. For example, one embodiment of this utility model relates to a display device that can also be applied to high-resolution small display devices used in VR (virtual reality) goggles, etc. Background Technology

[0002] With the technological advancements in liquid crystal displays (LCDs) and electroluminescent displays in recent years, extremely high-resolution display devices have become available. One application of these high-resolution displays is in VR headsets worn on the user's head. Unlike display devices used in smartphones and television monitors, which have rectangular display areas, VR headsets typically have near-circular display areas to accurately simulate human vision. For example, Patent Documents 1 and 2 disclose display devices with display areas whose outlines are partially curved and octagonal display areas. Non-rectangular display areas are also referred to as irregularly shaped display areas.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2024-7220

[0006] Patent Document 2: Japanese Patent No. 6639866 Utility Model Content

[0007] The technical problem to be solved

[0008] One of the technical problems addressed by one embodiment of this utility model is to provide a display device with a novel structure. Alternatively, one of the technical problems addressed by one embodiment of this invention is to provide a high-resolution display device with an irregularly shaped display area and a high occupancy rate of the display area.

[0009] Means for solving technical problems

[0010] One embodiment of the present invention is a display device. The display device includes a substrate, a gate line driving circuit and a signal line driving circuit, a plurality of gate lines, and a plurality of image signal lines. The substrate has a display area with a plurality of pixels and a border area surrounding the display area, the display area having a polygonal shape with n vertices. The gate line driving circuit and the signal line driving circuit are located on the border area. The plurality of gate lines extend from the gate line driving circuit toward the display area. The plurality of image signal lines extend from the signal line driving circuit toward the display area and intersect with the plurality of gate lines. Each of the plurality of pixels has a transistor, the transistor having a first gate electrode, a semiconductor film on the first gate electrode, and a second gate electrode on the semiconductor film. A portion of the signal line driving circuit is held by the gate line driving circuit and the display area in the direction in which the plurality of gate lines extend. The plurality of gate lines each have a lower gate line and an upper gate line, the lower gate line and the upper gate line overlapping each other, existing in the same layer as the first gate electrode and the second gate electrode, respectively, and electrically connected to the first gate electrode and the second gate electrode, respectively. The lower gate line and the upper gate line of at least one gate line selected from a plurality of gate lines are electrically connected to each other between the display area and a portion of the signal line driving circuit. n is a natural number greater than or equal to 5.

[0011] One embodiment of this utility model is a display device. The display device includes a substrate, a first gate line driving circuit, a second gate line driving circuit, a signal line driving circuit, a plurality of gate lines, and a plurality of image signal lines. The substrate has a display area with a plurality of pixels and a border area surrounding the display area, the display area having a polygonal shape with n vertices. The first and second gate line driving circuits are located on the border area, and the signal line driving circuit sandwiching the display area is also located on the border area. A plurality of gate lines extend from the first gate line driving circuit across the display area toward the second gate line driving circuit. A plurality of image signal lines extend from the signal line driving circuit toward the display area and intersect with the plurality of gate lines. Each of the plurality of pixels has a transistor, the transistor having a first gate electrode, a semiconductor film on the first gate electrode, and a second gate electrode on the semiconductor film. A first portion of the signal line driving circuit is sandwiched between the first gate line driving circuit and the display area in the direction of the extension of the plurality of gate lines. A second portion of the signal line driving circuit is sandwiched between the second gate line driving circuit and the display area in the direction of the extension of the plurality of gate lines. Multiple gate lines each have a lower gate line and an upper gate line, which overlap each other, exist in the same layer as the first gate electrode and the second gate electrode, and are electrically connected to the first gate electrode and the second gate electrode, respectively. The lower gate line and the upper gate line of at least one gate line selected from the multiple gate lines are electrically connected to each other between the display area and the first portion and between the display area and the second portion. n is a natural number greater than or equal to 5. Attached Figure Description

[0012] Figure 1 This is a schematic top view of a display device according to one embodiment of the present invention.

[0013] Figure 2 This is a schematic cross-sectional view of a display device that is one embodiment of the present invention.

[0014] Figure 3 This is a schematic cross-sectional view of a display device that is one embodiment of the present invention.

[0015] Figure 4 This is a schematic cross-sectional view of a display device that is one embodiment of the present invention.

[0016] Figure 5 This is a schematic top view of a display device that is part of one embodiment of the present invention.

[0017] Figure 6 This is a schematic cross-sectional view of a display device that is one embodiment of the present invention.

[0018] Figure 7 This is a schematic cross-sectional view of a display device that is one embodiment of the present invention.

[0019] Figure 8 This is a schematic top view of a display device that is part of one embodiment of the present invention.

[0020] Figure 9 This is a schematic cross-sectional view of a display device that is one embodiment of the present invention.

[0021] Figure 10 This is a schematic top view of a display device that is part of one embodiment of the present invention.

[0022] Figure 11 This is a schematic top view of a display device that is part of one embodiment of the present invention.

[0023] Figure 12 This is a schematic cross-sectional view of a display device that is one embodiment of the present invention.

[0024] Figure 13 This is a schematic top view of a display device that is part of one embodiment of the present invention.

[0025] Figure 14 This is a schematic cross-sectional view of a display device that is one embodiment of the present invention. Detailed Implementation

[0026] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention can be implemented in various ways without departing from its spirit and is not to be construed as limited to the description of the embodiments illustrated below.

[0027] To make the description clearer, the accompanying drawings sometimes schematically represent the width, thickness, shape, etc., of various parts compared to the actual representation; however, this is only an example and does not limit the interpretation of the invention. In this specification and the drawings, elements that have the same function as those described with respect to previously presented figures are sometimes labeled with the same reference numerals, omitting repeated descriptions. These reference numerals are used to generally represent multiple identical or similar structures; when representing them individually, a hyphen and a natural number are added after the reference numerals.

[0028] In this specification and claims, when describing the arrangement of other structures on a certain structure, the use of the word "above" includes, unless otherwise explicitly denied, both the case of arranging other structures directly above a certain structure in connection with it and the case of arranging other structures above a certain structure via other structures.

[0029] In this specification and claims, the expression "a structure is exposed from other structures" means that a portion of a structure is not covered by other structures, and also includes the possibility that the portion not covered by other structures may be further covered by other structures. Furthermore, this expression also includes the possibility that a structure is not in contact with other structures.

[0030] In this invention, when multiple membranes are formed by processing a single membrane, these multiple membranes sometimes have different functions and roles. However, these multiple membranes originate from membranes formed as the same layer in the same process, and have substantially the same layer structure, the same material, and the same morphology. Therefore, they are defined as existing in the same layer.

[0031] The following describes a display device according to one embodiment of the present invention.

[0032] 1. Overall Structure of the Display Device

[0033] Figure 1 A schematic top view showing one embodiment of the display device 100 of the present invention. The display device 100 includes a substrate 102 and Figure 1The opposing substrate is not shown. The substrate 102 is divided into a display area 110 for displaying images and a border area surrounding the display area 110. Various patterned conductive films, semiconductor films, and insulating films formed by photolithography are disposed between the substrate 102 and the opposing substrate. By appropriately combining these conductive films, semiconductor films, and insulating films, multiple pixels (described later) each containing display elements are formed in the display area 110. In addition to driving circuits for driving the pixels, and multiple gate lines 124 and multiple image signal lines 208 for supplying various signals to the pixels from each driving circuit, a series of additional components are also formed. Figure 1 Various scan lines and signal lines not shown.

[0034] The driving circuit includes a gate line driving circuit 170 and a signal line driving circuit 200. Figure 1 In the example shown, two gate line drive circuits 170 are arranged such that they sandwich the display area 110, but a single gate line drive circuit 170 can also be arranged on one side of the display area 110. On the other hand, the signal line drive circuit 200 includes an analog switch 204 and a driver integrated circuit (hereinafter referred to as driver IC) 202 connected to the analog switch 204 via a lead-in wiring 206. The driver IC 202 can be constructed by combining various conductive films, semiconductor films, and insulating films formed on the substrate 102, or an integrated circuit formed on a semiconductor substrate can be formed as the driver IC 202 and mounted on the substrate 102. Power and various signals supplied by an external circuit (not shown) are supplied to the gate line drive circuit 170 and the signal line drive circuit 200, and the gate line drive circuit 170 and the signal line drive circuit 200 generate various control signals for controlling the pixels based on these signals. Each gate line 124 controls each pixel by extending from the gate line drive circuit 170 to the display area 110 and supplying control signals to each pixel. Each gate line 124 can be electrically connected to one gate line driving circuit 170 or to two gate line driving circuits 170 sandwiching the display area 110. Multiple image signal lines 208 extending from the signal line driving circuit 200 also extend into the display area 110 and intersect with the multiple gate lines 124. Control signals are supplied from the signal line driving circuit 200 through the image signal lines 208, thereby supplying image signals required for displaying images to each pixel.

[0035] Here, from Figure 1As can be seen, the display area 110 is not rectangular, but rather an n-sided polygon with five or more vertices. n is a natural number greater than or equal to 4. There is no limit to the maximum value of n; for example, it can be chosen from the range of 8 to 12. Furthermore, the shape of the display area 110 does not necessarily have to be a regular n-sided polygon; it can also be a polygon where at least one side has a different length than any of the other sides. By having such an irregularly shaped display area, the display area 110 can achieve a display closer to a circle, thus making the display device 100 suitable for head-mounted VR goggles, etc. Additionally, the substrate 102 can be rectangular, or it can also be an m-sided polygon with five or more vertices, similar to the display area 110. m is a natural number greater than or equal to 5, and its maximum value can also be chosen from, for example, the range of 8 to 12. The vertices of the display area 110 do not necessarily have to be formed by the intersection of two straight lines; they can also have rounded corners. Similarly, the vertices of the substrate 102 can also be chamfered. By having an irregular shape for the substrate 102, the display device 100 can be miniaturized as a whole, thus enabling its suitable use in head-mounted VR goggles and the like. Furthermore, by having an irregular shape that matches the display area 110, the area occupied by the display area 110 relative to the overall area of ​​the display device 100 can be increased, allowing for the miniaturization of VR goggles while achieving large-scale images. As a result, VR goggles capable of reproducing a more realistic field of vision can be provided.

[0036] Because the display area 110 has an irregular shape, the gate line drive circuit 170 is bent along the contour of the display area 110. Figure 1 In the example shown, each gate line drive circuit 170 is configured with two bend points. Similarly, the signal line drive circuit 200 also bends along the contour of the display area 110. Figure 1 In the example shown, a portion of the signal line driving circuit 200, such as analog switch 204, is configured to have two bends. Additionally, a portion of the signal line driving circuit 200 is located between the gate line driving circuit 170 and the display area 110 in the direction in which the gate line 124 extends. Figure 1 In the example shown, in the direction in which the gate line 124 extends, a portion of the signal line driving circuit 200 is located between the display area 110 and another gate line driving circuit 170, another portion is located between the display area 110 and one gate line driving circuit 170, and the remaining portion is configured in a position not sandwiched by the two gate line driving circuits 170. The above configurations will be described in detail below.

[0037] (1) Substrate and opposing substrate

[0038] Figure 2 Indicates along Figure 1A schematic cross-sectional view of the dashed line AA′. Figure 2 The diagram shows a schematic cross-sectional view of a gate line driving circuit 170 and a pixel disposed in the display area 110, each having a liquid crystal element as a display element. Furthermore, when using a liquid crystal element as the display element, a backlight (not shown) is provided. Known light sources (e.g., cold cathode tubes, light-emitting diodes, etc.) can be appropriately used as the backlight, therefore, description is omitted.

[0039] The substrate 102 and the opposing substrate 104 are configured to face each other, providing physical strength to the display device 100 and allowing visible light emitted from a backlight (not shown) to pass through. For example, substrates with light transmittance, such as glass substrates or quartz substrates, are used as the substrate 102 and the opposing substrate 104. The substrate 102 and the opposing substrate 104 may also comprise light-transmitting polymers such as polyimide, polyamide, polycarbonate, acrylic resin, and polysiloxane. At least one of the substrate 102 and the opposing substrate 104 may be malleable.

[0040] (2) Drive circuit

[0041] At least a portion of the gate line driving circuit 170 and the signal line driving circuit 200 are formed by appropriately combining various patterned conductive films, semiconductor films, and insulating films disposed on the substrate 102. The configuration of these driving circuits is not limited; multiple transistors, capacitors, etc., can be used to construct the gate line driving circuit 170 and the signal line driving circuit 200. Figure 1 In the example shown, two transistors 172 and 174 are shown as components that constitute the gate line drive circuit 170.

[0042] Specifically, transistors 172 and 174 are disposed directly on the substrate 102 in the border region 112, or disposed on the bottom cover layer 106, which is of arbitrary configuration. The configuration of transistors 172 and 174 is not limited, as long as known structures are appropriately applied. Figure 2In the example shown, transistors 172 and 174 each have a semiconductor film 176, a first insulating film 178 on the semiconductor film 176, a gate electrode 180 located on the first insulating film 178 and overlapping the semiconductor film 176, a second insulating film 182 and a third insulating film 184 covering the gate electrode 180, and terminals 188 and 190 electrically connected to the semiconductor film 176 via openings provided in the second insulating film 182 and the third insulating film 184. Wiring 192 for providing signals from external circuits to transistors 172 and 174 is connected to terminals 188 and 190. The first insulating film 178 functions as the gate insulating film of transistors 172 and 174. Terminals 190 of transistor 172 and 188 of transistor 174 are integrated, thereby electrically connecting transistors 172 and 174. The material constituting the semiconductor film 176 is not limited and can be an oxide containing elements of group 14 such as silicon, or an oxide containing elements of group 13 such as gallium and indium. When the semiconductor film 176 contains silicon, its crystallinity is not limited; the semiconductor film 176 can be either amorphous or polycrystalline. For example, by forming the semiconductor film 176 from polycrystalline silicon, a drive circuit capable of high-speed operation can be formed.

[0043] (3) pixels

[0044] Each pixel is composed of a display element 150 and a pixel circuit for operating the display element 150 based on control signals supplied from the gate line driving circuit 170 and the signal line driving circuit 200. The configuration of the pixel circuit is not limited; it can be formed by appropriately combining one or more transistors, one or more capacitors, etc. The configuration of the display element 150 and / or the display mechanism is also not limited. Therefore, the display element 150 can be a liquid crystal element or an electroluminescent element. Figure 2 The example shown illustrates a driving transistor 122 electrically connected to the display element 150, and a liquid crystal element that functions as the display element 150.

[0045] The driving transistor 122 includes a first gate electrode 124-1a disposed on a first insulating film 178, a second insulating film 182 covering the first gate electrode 124-1a, a semiconductor film 126 disposed on the second insulating film 182 and overlapping the first gate electrode 124-1a, a third insulating film 184 disposed on the semiconductor film 126, a second gate electrode 124-2a disposed on the third insulating film 184 and overlapping the first gate electrode 124-1a and the semiconductor film 126, a fourth insulating film 186 covering the second gate electrode 124-2a, a terminal 128 electrically connected to the semiconductor film 126 through an opening disposed on the fourth insulating film 186, a fifth insulating film 132 disposed on the terminal 128 and the fourth insulating film 186, and a terminal 130 electrically connected to the semiconductor film 126 through openings disposed on the fourth insulating film 186 and the fifth insulating film 132, etc. The first gate electrode 124-1a and the gate electrode 180 exist in the same layer, and the second gate electrode 124-2a exists in the same layer as the terminals 188 and 190. Furthermore, the first gate electrode 124-1a and the second gate electrode 124-2a constitute part of the gate line 124. As described later, the first gate electrode 124-1a and the second gate electrode 124-2a are electrically connected and have the same potential. The second insulating film 182 and the third insulating film 184 are shared with the transistors 172 and 174 of the gate line driving circuit 170, and both function as gate insulating films for driving transistor 122. Terminal 130 is electrically connected to the display element 150. Therefore, the image signal input from the signal line driving circuit 200 to the terminal 128 via the image signal line 208 is input to the display element 150 via the semiconductor film 126 and the terminal 130 when the driving transistor 122 is turned on.

[0046] The material contained in the semiconductor film 126 is not limited, and examples include group 14 elements such as silicon. In this case, the crystallinity of the semiconductor film 126 is also not limited; the semiconductor film 126 can be amorphous or polycrystalline.

[0047] Alternatively, the semiconductor film 126 may also comprise an oxide semiconductor containing group 13 elements such as gallium and indium. Oxide semiconductors can contain multiple different group 13 elements; for example, indium gallium oxide (IGO) can be shown. Oxide semiconductors may also contain group 12 elements. Indium gallium zinc oxide (IGZO) is a typical example of an oxide semiconductor containing group 12 elements. The semiconductor film 126 may also contain other elements, such as group 14 elements like tin, or group 4 elements like titanium and zirconium.

[0048] A planarization film 142 is disposed on the gate line driving circuit 170 and the pixel circuit including the driving transistor 122. A sixth insulating film 134 may also be disposed below the planarization film 142. By disposing of the planarization film 142, the unevenness caused by the transistors 172, 174, and the driving transistor 122 is absorbed, enabling the formation of a flat surface. Furthermore, Figure 2 The display area 110 shown has a structure known as a color filter on array, in which a color filter 140 is disposed between the display element 150 and the substrate 102 (specifically, between the planarization film 142 and the fifth insulating film 132 (or between the planarization film 142 and the sixth insulating film 134)).

[0049] The aforementioned components forming the driving circuit and pixel circuit can be formed using known materials, therefore detailed descriptions are omitted. In short, the bottom cover layer 106, the first insulating film 178, the second insulating film 182, the third insulating film 184, the fourth insulating film 186, the fifth insulating film 132, and the sixth insulating film 134 can all be formed from one or more films containing silicon-containing inorganic compounds such as silicon oxide and silicon nitride. The gate electrode 180, terminals 188 and 190, the first gate electrode 124-1a, the second gate electrode 124-2a, and the terminal 128 can all be formed from metals such as titanium, molybdenum, tungsten, and copper, or alloys containing one or more of these metals. The terminal 130, the pixel electrode 152 (described later), and the common electrode 158 can be formed from, for example, a transparent conductive film such as an indium tin oxide (ITO) film. The planarization film 142 can be formed from polymers such as acrylic resin, epoxy resin, silicone resin, and polyimide resin. The color filter 140 can be composed of the aforementioned polymers and pigments.

[0050] When the display element 150 is a liquid crystal element, such as Figure 2 As shown, the structure comprises a pixel electrode 152 electrically connected to the driving transistor 122, a common electrode 158 on the pixel electrode 152, an inter-electrode insulating film 154 located between the pixel electrode 152 and the common electrode 158 and insulating the pixel electrode 152 from the common electrode 158, a first alignment film 160 and a second alignment film 164 on the pixel electrode 152, and a liquid crystal layer 162 between the first alignment film 160 and the second alignment film 164. Alternatively, an auxiliary wiring 156 for preventing voltage drop at the common electrode 158 may be provided below or above the common electrode 158.

[0051] Substrate 102 and opposing substrate 104 are fixed together by sealing material 146, and liquid crystal layer 162 is filled in the space formed by sealing material 146, substrate 102, and opposing substrate 104. Liquid crystal layer 162 may be provided with spacers 144 for maintaining the thickness of liquid crystal layer 162. Spacers 144 may be as follows: Figure 2 Although not shown, the liquid crystal layer 162 can also be formed in a columnar shape, but spherical spacers can also be dispersed within it. As an optional configuration, an outer cover layer 108 that contacts the opposing substrate 104 can also be provided. The outer cover layer 108 can be formed of one or more films containing a silicon-containing inorganic compound.

[0052] Figure 2 The liquid crystal element shown is a so-called IPS (In-Plane Switching) type liquid crystal element, but the driving method of the display element is not limited. The liquid crystal element can also be a TN (Twisted Nematic) type liquid crystal element or a VA (Vertical Alignment) type liquid crystal element. The components forming the liquid crystal element can also use well-known structures, so the description is omitted.

[0053] Alternatively, the color filter can be disposed on the opposing substrate 104 side instead of on the substrate 102 side. Specifically, as follows: Figure 3 As shown, the color filter 140 is disposed in contact with the opposing substrate 104, and an outer cover layer 108 is formed to cover the color filter 140.

[0054] Alternatively, the display element 150 can also be an electroluminescent element. In this case, such as Figure 4 As shown, an insulating partition wall 136 is provided to cover the end of the pixel electrode 152 and the opening in the planarization film 142, etc., for connecting the pixel electrode 152 to the terminal 130. This is achieved simply by forming an electroluminescent layer 168 between the pixel electrode 152 and the common electrode 158. The configuration of the electroluminescent layer 168 can be arbitrarily determined; it can be formed by appropriately combining functional layers such as a charge injection layer, a charge transport layer, a charge blocking layer, a light-emitting layer, and an exciton blocking layer. Furthermore, the electroluminescent element can be either bottom-emitting or top-emitting. A sealing material 146, which also functions as a protective film, is provided between the common electrode 158 and the opposing substrate 104. Examples of the sealing material 146 include layers containing silicon-containing inorganic compounds such as silicon nitride, layers containing resins such as acrylic resin and epoxy resin, or laminates thereof.

[0055] 2. Gate wire construction

[0056] Figure 5 A schematic top view showing a portion of the display device 100. Figure 5 The image shows a pair of gate line drive circuits 170 disposed in a border region 112 and a plurality of pixels 120 electrically connected to them. The pixels 120 are arranged in a manner that forms a plurality of rows and columns. Figure 5 In the example shown, a power supply method known as a single-sided power supply is employed. Multiple gate lines 124 are configured to extend from either of a pair of gate line drive circuits 170 along the row direction and traverse the display area 110, without being connected to the other gate line drive circuit. The power supply direction is switched per row. Therefore, when a gate line 124 is connected to one gate line drive circuit 170 and receives a gate signal as one of the control signals from that gate line drive circuit 170, the gate lines 124 adjacent to that gate line 124 in the column direction are all connected to the other gate drive circuit 170 and supplied with gate signals.

[0057] Here, each gate line 124 exists in a different layer, consisting of a lower gate line and an upper gate line in two layers that overlap each other in the normal direction of the substrate 102. Specifically, as included along... Figure 5 A schematic diagram of the cross-sections of the dashed lines BB′ and CC′. Figure 6 As shown, each gate line 124 is composed of a lower gate line 124-1 and an upper gate line 124-2. Both the lower gate line 124-1 and the upper gate line 124-2 span the display area 110 and are electrically connected to the first gate electrode 124-1a and the second gate electrode 124-2a, respectively. In other words, the first gate electrode 124-1a and the lower gate line 124-1 exist in the same layer, and the first gate electrode 124-1a constitutes a part of the lower gate line 124-1. Similarly, the second gate electrode 124-2a and the upper gate line 124-2 exist in the same layer, and the second gate electrode 124-2a constitutes a part of the upper gate line 124-2.

[0058] Furthermore, the lower gate line 124-1 and the upper gate line 124-2 are electrically connected to each other in the bezel region 112. More specifically, the lower gate line 124-1 and the upper gate line 124-2 are electrically connected in the bezel region 112 on the side where the gate line driving circuit 170 connected to the gate line 124 is located, and in the bezel region 112 on the opposite side of the display region 110 relative to the gate line driving circuit 170. Therefore, the first gate electrode 124-1a and the second gate electrode 124-2a are electrically connected and are at the same potential. The electrical connection between the lower gate line 124-1 and the upper gate line 124-2 is via an insulating film formed between them (in... Figure 6 In the example shown, the openings in the second insulating film 182 and the third insulating film 184 are used. Figure 6The example shown employs a single-sided power supply. Therefore, considering two adjacent gate lines 124 in the column direction, one gate line 124 receives a gate signal from a gate line drive circuit 170 and electrically connects the lower gate line 124-1 to the upper gate line 124-2 relative to the bezel regions 112 on both sides of the display area 110. On the other hand, as included along... Figure 5 A schematic diagram of the cross-sections of the dashed lines DD′ and EE′. Figure 7 As shown, another gate line 124 receives the gate signal from another gate line driving circuit 170 and electrically connects the lower gate line 124-1 and the upper gate line 124-2 on the side bezel regions 112 relative to the display area 110.

[0059] Furthermore, the lower gate line 124-1 is discontinuous in the bezel region 112 from the display region 110 to the gate line driving circuit 170, and is divided into two segment wirings (see reference). Figure 6 BB' end face Figure 7 (EE' end face). A section of wiring (in Figure 6 The lower gate line 124-1 on the left side of the BB' cross-section is connected to the gate line drive circuit 170, and another section of wiring (in Figure 6 The two cross-sectional views show the lower gate line 124-1 traversing the display area 110. The two segment wirings are electrically connected via the upper gate line 124-2. The electrical connection between the two segment wirings and the upper gate line 124-2 is also via an insulating film formed between them. Figure 6 and Figure 7 In the example shown, the openings in the second insulating film 182 and the third insulating film 184 are used to perform this.

[0060] Thus, in the display device 100, the gate line 124 is branched into a lower gate line 124-1 and an upper gate line 124-2 in the bezel region 112, and the branched lower gate line 124-1 and upper gate line 124-2 are used to supply gate signals. Furthermore, the connection between the lower gate line 124-1 and the upper gate line 124-2 is made at two points sandwiching the display region 110. By adopting this configuration, a large cross-sectional area of ​​the gate line 124 can be ensured within the display region 110. Therefore, the resistance of the gate line 124 is reduced, and the increase of the time constant can be prevented. As a result, gate signal delay can be prevented. In addition, by dividing the lower gate line 124-1 into two segment wirings, the pixel circuit provided in the display region 110 can be isolated from the gate line driving circuit 170 before the formation of the upper gate line 124-2. Therefore, when the display device 100 is charged during manufacturing, the probability of electrostatic damage to the pixel circuit due to discharge to the gate line drive circuit 170 can be greatly reduced.

[0061] In the display device 100, a dual-side power supply method can also be used instead of a single-side power supply method. In this case, such as Figure 8 As shown, each gate line 124 is connected to a pair of gate line driving circuits 170 arranged to sandwich the display area 110, and receives gate signals from the pair of gate line driving circuits 170. In this configuration, the gate line 124 is also composed of a lower gate line 124-1 and an upper gate line 124-2, which are electrically connected to each other in the bezel area 112. More specifically, as included along... Figure 8 A schematic diagram of the cross-sections of the dashed lines FF′ and GG′. Figure 9 As shown, within the bezel region 112, sandwiching the display region 110, the gate line 124 branches into a lower gate line 124-1 and an upper gate line 124-2, both of which traverse the display region 110. The electrical connection between the lower gate line 124-1 and the upper gate line 124-2 is via an insulating film formed between them. Figure 9 In the example shown, the openings in the second insulating film 182 and the third insulating film 184 are used.

[0062] Additionally, the lower gate line 124-1 is cut off in the bezel region 112. That is, the lower gate line 124-1 is divided into a first segment wiring that traverses the display region 110. Figure 9 The lower gate line 124-1 shown in the two cross-sectional views), and the second section wiring located between the first section wiring and a gate line driving circuit 170 and connected to the gate line driving circuit 170 ( Figure 9 The lower gate line 124-1 on the left side appears in the FF' cross-sectional view, and the third section wiring is located between the first section wiring and another gate line driving circuit 170 and connected to the other gate line driving circuit 170. Figure 9 The lower gate line 124-1 on the right side appears in the GG' cross-sectional view. The first and second segment wirings are electrically connected via the upper gate line 124-2, and similarly, the first and third segment wirings are also electrically connected via the upper gate line 124-2. The electrical connections between the first and second segment wirings, as well as between the first and third segment wirings, are also via an insulating film formed between them (in... Figure 9 In the example shown, the openings in the second insulating film 182 and the third insulating film 184 are used to perform this.

[0063] 3. Relationship between gate wiring connections and image signal lines

[0064] As described above, in the display device 100, the shapes of the substrate 102 and the opposing substrate 104 can be set in a manner suitable for the shape of the display area 110. Therefore, for example, by cutting off the corners of the substrate 102 and the opposing substrate 104 on the side where the signal line driving circuit 200 is provided, it is possible to provide a display device with a shape closer to a circle, and also to provide a display device with a high occupancy rate of the display area 110. However, with such a shape, it is difficult to arrange the gate line driving circuit 170 in a straight line, such as... Figure 1 As shown, a portion of the gate line driving circuit 170 is configured to be bent. Additionally, a portion of the signal line driving circuit 200, such as the analog switch 204, is also configured to be bent to fit the shape of the substrate 102 and the display area 110. Therefore, by configuring a portion of the signal line driving circuit 200, such as the analog switch 204, to be sandwiched between the display area 110 and the gate line driving circuit 170 in the direction in which the gate line 124 extends, miniaturization of the display device 100 can be achieved.

[0065] With such a configuration, such as Figure 10 As schematically shown, in the border region 112-1 between the display area 110 and the gate line driving circuit 170, where a portion of the signal line driving circuit 200 is not present, the connection between the lower gate line 124-1 and the upper gate line 124-2, including segment wiring, can be arbitrarily configured regardless of the configuration of the image signal lines 208 formed above the gate lines 124. On the other hand, in the border region 112-2 between the display area 110 and the gate line driving circuit 170, where a portion of the signal line driving circuit 200 is present, the lower gate line 124-1 and the upper gate line 124-2 are connected in the area where the image signal lines 208 are configured. Therefore, when the image signal lines 208 are arranged with a small pitch and high density, if alignment deviations occur during the photolithography process in manufacturing the display device 100, short circuits or cut-offs may sometimes occur between the image signal lines 208.

[0066] Therefore, in the border region 112-1, as Figure 11 A schematic top view and a schematic diagram of the cross-section along the dashed line HH′. Figure 12As shown, the connection between the lower gate line 124-1 and the upper gate line 124-2 is made at the location overlapping with the image signal line 208. In other words, the opening 114 provided in the plurality of insulating films (e.g., the second insulating film 182 and the third insulating film 184) for the electrical connection between the lower gate line 124-1 and the upper gate line 124-2 is formed such that its entirety overlaps with one image signal line 208. Alternatively, if the lower gate line 124-1 and the upper gate line 124-2 are in direct contact in the opening 114, the electrical connection between the lower gate line 124-1 and the upper gate line 124-2 is made such that their entire contact surface overlaps with one image signal line 208. Therefore, the opening 114 does not overlap with the area between adjacent image signal lines 208. By adopting such a configuration, even if the opening 114 is offset, the image signal lines 208 that do not overlap with the opening 114 will not be affected, thus preventing short circuits between adjacent image signal lines 208. For example, if the opening 114 is formed near an image signal line 208 that overlaps with the opening 114 due to alignment deviations, processing shape deviations, etc., the shape of the resist used to form the image signal line 208 may sometimes be abnormal. If such an abnormality occurs, it is difficult to perform the intended patterning, and adjacent image signal lines 208 may sometimes short-circuit with each other. Furthermore, if the image signal line 208 is not formed in a way that completely covers the opening 114, sometimes a portion of the image signal line 208 that overlaps with the opening 114 may not be formed with sufficient width, or a break may occur due to the opening 114. However, by forming the opening 114 as a whole that overlaps with an image signal line 208, such undesirable conditions can be prevented even when the image signal lines 208 are arranged at a high density.

[0067] Furthermore, when the spacing and density of the image signal lines 208 are large, it is sufficient to form an opening 114 between adjacent image signal lines 208 to electrically connect the lower gate line 124-1 to the upper gate line 124-2. Specifically, as follows: Figure 13 A schematic diagram of the cross-section along its dashed line JJ′. Figure 14 As shown, the opening 114 is formed so that it exposes from the plurality of image signal lines 208. In other words, the lower gate line 124-1 and the upper gate line 124-2 are electrically connected such that the entire contact surface of the lower gate line 124-1 and the upper gate line 124-2 does not overlap with any of the image signal lines 208. By adopting such a configuration, even if the opening 114 is offset, the interruption of the image signal lines 208 can be prevented.

[0068] As described above, in the display device 100 of one embodiment of the present invention, the gate line driving circuit 170 and the signal line driving circuit 200 can be bent to match the irregularly shaped display area 110, and a portion of the signal line driving circuit 200 is disposed between the gate line driving circuit 170 and the display area 110. This allows for miniaturization of the substrate 102 and the opposing substrate 104, thus providing a miniaturized display device with a high occupancy rate of the display area 110. Furthermore, the gate line 124 branches into a lower gate line 124-1 and an upper gate line 124-2 in the border region 112. Both the lower gate line 124-1 and the upper gate line 124-2 span the display area 110 and are electrically connected to each other in the border regions 112 on both sides of the display area 110. Therefore, it is possible to prevent an increase in the wiring resistance of the gate line 124, and even if the number of pixels 120 in each row increases, it is possible to prevent an increase in the resistance of the gate line 124 and the resulting increase in the time constant. Because of these characteristics, by applying the embodiments of the present invention, a small display device with a high pixel count, i.e., high precision, can be provided. Furthermore, the openings 114 for the electrical connection between the lower gate line 124-1 and the upper gate line 124-2 are respectively configured to either completely overlap with an image signal line 208, or completely expose themselves from adjacent image signal lines 208. Therefore, the impact on the image signal lines 208 caused by alignment deviations during the formation of the openings 114 can be mitigated, and even with a high-density arrangement of the image signal lines 208, short circuits and cuts in the image signal lines 208 can be prevented. It can be said that such features also contribute to the high precision and improved yield of the display device.

[0069] As embodiments of the present invention, the above-described embodiments can be appropriately combined and implemented as long as they do not contradict each other. Furthermore, solutions obtained by adding, deleting, or modifying constituent elements, or by adding, omitting, or changing processes or conditions, based on the embodiments, are also included within the scope of the present invention, provided they possess the spirit of the present invention.

[0070] Even if other effects are different from those brought about by the various embodiments described above, the effects that are clearly defined according to the description in this specification, or the effects that can be easily predicted by those skilled in the art, are of course understood to be effects brought about by the present invention.

[0071] Explanation of reference numerals in the attached figures

[0072] 100: Display device; 102: Substrate; 104: Opposing substrate; 106: Bottom cover layer; 108: Outer cover layer; 110: Display area; 112: Bezel area; 112-1: Bezel area; 112-2: Bezel area; 114: Opening; 120: Pixel; 122: Driving transistor; 124: Gate line; 124-1: Lower gate line; 124-1a: First gate electrode; 124-2: Upper gate line; 124-2a: Second gate electrode; 126: Semiconductor film; 128: Terminal; 130: Terminal; 132: Fifth insulating film; 134: Sixth insulating film; 136: Separator; 140: Color filter; 142: Planarization film; 144: Spacer; 14 6: Sealing material; 150: Display element; 152: Pixel electrode; 154: Inter-electrode insulating film; 156: Auxiliary wiring; 158: Common electrode; 160: First alignment film; 162: Liquid crystal layer; 164: Second alignment film; 168: Electroluminescent layer; 170: Gate line driving circuit; 172: Transistor; 174: Transistor; 176: Semiconductor film; 178: First insulating film; 180: Gate electrode; 182: Second insulating film; 184: Third insulating film; 186: Fourth insulating film; 188: Terminal; 190: Terminal; 192: Wiring; 200: Signal line driving circuit; 202: Driver IC; 204: Analog switch; 206: Lead-in wiring; 208: Image signal line.

Claims

1. A display device, characterized in that, have: The substrate has a display area configured with multiple pixels and a border area surrounding the display area, the display area having a polygonal shape with n vertices, where n is a natural number of 4 or more. The gate line driving circuit and signal line driving circuit on the frame area; A plurality of gate lines extending from the gate line driving circuit to the display area; as well as Multiple image signal lines extend from the signal line driving circuit to the display area and intersect with the multiple gate lines. Each of the plurality of pixels has a transistor, and the transistor has a first gate electrode, a semiconductor film on the first gate electrode, and a second gate electrode on the semiconductor film. A portion of the signal line driving circuit is sandwiched between the gate line driving circuit and the display area in the direction in which the plurality of gate lines extend. The plurality of gate lines each have a lower gate line and an upper gate line, the lower gate line and the upper gate line overlap each other, exist in the same layer as the first gate electrode and the second gate electrode respectively, and are electrically connected to the first gate electrode and the second gate electrode respectively. The lower gate line and the upper gate line of at least one gate line selected from the plurality of gate lines are electrically connected to each other between the display area and the portion of the signal line driving circuit.

2. The display device according to claim 1, characterized in that, The contact surface between the lower gate line and the upper gate line overlaps with one of the plurality of image signal lines.

3. The display device according to claim 1, characterized in that, The contact surface between the lower gate line and the upper gate line is exposed from the plurality of image signal lines.

4. The display device according to claim 1, characterized in that, The lower gate line of the at least one gate line is divided into two segment wirings between the display area and the portion of the signal line driving circuit. The two segment wirings are electrically connected to each other via the upper gate line between the display area and the portion of the signal line driving circuit.

5. The display device according to claim 4, characterized in that, The contact surface between the segment wiring and the upper gate line overlaps with one of the plurality of image signal lines.

6. The display device according to claim 4, characterized in that, The contact surface between the segment wiring and the upper gate line is exposed from the plurality of image signal lines.

7. The display device according to claim 1, characterized in that, The lower gate line and the upper gate line of the at least one gate line are also electrically connected to each other on the bezel region opposite to the gate line driving circuit, between the display area and the portion of the signal line driving circuit.

8. The display device according to claim 1, characterized in that, The portion of the signal line drive circuit includes an analog switch.

9. The display device according to claim 1, characterized in that, The gate line driving circuit bends along the contour of the display area.

10. The display device according to claim 1, characterized in that, The substrate has a polygonal shape with m vertices, where m is a natural number greater than or equal to 5.

11. A display device, characterized in that, have: The substrate has a display area configured with multiple pixels and a border area surrounding the display area, the display area having a polygonal shape with n vertices, where n is a natural number of 4 or more. A first gate line driving circuit and a second gate line driving circuit located on the border area and clamping the display area; The signal line driving circuit on the border area; Multiple gate lines extend from the first gate line driving circuit across the display area toward the second gate line driving circuit; as well as Multiple image signal lines extend from the signal line driving circuit to the display area and intersect with the multiple gate lines. Each of the plurality of pixels has a transistor, the transistor having a first gate electrode, a semiconductor film on the first gate electrode, and a second gate electrode on the semiconductor film. The first part of the signal line driving circuit is sandwiched between the first gate line driving circuit and the display area in the direction in which the plurality of gate lines extend. The second part of the signal line driving circuit is sandwiched between the second gate line driving circuit and the display area in the direction in which the plurality of gate lines extend. The plurality of gate lines each have a lower gate line and an upper gate line, the lower gate line and the upper gate line overlap each other, exist in the same layer as the first gate electrode and the second gate electrode respectively, and are electrically connected to the first gate electrode and the second gate electrode respectively. The lower gate line and the upper gate line of at least one gate line selected from the plurality of gate lines are electrically connected to each other between the display area and the first portion and between the display area and the second portion.

12. The display device according to claim 11, characterized in that, The contact surface between the lower gate line and the upper gate line overlaps with one of the plurality of image signal lines.

13. The display device according to claim 11, characterized in that, The contact surface between the lower gate line and the upper gate line is exposed from the plurality of image signal lines.

14. The display device according to claim 11, characterized in that, The lower gate line of the at least one gate line is divided into a first segment wiring that traverses the display area, a second segment wiring between the first segment wiring and the first gate line driving circuit, and a third segment wiring between the first segment wiring and the second gate line driving circuit. The second segment wiring and the third segment wiring are respectively between the display area and the first part, and between the display area and the second part, and are electrically connected to the first segment wiring via the upper gate line.

15. The display device according to claim 14, characterized in that, The contact surface between the second segment wiring and the upper gate line overlaps with one of the plurality of image signal lines.

16. The display device according to claim 14, characterized in that, The contact surface between the second segment wiring and the upper gate line is exposed from the plurality of image signal lines.

17. The display device according to claim 14, characterized in that, The contact surface between the third segment wiring and the upper gate line overlaps with one of the plurality of image signal lines.

18. The display device according to claim 14, characterized in that, The contact surface between the third segment wiring and the upper gate line is exposed from the plurality of image signal lines.

19. The display device according to claim 11, characterized in that, The first and second parts include analog switches.

20. The display device according to claim 11, characterized in that, The first gate line driving circuit and the second gate line driving circuit are curved along the contour of the display area.

Images