Display substrate, display panel and display device

Abstract

The utility model discloses a display substrate, a display panel and a display device, relates to the technical field of display, and can improve the problem of film breakage so as to improve the stability of a TFT (Thin Film Transistor) structure. The display substrate comprises a substrate layer, a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer and a second insulating layer, the second conductive layer comprises a first electrode, a second electrode and a third electrode, the first insulating layer comprises a first via hole, the second insulating layer comprises a second via hole and a third via hole, the first electrode is electrically connected with one end of the semiconductor layer through the second via hole, and the first electrode is electrically connected with the electrode signal line through the first via hole; the second electrode is electrically connected with the other end of the semiconductor layer through the third via hole; the second insulating layer comprises a gate insulating structure, the gate insulating structure is located between the second via hole and the third via hole, the gate insulating structure comprises a first structure part, a second structure part and a third structure part, and the orthographic projection of the third structure part on the substrate layer completely covers the orthographic projection of the third electrode.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display substrate, display panel and display device. Background Technology

[0002] Currently, with the continuous development of display technology, the consumer market has increasingly higher requirements for the performance of display products.

[0003] However, in the manufacturing process of display products, after the organic insulating layer above the semiconductor layer is etched and other film layers are covered, the film layer covered on the etched organic insulating layer is prone to film breakage due to the etching step difference. Film breakage can lead to gate oxidation, negative bias or conductor of TFT (Thin Film Transistor) characteristics, making the semiconductor device unable to pass the reliability test.

[0004] In summary, how to avoid membrane breakage is an urgent problem to be solved. Utility Model Content

[0005] The present application provides a display substrate, display panel, and display device that can improve the problem of film layer breakage and thus enhance the stability of the TFT structure.

[0006] A first aspect of this application provides a display substrate, comprising:

[0007] The system comprises a substrate layer, a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, and a second insulating layer. The first conductive layer is disposed between the substrate layer and the semiconductor layer, the semiconductor layer is disposed between the first conductive layer and the second conductive layer, the first insulating layer is disposed between the first conductive layer and the semiconductor layer, and the second insulating layer is disposed between the semiconductor layer and the second conductive layer.

[0008] The first conductive layer includes an electrode signal line, the second conductive layer includes a first electrode, a second electrode, and a third electrode, the first insulating layer includes a first via, the second insulating layer includes a second via and a third via, the first electrode is electrically connected to one end of the semiconductor layer through the second via, the first electrode is electrically connected to the electrode signal line through the first via, the second electrode is electrically connected to the other end of the semiconductor layer through the third via, and the orthogonal projection of the third electrode on the substrate layer is located between the orthogonal projections of the second via and the third via on the substrate layer;

[0009] The second insulating layer includes a gate insulating structure located between the second via and the third via. The gate insulating structure includes a first structural portion, a second structural portion, and a third structural portion. The third structural portion is connected between the first structural portion and the second structural portion. The orthogonal projections of the first structural portion and the second structural portion on the substrate do not overlap with the orthogonal projection of the third electrode on the substrate. The orthogonal projection of the third structural portion on the substrate completely covers the orthogonal projection of the third electrode on the substrate. The orthogonal projection of the semiconductor layer on the substrate completely covers the orthogonal projection of the gate insulating structure on the substrate.

[0010] In some embodiments, the first conductive layer includes a light-shielding structure;

[0011] The orthogonal projection of the semiconductor layer onto the substrate completely covers the orthogonal projection of the light-shielding structure onto the substrate; and / or

[0012] The orthographic projection of the light-shielding structure onto the substrate overlaps with the orthographic projection of the third electrode onto the substrate; and / or

[0013] The orthographic projection of the light-shielding structure on the substrate layer covers the orthographic projection of the first structural portion on the substrate layer, or the orthographic projection of the light-shielding structure on the substrate layer does not overlap with the orthographic projection of the first structural portion on the substrate layer; and / or

[0014] The orthographic projection of the light-shielding structure on the substrate overlaps with the orthographic projection of the second structural portion on the substrate; and / or

[0015] The orthographic projection of the light-shielding structure on the substrate overlaps with the orthographic projection of the third structural part on the substrate.

[0016] In some embodiments, the light-shielding structure is electrically connected to the third electrode.

[0017] In some embodiments, the light-shielding structure includes a fourth structural portion, a fifth structural portion, and a sixth structural portion, wherein the sixth structural portion is connected between the fourth structural portion and the fifth structural portion;

[0018] The orthographic projection of the sixth structural portion on the substrate layer coincides with the orthographic projection of the gate insulating structure on the substrate layer, while the orthographic projections of the fourth and fifth structural portions on the substrate layer do not overlap with the orthographic projection of the gate insulating portion on the substrate layer.

[0019] In some embodiments, the dimension of the first structural portion in the first direction is greater than or equal to 1 μm; and / or

[0020] The second structural part has a dimension greater than or equal to 1 μm in the first direction;

[0021] Wherein, the first direction is parallel to the plane where the semiconductor layer is located, and the first direction is the direction of the line connecting the first electrode and the second electrode.

[0022] In some embodiments, the first structural portion is connected to the first electrode, and the first electrode covers at least a portion of the edge of the first structural portion near the first electrode; the second structural portion is connected to the second electrode, and the second electrode covers at least a portion of the edge of the second structural portion near the second electrode.

[0023] The second insulating layer includes a first insulating structure and a second insulating structure. The first insulating structure is located on the edge of the second via away from the third electrode, and the second insulating structure is located on the edge of the third via away from the third electrode. The first direction is parallel to the plane of the semiconductor layer, and the first direction is the direction of the line connecting the first electrode and the second electrode.

[0024] The first electrode covers at least a portion of the edge of the first insulating structure, and / or the second electrode covers at least a portion of the edge of the second insulating structure.

[0025] In some embodiments, the size of the first electrode covering the first insulating structure in the first direction is less than or equal to 0.6 μm, and / or, the size of the first electrode covering the first structural portion in the first direction is less than or equal to 0.6 μm; and / or,

[0026] The second electrode covers the second insulating structure by a size of 0.6 μm or less in the first direction, and / or the second electrode covers the second structural portion by a size of 0.6 μm or less in the first direction.

[0027] In some embodiments, the semiconductor layer includes a fourth via, which communicates with the first via and the second via, respectively, and the first electrode is electrically connected to the electrode signal line through the fourth via;

[0028] The orthogonal projections of the first via, the second via, and the fourth via on the substrate fall within the orthogonal projection of the semiconductor layer on the substrate.

[0029] In some embodiments, the orthogonal projection of the electrode signal line onto the substrate layer covers a portion of the edge of the semiconductor layer near the end of the first electrode.

[0030] In some embodiments, the second via includes a first exposed region for exposing a portion of the surface of the semiconductor layer away from the substrate layer, wherein the orthographic projection of the first exposed region onto the substrate layer does not overlap with the orthographic projection of the first electrode onto the substrate layer; and / or

[0031] The third via includes a second exposed area, which is used to expose a portion of the surface of the semiconductor layer away from the substrate layer. The orthographic projection of the second exposed area on the substrate layer does not overlap with the orthographic projection of the second electrode on the substrate layer.

[0032] In some embodiments, the size of the first exposed area in the first direction is greater than or equal to 0.5 μm; and / or

[0033] The second exposed area has a size greater than or equal to 0.5 μm in the first direction.

[0034] In some embodiments, the orthographic projection of the first via on the substrate layer does not overlap with the orthographic projection of the semiconductor layer on the substrate layer.

[0035] In some embodiments, the orthogonal projection of the electrode signal line onto the substrate layer covers the orthogonal projection of the semiconductor layer on the substrate layer on the side closest to the first electrode.

[0036] In some embodiments, the second insulating layer includes a first insulating structure and a second insulating structure, wherein the first insulating structure is located on the edge of the second via away from the third electrode, and the second insulating structure is located on the edge of the third via away from the third electrode, wherein the first direction is parallel to the plane of the semiconductor layer, and the first direction is the direction of the line connecting the first electrode and the second electrode;

[0037] The first electrode covers at least a portion of the edge of the first insulating structure, and / or the second electrode covers at least a portion of the edge of the second insulating structure;

[0038] And / or,

[0039] The orthographic projection of the second insulating structure onto the substrate layer does not overlap with the orthographic projection of the semiconductor layer onto the substrate layer.

[0040] In some embodiments, the semiconductor layer includes a fourth via, which communicates with both the first via and the second via, and the first electrode is electrically connected to an electrode signal line through the fourth via.

[0041] In some embodiments, a plurality of sub-pixels are arranged in an array, each sub-pixel including a pixel electrode and a driving transistor, the driving transistor including a semiconductor layer, a first electrode, a second electrode and a third electrode;

[0042] Multiple gate lines, the gate lines being electrically connected to the driving transistor, and at least four of the gate lines connecting to the same row of sub-pixels.

[0043] In some implementations, at least one gate signal line is disposed between the light-emitting regions of the nth row sub-pixel and the (n-1)th row sub-pixel; and / or,

[0044] At least one of the gate signal lines is disposed between the light-emitting regions of the nth row sub-pixel and the (n+1)th row sub-pixel; and / or,

[0045] At least two gate signal lines are disposed in the light-emitting area of ​​the nth row of sub-pixels, wherein the (n-1)th row of sub-pixels, the nth row of sub-pixels and the (n-1)th row of sub-pixels are arranged in an array along a second direction, the second direction being the length direction, and n being a natural number greater than 0.

[0046] In some implementations, adjacent columns of sub-pixels of different colors are connected by the same gate line.

[0047] In some implementations, multiple pixel units and multiple data signal transmission lines are repeatedly arranged, and the data signal transmission lines are electrically connected to data signal lines;

[0048] The pixel unit includes multiple sub-pixels;

[0049] Subpixels of the same color within the same pixel unit are connected to the same data signal transmission line.

[0050] A second aspect of this application provides a display panel, including:

[0051] The display substrate described in the first aspect above.

[0052] A third aspect of this application provides a display device, comprising:

[0053] The display panel described in the second aspect above.

[0054] The display substrate provided in this application can improve the ion-blocking effect by widening the gate insulating structure by placing the orthogonal projection of the third electrode on the substrate layer into the orthogonal projection of the gate insulating structure on the substrate layer. This widens the edge of the gate insulating structure away from the edge of the third electrode and the channel region of the semiconductor layer, thus preventing ions from penetrating into the channel region through the gate insulating structure and improving the stability of the TFT structure. Furthermore, due to the increased area of ​​the gate insulating structure, the area of ​​the gate insulating structure not covered by the third electrode increases. The uncovered portion of the gate insulating structure can act as a buffer platform, lengthening the step difference between the third electrode and the gate insulating structure. This prevents the film covering the third electrode and the gate insulating structure from breaking due to the step difference, thus avoiding moisture intrusion into the channel. Attached Figure Description

[0055] Figure 1 A schematic top view of a display substrate provided in an embodiment of this application;

[0056] Figure 2 A schematic top view of another display substrate provided in an embodiment of this application;

[0057] Figure 3 for Figure 2 Cross-sectional view along the A-A1 direction;

[0058] Figure 4 A schematic partial top view of another display substrate provided in an embodiment of this application;

[0059] Figure 5 This is a schematic diagram of the conductor formation of a display substrate provided in an embodiment of this application;

[0060] Figure 6 A schematic partial structural diagram of another display substrate provided in an embodiment of this application;

[0061] Figure 7 for Figure 6 A schematic diagram of the cross-section along the A-A1 direction;

[0062] Figure 8 for Figure 6 A schematic diagram of the cross-section along the B-B1 direction;

[0063] Figure 9 A schematic partial top view of another display substrate provided in an embodiment of this application;

[0064] Figure 10 This is a schematic diagram of a conductor fabrication process for a display substrate provided in an embodiment of this application;

[0065] Figure 11A schematic partial structural diagram of another display substrate provided in an embodiment of this application;

[0066] Figure 12 A schematic partial top view of a display substrate provided in an embodiment of this application;

[0067] Figure 13 for Figure 11 Cross-sectional view along the A-A1 direction;

[0068] Figure 14 A schematic partial top view of another display substrate provided in an embodiment of this application;

[0069] Figure 15 for Figure 14 Cross-sectional view along the A-A1 direction;

[0070] Figure 16 A schematic partial top view of another display substrate provided in an embodiment of this application;

[0071] Figure 17 A schematic partial top view of a display substrate provided in an embodiment of this application;

[0072] Figure 18 A schematic partial structural diagram of a display panel provided in an embodiment of this application;

[0073] Figure 19 This is a schematic partial structural diagram of a display device provided in an embodiment of this application.

[0074] The reference numerals in the figure represent:

[0075] 100, Substrate layer; 200, First conductive layer; 210, Electrode signal line; 220, Light-shielding structure; 221, Fourth structural part; 222, Fifth structural part; 223, Sixth structural part; 300, Semiconductor layer; 310, Fourth via; 400, Second conductive layer; 410, First electrode; 420, Second electrode; 430, Third electrode; 500, First insulating layer; 510, First via; 600, Second insulating layer; 610, Second via; 6 11. First exposed area; 620. Third via; 621. Second exposed area; 630. Gate insulating structure; 631. First structural portion; 632. Second structural portion; 633. Third structural portion; 640. First insulating structure; 650. Second insulating structure; 700. Pixel electrode; 800. Display substrate; 801. Liquid crystal layer; 802. Color filter substrate; 900. Display panel; 1000. Display device; X, First direction; Y, Second direction. Detailed Implementation

[0076] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0077] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0078] Currently, various pixel arrangements for liquid crystal displays have been proposed, including Dual-Gate Driving, Triple-Gate Driving (TRD), and Quadruple-Gate Driving. These reduce the number of source driver integrated circuits (ICs) to 1 / n (n=2, 3, 4, ...), thereby lowering backplane costs. While reducing the number of ICs significantly lowers costs, the increased number of gate signal lines leads to a lower aperture ratio in the display panel, further increasing power consumption and impacting display performance.

[0079] Figure 1 This is a schematic top view of a display substrate provided in an embodiment of this application. Figure 2 A schematic partial top view of another display substrate provided in an embodiment of this application. Exemplary, see reference... Figure 1 and Figure 2 Typically, in display products manufactured using gate technology, the first electrode 410, the second electrode 420, and the third electrode 430 can be used sequentially as the source, drain, and gate in the display substrate to form a TFT structure. The first electrode 410 and the second electrode 420 can be disposed on both sides of the semiconductor layer 300, the third electrode 430 can be disposed above the semiconductor layer 300, and the electrode signal line 310 can be disposed below the first electrode 410 or the second electrode 420.

[0080] Figure 3 for Figure 2 A schematic cross-sectional view along the A-A1 direction. For example, refer to... Figure 3 The electrode signal line 210 can be positioned at the bottom, within the first conductive layer 200. The first conductive layer 200 can be located between the semiconductor layer 300 and the substrate layer 100. The electrode signal line 210 can be connected to the semiconductor layer 300 via the first electrode 420. The second electrode 420 can cover the semiconductor layer. An insulating layer is disposed between the third electrode 430 and the semiconductor layer. (Reference) Figure 3 Typically, a large-area etching process is performed on the insulating layer. By etching the insulating layer over a large area, a portion of the insulating layer corresponding to the third electrode 430 can be preserved. For example, the preserved portion... Figure 3 As shown in the gate insulating structure 630, the semiconductor layer 300 can be made conductive through subsequent processes. However, after etching the insulating layer over a large area, the edge of the insulating layer is close to the channel region of the semiconductor layer 300. Ions can invade the channel region of the semiconductor layer 300 along the edge of the insulating layer, which means that the TFT structure is prone to conductor formation.

[0081] Figure 4 This is a schematic partial structural diagram of another display substrate provided in an embodiment of this application. Figure 5 This is a schematic diagram of the conductor formation of a display substrate provided in an embodiment of this application, wherein... Figure 5 This can be the id-Vg curve of the display substrate. Figure 5 The x-coordinate is Vg / V. Figure 5 The ordinate, ids / A, represents the characteristics of the source-drain current and gate-source voltage. (Reference) Figure 1 , Figure 4 and Figure 5 A step is formed between the third electrode 430 and the etched gate insulating structure 630, and the distance between the edges of the third electrode 430 and the gate insulating structure 630 is relatively small, with a small edge spacing or even flush edges. This results in a large drop in the film layer covering the step position, making the aforementioned film layer prone to defects such as... Figure 4 The fracture situation shown is as follows. Figure 4 The area marked C represents a region where the film layer is prone to breakage due to step differences. Breakage of the film layer can lead to moisture intrusion into the display substrate, resulting in, for example... Figure 5 The TFT structure shown exhibits negative bias and conductor characteristics; the negative bias characteristic is... Figure 5 The threshold voltage (Vth) of the TFT structure shifts negatively as the temperature decreases.

[0082] Figure 6 This is a schematic partial structural diagram of another display substrate provided in an embodiment of this application. Figure 7 for Figure 6 A schematic cross-sectional view along the A-A1 direction. For example, refer to... Figure 6 and Figure 7 The display substrate includes: a substrate layer 100, a first conductive layer 200, a semiconductor layer 300, a second conductive layer 400, a first insulating layer 500, and a second insulating layer 600. The substrate layer 100 may include a flexible substrate or a rigid substrate; the flexible substrate may include polyimide, and the rigid substrate may be made of glass. The first conductive layer 200 is disposed between the substrate layer 100 and the semiconductor layer 300, the semiconductor layer 300 is disposed between the first conductive layer 200 and the semiconductor layer 300, and the second insulating layer 600 is disposed between the semiconductor layer 300 and the second conductive layer 400. The first insulating layer 500 or the second insulating layer 600 may include a single-layer silicon nitride layer, a single-layer silicon oxide layer, or a stacked structure of silicon nitride and silicon oxide layers. The first electrode 410, the second electrode 420, the third gate, and the semiconductor layer 300 may together form a driving transistor. The driving transistor may be electrically connected to a pixel electrode 700, and the pixel electrode 700 may be located on the side of the driving transistor away from the substrate layer 100. A driving transistor can be used as a pixel driving circuit, and the driving transistor can be a driving device in the pixel driving circuit. The pixel driving circuit can include a 2T1C circuit structure, a 7T1C circuit structure, an 8T1C circuit structure, or a 9T1C circuit structure. A 2T1C circuit structure consists of two TFTs and one capacitor. Similarly, a 7T1C circuit consists of seven TFTs and one capacitor, and so on.

[0083] For example, the display substrate of this application can be an array substrate of LCD (Liquid Crystal Display) or a driving substrate of OLED (Organic Light-Emitting Diode). In LCD, driving transistors are connected to pixel electrodes to drive the liquid crystal to flip, thereby enabling light emission from the display panel. In OLED, the pixel electrode serves as the anode of the light-emitting device, and driving transistors are connected to the pixel electrode to drive the light-emitting device to emit light, thereby enabling light emission from the display panel.

[0084] In some examples, reference Figure 7The first conductive layer 200 may include an electrode signal line 210, which can transmit data signals. The second conductive layer 400 may include a first electrode 410, a second electrode 420, and a third electrode 430. The three electrodes can serve as the source, drain, and gate, respectively, to form a driving transistor. The material of the third electrode 430 may include Ti or Cu, or an alloy of Ti and Cu. The first insulating layer 500 includes a first via 510, and the second insulating layer 600 includes a second via 610 and a third via 620. The first electrode 410 is electrically connected to one end of the semiconductor layer 300 through the second via 610, and the first electrode 410 is electrically connected to the electrode signal line 210 through the first via 510. The first via 510 and the second via 610 allow the first electrode 410 to overlap with one edge of the semiconductor layer 300, and this overlap connects the first electrode 410 and the semiconductor layer 300. Correspondingly, the third via 620 allows the second electrode 420 to overlap the other edge of the semiconductor layer 300. For example, the second electrode 420 is electrically connected to the other end of the semiconductor layer 300 through the third via 620.

[0085] For example, the semiconductor layer includes conductive and non-conductive regions. The non-conductive region may be the region corresponding to the third electrode. The non-conductive region may include regions of the semiconductor layer other than the non-conductive region. For example, the first electrode and the second electrode may be located at opposite ends of the semiconductor layer, and the edge of the semiconductor layer may correspond to the edge of the conductive region of the semiconductor layer. The orthogonal projection of the third electrode onto the substrate layer is located between the orthogonal projections of the second via and the third via onto the substrate layer. The third electrode may correspond to the non-conductive region of the semiconductor layer, and the conductive region of the semiconductor layer may be disposed on both sides of the non-conductive region. The three electrodes and the semiconductor layer can form the driving transistor described above.

[0086] refer to Figure 7 In some examples, the second insulating layer 600 includes a gate insulating structure 630 located between the second via 610 and the third via 620. The gate insulating structure 630 may include a first structural portion 631, a second structural portion 632, and a third structural portion 633. The third structural portion 633 is connected between the first structural portion 631 and the second structural portion 632. The orthographic projections of the first structural portion 631 and the second structural portion 632 on the substrate 100 do not overlap with the orthographic projection of the third electrode 430 on the substrate 100. The orthographic projection of the third structural portion 633 on the substrate 100 completely covers the orthographic projection of the third electrode 430 on the substrate 100. The orthographic projection of the semiconductor layer 300 on the substrate 100 completely covers the orthographic projection of the gate insulating structure 630 on the substrate 100.

[0087] For example, the first structural portion, the second structural portion, and the third structural portion are disposed on the same layer and can also be integrally formed. Based on the orthogonal projection of the gate insulating structure on the substrate layer, the gate insulating structure can be divided into corresponding structural portions. For example, the structure of the gate insulating structure corresponding to the third electrode region can be the third structural portion, the part of the gate insulating structure other than the third structural portion that is close to the first electrode region can be the first structural portion, and the part of the gate insulating structure other than the third structural portion that is close to the second electrode region can be the second structural portion.

[0088] For example, the first electrode can serve as either the source or the drain, and the second electrode can serve as the other. Under the control of the gate signal applied to the third electrode, the voltage difference between the gate and the source reaches the threshold voltage of the driving transistor, so that the first electrode and the second electrode are connected through the semiconductor layer, transmitting the data signal from the first electrode to the second electrode. The first electrode, the second electrode, the third electrode, and the semiconductor layer can form the driving transistor, and the threshold voltage of the driving transistor is the minimum gate-source voltage required to form a conductive path between the source and drain terminals. The second electrode is electrically connected to the pixel electrode, transmitting the data signal to the pixel electrode to drive the pixel to emit light, thus realizing image display.

[0089] In some examples, the electrode signal lines can transmit data signals. The electrode signal lines can be arranged in the same layer as the third electrode. By placing the electrode signal lines in the first conductive layer, the space occupied by the signal lines can be reduced, so as to reasonably wire and arrange the first electrode, the second electrode and the third electrode, and improve the aperture ratio of the display substrate.

[0090] The display substrate provided in this application embodiment can improve the ion blocking effect by widening the gate insulating structure, so that the orthogonal projection of the third electrode on the substrate layer falls within the orthogonal projection of the gate insulating structure on the substrate layer. This makes the edge of the gate insulating structure farther away from the edge of the third electrode and also farther away from the channel region of the semiconductor layer. This prevents ions from penetrating into the channel region through the gate insulating structure, thereby improving the stability of the TFT structure. Furthermore, due to the increased area of ​​the gate insulating structure, the area of ​​the gate insulating structure not covered by the third electrode increases. The uncovered portion of the gate insulating structure can act as a buffer platform, lengthening the step difference between the third electrode and the gate insulating structure. This prevents the film covering the third electrode and the gate insulating structure from breaking due to the step difference, thus avoiding moisture intrusion into the channel.

[0091] In some examples, reference Figure 7The dimension of the first structural portion 631 in the first direction X is greater than or equal to 1 μm. For example, the dimension of the first structural portion 631 is 1 μm, 2 μm, or 3 μm. The first direction X is parallel to the plane of the semiconductor layer 300 and is the direction of the line connecting the first electrode 410 and the second electrode 420. The boundary distance between the first structural portion 631 and the third electrode 430 in the first direction X is greater than or equal to 1 μm, so that there can be a smaller step difference and a longer step difference buffer platform between the first structural portion 631 and the third electrode 430. After the film layer covers the first structural portion 631 and the third electrode 430, it is not easy for breakage to occur due to step difference problems.

[0092] In some examples, the size of the second structure in the first direction is greater than or equal to 1 μm. For example, the size of the second structure is 1 μm, 2 μm, or 3 μm. Exemplarily, the boundary distance between the second structure and the third electrode in the first direction is greater than or equal to 1 μm. The second structure and the third electrode can have a smaller step difference and a longer step difference buffer plateau, which can also prevent the film layer covering the second structure and the third electrode from breaking.

[0093] In some examples, reference Figure 7 The first structural portion 631 can be connected to the first electrode 410. The first electrode 410 covers at least a portion of the edge of the first structural portion 631 near the end of the first electrode 410. That is, the first electrode 410 can overlap the first structural portion 631. By covering the edge of the first structural portion 631 with the first electrode 410, the step difference between the third electrode 430 and the first structural portion 631 can be the thickness of the third electrode 430. This makes the film layer covered in subsequent processes less prone to breakage due to the step difference problem, thereby improving the film layer coverage of the display substrate and improving the problems of gate oxidation and TFT characteristic abnormalities caused by film layer breakage, such as negative bias or conductor formation.

[0094] In some examples, reference Figure 7 The second structural portion 632 can be connected to the second electrode 420. The second electrode 420 covers at least a portion of the edge of the second structural portion 632 near one end of the second electrode 420. The second electrode 420 can overlap the second structural portion 632. The step difference between the third electrode 430 and the second structural portion 632 can also be the thickness of the third electrode 430, so that the film layer covered in subsequent processes is not easily broken due to the step difference problem, thereby improving the film layer coverage of the display substrate and improving the problems of gate oxidation and TFT structural characteristic abnormalities caused by film layer breakage, such as negative bias or conductor formation.

[0095] For example, refer to Figure 7The first electrode 410 can completely cover the second via 610. Covering the second via 610 with the first electrode 410 achieves edge-wrapping of the second via 610, and simultaneously enables the second electrode 410 to overlap with the gate insulating structure 630. Similarly, the second electrode 420 can completely cover the third via 620. Covering the second electrode 420 achieves edge-wrapping of the third via 620, and simultaneously enables the second electrode 420 to overlap with the gate insulating structure 630.

[0096] For example, the boundary of the gate insulating layer near the first electrode is far from the channel of the semiconductor layer, and the boundary of the gate insulating layer near the second electrode is also far from the channel of the semiconductor layer. This can improve the blocking effect of the gate insulating layer and improve the stability of the TFT.

[0097] In some examples, reference Figure 7 The semiconductor layer 300 includes a fourth via 310, which is connected to the first via 510 and the third via 620. The first electrode 410 is electrically connected to the electrode signal line 210 through the fourth via 310. The orthographic projections of the first via 510, the second via 610 and the fourth via 310 on the substrate layer 100 fall within the orthographic projection of the semiconductor layer 300 on the substrate layer 100. Thus, the first electrode 410 can penetrate the semiconductor layer 300 and overlap a portion of the first structural portion 631. This improves the contact effect between the gate and the semiconductor layer 300 through the first via 510, the second via 610 and the fourth via 310, thereby reducing the contact resistance.

[0098] For example, since a fourth via is provided on the semiconductor layer, the first via can reserve space for the first electrode. Accordingly, the size of the semiconductor layer in the first direction can be appropriately increased to avoid degrading the characteristics of the semiconductor layer.

[0099] In some examples, the diameter of the fourth via can be the same as that of the first via, and both can be formed using the same mask.

[0100] In some examples, reference Figure 7 The edge of the second structure 632 covered by the second electrode 420 is far from the edge of the first structure 631, that is, the second electrode 420 can overlap the second structure 632.

[0101] In some examples, reference Figure 7 The second insulating layer 600 includes a first insulating structure 640 and a second insulating structure 650. The first insulating structure 640 is located at the edge of the second via 610 away from the third electrode 430, and the second insulating structure 650 is located at the edge of the third via 620 away from the third electrode 430.

[0102] In some examples, reference Figure 7 The first electrode 410 covers at least a portion of the edge of the first insulating structure 640, thereby allowing the first electrode 410 to overlap with the semiconductor layer 300 and the second insulating layer 600.

[0103] In some examples, reference Figure 7 The second electrode 420 covers at least a portion of the edge of the second insulating structure 650, thereby allowing the second electrode 420 to overlap with the semiconductor layer 300 and the second insulating layer 600.

[0104] In some examples, the size of the first electrode covering the first insulating structure in the first direction is less than or equal to 0.6 μm, for example, 0.6 μm, 0.5 μm or 0.4 μm.

[0105] In some examples, the size of the first electrode covering the first structural portion in the first direction is less than or equal to 0.6 μm, for example, 0.6 μm, 0.5 μm, or 0.4 μm. The first direction is parallel to the plane containing the semiconductor layer and is the direction of the line connecting the first and second electrodes.

[0106] In some examples, the size of the second electrode covering the second insulating structure in the first direction is less than or equal to 0.6 μm, for example, 0.6 μm, 0.5 μm or 0.4 μm.

[0107] In some examples, the size of the second electrode covering the second structure in the first direction is less than or equal to 0.6 μm, for example, 0.6 μm, 0.5 μm or 0.4 μm.

[0108] For example, refer to Figure 7 The edge size of the first electrode 410 needs to be less than half of ΔL, where ΔL is the total length of the two sides of the third electrode 430 that are conductord during semiconductor conductor formation. Half of ΔL is the length of one side of the semiconductor covered by the orthographic projection of the third electrode 430 that is conductord, ensuring that the semiconductor layer of the gate contact is conductord after the semiconductor layer is conductord, thus achieving an ohmic contact. Typically, the conductor ΔL is greater than or equal to 1.2 μm and less than or equal to 1.5 μm, therefore the edge size of the first electrode 410 only needs to be less than or equal to 0.6 μm. Similarly, the edge size of the second electrode 420 only needs to be less than or equal to 0.6 μm.

[0109] In some examples, reference Figure 7 The orthogonal projection of the electrode signal line 210 onto the substrate layer 100 covers a portion of the edge of the semiconductor layer 300 near the first electrode 410.

[0110] In some examples, reference Figure 7The first conductive layer 200 includes a light-shielding structure 220. The orthographic projection of the light-shielding structure 220 on the substrate layer 100 and the orthographic projection of the electrode signal line 210 on the substrate layer 100 do not overlap. The orthographic projection of the light-shielding structure 220 on the substrate layer 100 can be set based on the orthographic projection of the third electrode 430 on the substrate layer 100, for example... Figure 2 The orthogonal projection of the light-shielding structure 220 on the substrate 100 completely covers the orthogonal projection of the third electrode 430 on the substrate 100.

[0111] For example, a light-shielding structure can be used to protect the channel of a semiconductor layer. For instance, the light-shielding structure can block the light emitted by the light-emitting backplane or the light from the external environment to avoid the phenomenon of photo-induced leakage current caused by the influence of light on the conductivity of the channel.

[0112] In some examples, reference Figure 7 The orthographic projection of the semiconductor layer 300 on the substrate layer 100 can completely cover the orthographic projection of the light-shielding structure 220 on the substrate layer 100, so as to block light through the light-shielding structure 220.

[0113] In some examples, reference Figure 7 The orthographic projection of the light-shielding structure 220 on the substrate 100 covers the orthographic projection of the first structural part 631 on the substrate 100.

[0114] In some examples, reference Figure 7 The orthographic projection of the light-shielding structure 220 on the substrate 100 partially overlaps with the orthographic projection of the second structure 632 on the substrate 100.

[0115] Figure 8 for Figure 6 A schematic cross-sectional view along the B-B1 direction; in some examples, refer to... Figure 8 The light-shielding structure 220 can be electrically connected to the third electrode 430 to form a dual-gate structure.

[0116] Figure 9 This is a schematic partial top view of another display substrate provided in an embodiment of this application. Figure 10 This is a schematic diagram of a conductor fabrication process for a display substrate, provided as an embodiment of this application. (Reference) Figure 9 and Figure 10 The TFT structure fabrication scheme can be 4Mask (4-mask process), for example, the fabrication scheme can be... Figure 9 The processes shown, in order, are light-shielding mask process, semiconductor mask process, gate insulating mask process, and gate mask process. After patterning is completed in the gate mask process, the semiconductor is then subjected to a conductor-forming process.

[0117] For example, refer to Figure 9The structure of the display substrate can be achieved by depositing a first conductive thin film layer on one side of the substrate layer 100, etching the first conductive thin film layer to obtain a first conductive layer 200, wherein the etching yields a light-shielding structure 220 and an electrode signal line 210. Then, a first insulating layer 500 and a semiconductor thin film layer are sequentially deposited on the side of the first conductive layer 200 away from the substrate layer 100. The semiconductor thin film layer is then etched to obtain a semiconductor layer 300. A second insulating layer 600 and a second conductive layer 400 are then sequentially deposited on the side of the semiconductor layer 300 away from the substrate layer 100. The second conductive layer 400 is then etched, including photolithography and wet etching, to obtain a first electrode 410, a second electrode 420, and a third electrode 430. Photoresist is deposited on the side of the etched second conductive layer 400 away from the substrate layer 100, and the photoresist is exposed and developed to obtain a patterned photoresist. The orthographic projection of the patterned photoresist onto the substrate layer 100 covers the non-conductive region, resulting in a transition substrate. Finally, the transition substrate is subjected to a conductor treatment to make the areas of the semiconductor layer other than the conductor-conducting areas conductor-conducting, thereby obtaining the conductor-conducting areas and thus the display substrate.

[0118] For example, refer to Figure 10 Photoresist can be applied to the side of the third electrode 430 away from the substrate layer 100. The third electrode 430 is then etched using a mask, including photolithography and wet etching. Dopant ions are then implanted into the semiconductor layer 300 to achieve conductor fabrication. Finally, the photoresist on the third electrode 430 is removed, completing the fabrication of the TFT structure. Subsequent fabrication steps can be, in sequence, an organic insulating layer process, a first pixel electrode layer process, a passivation layer process, and a second pixel electrode layer process.

[0119] Figure 11 This is a schematic partial structural diagram of another display substrate provided in an embodiment of this application. In some examples, reference is made to... Figure 11 The second via 610 includes a first exposed region 611, which exposes a portion of the surface of the semiconductor layer 300 away from the substrate layer 100. The orthographic projection of the first exposed region 611 onto the substrate layer 100 does not overlap with the orthographic projection of the first electrode 410 onto the substrate layer 100. The edge of the gate insulating structure 630 near the first electrode 410 may correspond to a portion of the boundary of the first exposed region 611. The structure between the edge of the gate insulating structure 630 corresponding to the first exposed region 611 and the edge of the third electrode 430 may be a first structural portion 631, the size of which in the first direction X is greater than or equal to 1 μm.

[0120] In some examples, reference Figure 11The third via 620 includes a second exposed region 621, which exposes a portion of the surface of the semiconductor layer 300 away from the substrate layer 100. The orthographic projection of the second exposed region 621 onto the substrate layer 100 does not overlap with the orthographic projection of the second electrode 420 onto the substrate layer 100. The edge of the gate insulating structure 630 near the second electrode 420 may correspond to a portion of the boundary of the second exposed region 621. The structure between the edge of the gate insulating structure 630 corresponding to the second exposed region 621 and the edge of the third electrode 430 may be a second structural portion 632, the size of which in the first direction X is greater than or equal to 1 μm.

[0121] In some examples, the size of the first exposed region in the first direction is greater than or equal to 0.5 μm, and the size of the second exposed region in the first direction is greater than or equal to 0.5 μm, to ensure that the third electrode does not completely cover the semiconductor layer. Thus, the non-channel region of the semiconductor layer can be made conductive through the exposed region based on the ion doping process, followed by the organic insulating layer process, the first pixel electrode layer process, the passivation layer process, and the second pixel electrode layer process.

[0122] In some examples, the orthographic projection of the first via on the substrate layer and the orthographic projection of the semiconductor layer on the substrate layer do not overlap, and the aperture of the first via in the first direction can be less than or equal to the aperture of the fourth via in the first direction, so that the first electrode can be connected to the semiconductor layer through the first via, the second via and the fourth via.

[0123] In some examples, reference Figure 11 The first conductive layer 200 includes a first insulating structure 640 and a second insulating structure 650. The first electrode 410 covers at least a portion of the edge of the first insulating structure 640, such that the first electrode 410 can overlap the first insulating structure 640, while the first insulating structure 640 can cover a portion of the edge of the semiconductor layer 300.

[0124] In some examples, reference Figure 11 The orthographic projection of the second insulating structure 650 on the substrate 100 does not overlap with the orthographic projection of the semiconductor layer 300 on the substrate 100, so that the second electrode 420 can cover a portion of the semiconductor layer 300.

[0125] In some examples, reference Figure 11 The semiconductor layer 300 includes a fourth via 310, which is connected to the first via 510 and the third via 620 respectively. The first electrode 410 is electrically connected to the electrode signal line 210 through the fourth via 310.

[0126] In some examples, reference Figure 11The orthogonal projection of the electrode signal line 210 on the substrate 100 covers the orthogonal projection of the semiconductor layer 300 on the side near the first electrode 410 on the substrate 100.

[0127] In some examples, reference Figure 11 The first conductive layer 200 may include a light-shielding structure 220. The orthographic projection of the light-shielding structure 220 on the substrate layer 100 may overlap with the orthographic projection of the gate insulating structure 630 on the substrate layer 100, so as to avoid the phenomenon of photo-generated leakage current caused by the influence of light on the conductivity of the channel.

[0128] In some examples, reference Figure 11 The orthographic projection of the light-shielding structure 220 on the substrate 100 and the orthographic projection of the third electrode 430 on the substrate 100 partially overlap.

[0129] In some examples, reference Figure 11 The orthographic projection of the light-shielding structure 220 on the substrate 100 and the orthographic projection of the first structural part 631 on the substrate 100 do not overlap.

[0130] In some examples, reference Figure 11 The orthographic projection of the light-shielding structure 220 on the substrate 100 overlaps with the orthographic projection of the third structure 633 on the substrate 100.

[0131] Figure 12 This is a schematic partial top view of a display substrate provided in an embodiment of this application. Figure 13 for Figure 12 A cross-sectional view along the A-A1 direction. In some examples, refer to... Figure 12 and Figure 13 The first electrode 410 covers a portion of the first insulating structure 640 and is partially overlapped with the semiconductor layer 300. For example, the orthographic projection of the first insulating structure 640 on the substrate layer 100 and the orthographic projection of the semiconductor layer 300 on the substrate layer 100 do not overlap. The first electrode 410 covers at least a portion of the edge of the first insulating structure 640.

[0132] In some examples, reference Figure 13 The second insulating layer 600 includes a first insulating structure 640 and a second insulating structure 650. The orthographic projections of the first insulating structure 640 and the second insulating structure 650 on the substrate layer 100 do not overlap with the orthographic projections of the semiconductor layer 300 on the substrate layer 100. The first electrode 410 can be partially overlapped with the semiconductor layer 300 and cover part of the first insulating structure 640. The second electrode 420 can cover part of the semiconductor layer 300.

[0133] In some examples, reference Figure 13The orthogonal projection of the light-shielding structure 220 on the substrate 100 can completely cover the orthogonal projections of the third electrode 430, the second structural part 632, and the third structural part 633 on the substrate 100.

[0134] In some examples, reference Figure 13 The orthographic projection of the light-shielding structure 220 on the substrate 100 and the orthographic projection of the first structural part 631 on the substrate 100 do not overlap.

[0135] In some examples, reference Figure 13 The orthogonal projection of the light-shielding structure 220 onto the substrate 100 completely covers the orthogonal projections of the second structural part 632 and the third structural part 633 onto the substrate 100.

[0136] Figure 14 This is a schematic partial structural diagram of another display substrate provided in an embodiment of this application. Figure 15 for Figure 14 A cross-sectional view along the A-A1 direction. In some examples, refer to... Figure 13 and 14 The orthogonal projection of the light-shielding structure 220 on the substrate 100 can completely cover the orthogonal projection of the gate insulating structure 630 on the substrate 100, so as to avoid the phenomenon of photo-generated leakage current caused by the influence of light on the channel conductivity.

[0137] In some examples, the light-shielding structure can be electrically connected to the third electrode, which serves as the top gate of the display substrate, and the light-shielding structure can serve as the bottom gate of the display substrate, that is, the display substrate can form a dual-gate structure.

[0138] For example, the material of the light-shielding structure may include Ti or Cu, or an alloy of Ti and Cu.

[0139] In some examples, reference Figure 15 The light-shielding structure 220 may include a fourth structural portion 221, a fifth structural portion 222, and a sixth structural portion 223. The sixth structural portion 223 is connected between the fourth structural portion 221 and the fifth structural portion 222. The orthographic projection of the sixth structural portion 223 on the substrate 100 coincides with the orthographic projection of the gate insulating structure 630 on the substrate 100. The orthographic projections of the fourth structural portion 221 and the fifth structural portion 222 on the substrate 100 do not overlap with the orthographic projection of the gate insulating structure 630 on the substrate 100, so as to avoid the phenomenon of photo-generated leakage current caused by the influence of light on the conductivity of the channel.

[0140] refer to Figure 15Because the gate insulating structure 630 is larger in the first direction than the third electrode 430, the non-conductive region of the original semiconductor layer increases, while the conductive region of the semiconductor layer decreases. Therefore, to compensate for the insufficient conductive region, the length of the semiconductor layer 300 in the first direction X can be increased, and the length of the first electrode 410 in the first direction X can also be increased. When the semiconductor layer 300 is insufficiently conductive, the light-shielding structure 220, acting as the bottom gate, can enhance the carrier induction excitation of the semiconductor layer 300 in the non-conductive region, thereby improving the conductivity of the semiconductor layer 300 in the non-conductive region. This reduces the contact resistance between the first electrode 410 and the second electrode 420, increases the supply current, and improves the electrical performance of the driving transistor. This provides sufficient supply current to the pixel electrode, improves the charging efficiency of the pixel electrode, and enables stable light emission from the sub-pixels. This avoids uneven display brightness and bright / dark lines caused by insufficient supply current, thus improving the display effect of the display panel.

[0141] In some examples, the display substrate also includes multiple sub-pixels and multiple gate lines arranged in an array. Each sub-pixel includes a pixel electrode and a driving transistor, which may include a semiconductor layer, a first electrode, a second electrode, and a third electrode. The gate lines may be electrically connected to the driving transistor, and at least four gate lines may be connected to the same row of sub-pixels.

[0142] Figure 16 A schematic partial top view of another display substrate provided in an embodiment of this application. In some examples, reference is made to... Figure 16 At least one gate signal line can be disposed between the light-emitting areas of the nth row of sub-pixels and the (n-1)th row of sub-pixels. Alternatively, in some examples, at least one gate signal line can be disposed between the light-emitting areas of the nth row of sub-pixels and the (n+1)th row of sub-pixels. Alternatively, in some examples, at least two gate signal lines can be disposed within the light-emitting area of ​​the nth row of sub-pixels. The (n-1)th, nth, and (n+1)th row of sub-pixels can be arranged in an array along the second direction, thereby saving space occupied by gate lines and achieving reasonable wiring of the display panel through the arrangement of multiple gate line arrays and the setting of at least four gate lines driving one row of sub-pixels. The second direction is parallel to the plane of the substrate layer, and the second direction can intersect with the first direction. The second direction is the length direction of the electrode signal line, and n is a natural number greater than 0.

[0143] For example, refer to Figure 16The first gate line G1, the second gate line G2, the third gate line G3, and the fourth gate line G4 can provide gate driving signals to the nth row of sub-pixels in a multi-row sub-pixel array. The first gate line G1 can be positioned between the light-emitting areas of the nth row of sub-pixels and the (n-1)th row of sub-pixels. The fourth gate line G4 can be positioned between the light-emitting areas of the nth row of sub-pixels and the (n+1)th row of sub-pixels; the second gate line G2 and the third gate line G3 can intersect with the nth row of sub-pixels. The light-emitting area of ​​each sub-pixel is denoted as LA. By arranging multiple gate lines in an array and setting at least four gate lines to drive a row of sub-pixels, space occupied by gate lines is saved, achieving reasonable wiring of the display panel.

[0144] It should be noted that the first direction X is the direction in which rows can be extended, and the second direction Y is the direction in which columns can be extended.

[0145] In some examples, subpixels of different colors in two adjacent columns can be connected by the same grid line.

[0146] In some examples, the display substrate may also include multiple pixel units and multiple data signal transmission lines that are repeatedly arranged. The data signal transmission lines may be electrically connected to electrode signal lines. A pixel unit may include multiple sub-pixels, and sub-pixels of the same color within the same pixel unit may be connected to the same data signal transmission line.

[0147] For example, the smallest repeating unit of subpixels of different colors in the display substrate includes 24 columns of subpixels, corresponding to six data signal transmission lines. The smallest repeating unit of subpixels of different colors refers to the smallest group of subpixels, each group corresponding to a different color, typically including red, green, and blue subpixels, which are regularly repeated throughout the display substrate to form the complete pixel structure of the display panel. The arrangement of these repeating units defines the basic arrangement of the subpixels, ensuring the proper distribution of different colors in the display panel.

[0148] For example, in the smallest repeating unit where driving transistors are connected to gate lines, each gate line is connected to two driving transistors. The smallest repeating unit where driving transistors are connected to gate lines refers to the minimum arrangement of driving transistors and gate lines formed within a repeating unit throughout the entire display substrate. The smallest repeating unit where driving transistors are connected to gate lines can be configured with specific patterns or arrangements to connect the driving transistors to the gate lines, thereby ensuring the uniformity and consistency of the display driving.

[0149] Figure 17 This is a schematic partial top view of a display substrate provided for an embodiment of this application. In some examples, reference is made to... Figure 17The area enclosed by the dashed box A3 represents the smallest repeating unit connecting the driving transistor and the gate lines. Multiple gate lines extend along a first direction X, and multiple data lines extend along a second direction Y. The multiple gate lines may include a first gate line G1, a second gate line G2, a third gate line G3, a fourth gate line G4…a twelfth gate line G12. The multiple data signal transmission lines may include a first data signal transmission line RD1, a second data signal transmission line GD1, a third data signal transmission line BD1, a fourth data signal transmission line RD2, a fifth data signal transmission line GD2, and a sixth data signal transmission line BD2. The first data signal transmission line RD1 can provide data signals to multiple columns of red sub-pixels. The fourth data signal transmission line RD2 can provide data signals to different columns of red sub-pixels. The second data signal transmission line GD1 can provide data signals to multiple columns of green sub-pixels. The fifth data signal transmission line GD2 can provide data signals to different columns of green sub-pixels. The third data signal transmission line BD1 can provide data signals to multiple columns of blue sub-pixels. The sixth data signal transmission line BD2 can provide data signals to different columns of blue sub-pixels.

[0150] In some embodiments, reference Figure 17 The system comprises multiple gate lines, including a first gate line G1, a second gate line G2, a third gate line G3, and a fourth gate line G4 arranged sequentially along the second direction Y. The smallest repeating unit connecting the driving transistors to the gate lines comprises a first sub-pixel sp1, a second sub-pixel sp2, a third sub-pixel sp3, a fourth sub-pixel sp4, a fifth sub-pixel sp5, a sixth sub-pixel sp6, a seventh sub-pixel sp7, and an eighth sub-pixel sp8 arranged sequentially along the first direction X. The first gate line G1 connects to the driving transistors in the first sub-pixel sp1 and the second sub-pixel sp2; the third gate line G3 connects to the driving transistors in the third sub-pixel sp3 and the fourth sub-pixel sp4; the second gate line G2 connects to the driving transistors in the fifth sub-pixel sp5 and the sixth sub-pixel sp6; and the fourth gate line G4 connects to the driving transistors in the seventh sub-pixel sp7 and the eighth sub-pixel sp8. By using multiple gate lines, multiple data signal transmission lines, and multiple repeating sub-pixel units, the spatial layout of the signal lines can be rationally planned, while ensuring the uniformity and consistency of the display driving.

[0151] Figure 18 This is a schematic partial structural diagram of a display panel provided in an embodiment of this application. In some examples, reference is made to... Figure 1 8. This application provides a display panel. The display panel of this application may include the display substrate in any of the above-described technical solutions.

[0152] For example, refer to Figure 18In a liquid crystal display, the display panel includes a display substrate 800, a liquid crystal layer 801, and a color filter substrate 802. The color filter substrate includes a color filter film and a black matrix.

[0153] For example, an LCD display module includes a backlight and a display substrate.

[0154] For example, in an OLED, the display panel includes a display substrate and a light-emitting device.

[0155] Figure 19 This is a schematic partial structural diagram of a display device provided in an embodiment of this application. In some examples, reference is made to… Figure 19 This application provides a display device. The display device 1000 of this application may include the display panel 900 in any of the above-described technical solutions.

[0156] The display devices provided in this application embodiment may include televisions, computers, smartphones, smart wearable devices, laptops, and tablets, etc. Smart wearable devices may include smartwatches, AR (augmented reality) devices, and VR (virtual reality) devices, etc.

[0157] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0158] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

[0159] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0160] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. A display substrate, characterized in that, include: The system comprises a substrate layer, a first conductive layer, a semiconductor layer, a second conductive layer, a first insulating layer, and a second insulating layer. The first conductive layer is disposed between the substrate layer and the semiconductor layer, the semiconductor layer is disposed between the first conductive layer and the second conductive layer, the first insulating layer is disposed between the first conductive layer and the semiconductor layer, and the second insulating layer is disposed between the semiconductor layer and the second conductive layer. The first conductive layer includes an electrode signal line, the second conductive layer includes a first electrode, a second electrode, and a third electrode, the first insulating layer includes a first via, the second insulating layer includes a second via and a third via, the first electrode is electrically connected to one end of the semiconductor layer through the second via, the first electrode is electrically connected to the electrode signal line through the first via, the second electrode is electrically connected to the other end of the semiconductor layer through the third via, and the orthogonal projection of the third electrode on the substrate layer is located between the orthogonal projections of the second via and the third via on the substrate layer; The second insulating layer includes a gate insulating structure located between the second via and the third via. The gate insulating structure includes a first structural portion, a second structural portion, and a third structural portion. The third structural portion is connected between the first structural portion and the second structural portion. The orthogonal projections of the first structural portion and the second structural portion on the substrate do not overlap with the orthogonal projection of the third electrode on the substrate. The orthogonal projection of the third structural portion on the substrate completely covers the orthogonal projection of the third electrode on the substrate. The orthogonal projection of the semiconductor layer on the substrate completely covers the orthogonal projection of the gate insulating structure on the substrate.

2. The display substrate according to claim 1, characterized in that, The first conductive layer includes a light-shielding structure; The orthogonal projection of the semiconductor layer onto the substrate completely covers the orthogonal projection of the light-shielding structure onto the substrate; and / or The orthographic projection of the light-shielding structure on the substrate overlaps with the orthographic projection of the third electrode on the substrate. and / or The orthographic projection of the light-shielding structure on the substrate layer covers the orthographic projection of the first structural part on the substrate layer, or the orthographic projection of the light-shielding structure on the substrate layer and the orthographic projection of the first structural part on the substrate layer do not overlap; and / or The orthographic projection of the light-shielding structure on the substrate overlaps with the orthographic projection of the second structural part on the substrate. and / or The orthographic projection of the light-shielding structure on the substrate overlaps with the orthographic projection of the third structural part on the substrate.

3. The display substrate according to claim 2, characterized in that, The light-shielding structure is electrically connected to the third electrode.

4. The display substrate according to claim 3, characterized in that, The light-shielding structure includes a fourth structural part, a fifth structural part, and a sixth structural part, wherein the sixth structural part is connected between the fourth structural part and the fifth structural part; The orthographic projection of the sixth structural portion on the substrate layer coincides with the orthographic projection of the gate insulating structure on the substrate layer, while the orthographic projections of the fourth and fifth structural portions on the substrate layer do not overlap with the orthographic projection of the gate insulating structure on the substrate layer.

5. The display substrate according to claim 1, characterized in that, The first structural portion has a dimension greater than or equal to 1 μm in the first direction; and / or The second structural part has a dimension greater than or equal to 1 μm in the first direction; Wherein, the first direction is parallel to the plane where the semiconductor layer is located, and the first direction is the direction of the line connecting the first electrode and the second electrode.

6. The display substrate according to any one of claims 1 to 5, characterized in that, The first structural portion is connected to the first electrode, and the first electrode covers at least a portion of the edge of the first structural portion near the first electrode; the second structural portion is connected to the second electrode, and the second electrode covers at least a portion of the edge of the second structural portion near the second electrode. The second insulating layer includes a first insulating structure and a second insulating structure, wherein the first insulating structure is located at the edge of the second via on the side away from the third electrode, and the second insulating structure is located at the edge of the third via on the side away from the third electrode; The first electrode covers at least a portion of the edge of the first insulating structure, and / or the second electrode covers at least a portion of the edge of the second insulating structure.

7. The display substrate according to claim 6, characterized in that, The first electrode covers the first insulating structure in the first direction with a size less than or equal to 0.6 μm, and / or the first electrode covers the first structural portion in the first direction with a size less than or equal to 0.6 μm; And / or, The second electrode covers the second insulating structure in the first direction with a size less than or equal to 0.6 μm, and / or the second electrode covers the second structural portion in the first direction with a size less than or equal to 0.6 μm; The first direction is parallel to the plane where the semiconductor layer is located, and the first direction is the direction of the line connecting the first electrode and the second electrode.

8. The display substrate according to claim 6, characterized in that, The semiconductor layer includes a fourth via, which is connected to the first via and the second via, respectively, and the first electrode is electrically connected to the electrode signal line through the fourth via. The orthogonal projections of the first via, the second via, and the fourth via on the substrate fall within the orthogonal projection of the semiconductor layer on the substrate.

9. The display substrate according to claim 8, characterized in that, The orthogonal projection of the electrode signal line onto the substrate layer covers a portion of the edge of the semiconductor layer near the first electrode.

10. The display substrate according to any one of claims 1 to 5, characterized in that, The second via includes a first exposed area, which is used to expose a portion of the surface of the semiconductor layer away from the substrate layer. The orthographic projection of the first exposed area on the substrate layer does not overlap with the orthographic projection of the first electrode on the substrate layer. and / or The third via includes a second exposed area, which is used to expose a portion of the surface of the semiconductor layer away from the substrate layer. The orthographic projection of the second exposed area on the substrate layer does not overlap with the orthographic projection of the second electrode on the substrate layer.

11. The display substrate according to claim 10, characterized in that, The first exposed area has a size greater than or equal to 0.5 μm in the first direction; and / or The second exposed area has a size greater than or equal to 0.5 μm in the first direction.

12. The display substrate according to claim 10, characterized in that, The orthographic projection of the first via on the substrate layer does not overlap with the orthographic projection of the semiconductor layer on the substrate layer.

13. The display substrate according to claim 10, characterized in that, The orthogonal projection of the electrode signal line onto the substrate covers the orthogonal projection of the semiconductor layer on the side of the semiconductor layer closest to the first electrode onto the substrate.

14. The display substrate according to claim 10, characterized in that, The second insulating layer includes a first insulating structure and a second insulating structure. The first insulating structure is located on the edge of the second via away from the third electrode, and the second insulating structure is located on the edge of the third via away from the third electrode. The first direction is parallel to the plane of the semiconductor layer, and the first direction is the direction of the line connecting the first electrode and the second electrode. The first electrode covers at least a portion of the edge of the first insulating structure, and / or the second electrode covers at least a portion of the edge of the second insulating structure; And / or, The orthographic projection of the second insulating structure onto the substrate layer does not overlap with the orthographic projection of the semiconductor layer onto the substrate layer.

15. The display substrate according to claim 10, characterized in that, The semiconductor layer includes a fourth via, which is connected to the first via and the second via, respectively, and the first electrode is electrically connected to the electrode signal line through the fourth via.

16. The display substrate according to claim 1, characterized in that, include: Multiple sub-pixels arranged in an array, each sub-pixel including a pixel electrode and a driving transistor, the driving transistor including a semiconductor layer, a first electrode, a second electrode and a third electrode; Multiple gate lines, the gate lines being electrically connected to the driving transistor, and at least four of the gate lines connecting to the same row of sub-pixels.

17. The display substrate according to claim 16, characterized in that, At least one gate signal line is disposed between the light-emitting areas of the nth row sub-pixel and the (n-1)th row sub-pixel; and / or, At least one of the gate signal lines is disposed between the light-emitting regions of the nth row sub-pixel and the (n+1)th row sub-pixel; and / or, At least two of the gate signal lines are disposed in the light-emitting area of ​​the nth row of sub-pixels, wherein the (n-1)th row of sub-pixels, the nth row of sub-pixels and the (n+1)th row of sub-pixels are arranged in an array along a second direction, the second direction being the length direction of the electrode signal lines, and n being a natural number greater than 0.

18. The display substrate according to claim 17, characterized in that, The sub-pixels of two adjacent columns of different colors are connected by the same gate line.

19. The display substrate according to claim 18, characterized in that, Also includes: Multiple pixel units and multiple data signal transmission lines are repeatedly configured, and the data signal transmission lines are electrically connected to data signal lines; The pixel unit includes multiple sub-pixels; Subpixels of the same color within the same pixel unit are connected to the same data signal transmission line.

20. A display panel, characterized in that, include: The display substrate as described in any one of claims 1 to 19.

21. A display device, characterized in that, include: The display panel as described in claim 20.

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