Miniature light-emitting structure and miniature light-emitting device

Abstract

The utility model discloses a miniature light-emitting structure and a miniature light-emitting device, which are characterized in that light emitted by the side wall of a pixel unit is shielded through a metal wall arranged between adjacent pixel units, so that optical crosstalk is avoided; the coplanar design that the top surface of the metal wall is flush with the top surface of the first electrode can ensure that the bonding layer is in contact with the first electrode and the second electrode at the same time, so that the problem of pseudo soldering or open circuit caused by height difference is avoided; the second electrode and the metal wall are integrally connected to form a conductive network, so that the transmission distance of current is greatly shortened, the resistance difference is reduced, and the problem of non-uniform brightness of a central area and a peripheral area of a display device in related technologies is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor light-emitting technology, specifically to a micro light-emitting structure and a micro light-emitting device. Background Technology

[0002] With the continuous development of display technology, micron-sized light-emitting diodes (Micro-LEDs) are leading industry innovation as a new generation of display technology. Leveraging their advantages such as ultra-high resolution, high color saturation, flexible display capabilities, and ultra-long lifespan, they are gradually becoming a core technology in the high-end display field. However, as market demands shift towards smaller sizes, higher brightness, and greater integration, Micro-LED technology faces numerous technical bottlenecks. Utility Model Content

[0003] This application provides a micro-light-emitting structure and a micro-light-emitting device to solve problems in related technologies.

[0004] To address the aforementioned problems, in a first aspect, embodiments of this application provide a micro-light-emitting structure comprising a pixel array having multiple pixel units, each pixel unit comprising a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and a first electrode stacked sequentially, and a second electrode disposed in the outer peripheral region of the pixel array; a metal wall is disposed in the pixel array, the metal wall forming an isolation structure between adjacent pixel units, the top surface of the metal wall being flush with the top surface of the first electrode, and the height of the metal wall being greater than the sidewall height of the light-emitting layer; the metal wall and the second electrode are integrally connected to form a conductive network.

[0005] In some possible implementations, the metal wall includes a first metal layer and a second metal layer, wherein the first metal layer is disposed close to the first semiconductor layer and the second metal layer is disposed away from the first semiconductor layer, wherein the first metal layer is made of a highly conductive material and the second metal layer is made of a highly reflective material.

[0006] In some possible implementations, the bottom of the first metal layer includes a conductive contact portion that extends into the interior of the first semiconductor layer and forms an ohmic contact with the first semiconductor layer; the material of the conductive contact portion is a titanium-aluminum alloy.

[0007] In some possible implementations, the second electrode is a ring-shaped electrode arranged around the pixel array.

[0008] In some possible implementations, the micro-light-emitting structure further includes an insulating layer covering the surface of the pixel array, the metal wall, and the area between the pixel array and the second electrode; the first electrode and the metal wall are isolated by the insulating layer.

[0009] In some possible implementations, the insulating layer is provided with contact holes located in the connection area between the first electrode and the second electrode, so that the first electrode and the second electrode are electrically connected through the contact holes.

[0010] In some possible implementations, the bottom of the metal wall is in direct contact with the first semiconductor layer, and the insulating layer does not cover the contact area between the metal wall and the first semiconductor layer.

[0011] In some possible implementations, the width of the metal wall is greater than or equal to 50% and less than or equal to 80% of the channel spacing between adjacent pixel units.

[0012] In some possible implementations, the lateral spacing between the sidewall of the metal wall and the sidewall of the light-emitting layer is greater than or equal to 1.0 micrometer and less than or equal to 1.5 micrometer.

[0013] In some possible implementations, the micro-light-emitting structure further includes a transparent conductive layer disposed between the second semiconductor layer and the first electrode, wherein the transparent conductive layer is made of indium tin oxide or indium gallium zinc oxide.

[0014] Secondly, embodiments of this application provide a micro light-emitting device, including a micro light-emitting structure and a driving substrate as described in any of the preceding claims; the driving substrate is a silicon substrate, and a first bonding point and a second bonding point are disposed on the silicon substrate, the first bonding point being bonded to the first electrode, and the second bonding point being bonded to the second electrode.

[0015] Based on the aforementioned technical solution, this application uses a metal wall disposed between adjacent pixel units to block the light emitted from the sidewalls of the pixel units, thereby avoiding optical crosstalk. Furthermore, the coplanar design, where the top surface of the metal wall is flush with the top surface of the first electrode, ensures that the bonding layer contacts both the first and second electrodes simultaneously, thus avoiding issues such as poor soldering or open circuits caused by height differences. Simultaneously, by using the metal wall as an extension of the second electrode, the second electrode and the metal wall are integrally connected to form a conductive network, which significantly shortens the current transmission distance and reduces resistance differences, thereby improving the problem of uneven brightness between the central and peripheral areas of the display device in related technologies. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of this application. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0017] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0018] Figure 1 This is a cross-sectional schematic diagram of the micro-light-emitting structure provided in the embodiments of this application.

[0019] Figure 2 A schematic diagram showing the structural relationship between the metal wall and the first semiconductor layer of the micro-light-emitting structure provided in this application embodiment.

[0020] Figure 3 This is a top view of a pixel array of a micro-light-emitting structure provided in an embodiment of this application.

[0021] Figure 4 This is a schematic flowchart illustrating the fabrication method of the micro-luminescent structure provided in the embodiments of this application.

[0022] Figure 5 This is a schematic cross-sectional view of the epitaxial stack provided in an embodiment of this application.

[0023] Figure 6 This is a schematic diagram of the cross-sectional structure after the table structure is etched and formed according to an embodiment of this application.

[0024] Figure 7 This is a schematic cross-sectional view of the first electrode after its formation, as provided in an embodiment of this application.

[0025] Figure 8 This is a schematic cross-sectional view of the second electrode and the metal wall after they are formed, as provided in an embodiment of this application.

[0026] Figure 9 This is a schematic cross-sectional view of the insulating layer after deposition and the formation of contact holes, as provided in an embodiment of this application.

[0027] Figure 10 This is a schematic cross-sectional view of the solder joint after the underlayer is formed, as provided in the embodiments of this application.

[0028] Figure 11 This is a schematic diagram of the cross-sectional structure of the weld joint after its formation, provided in an embodiment of this application.

[0029] Figure 12 This is a cross-sectional structural diagram of the micro light-emitting device provided in the embodiments of this application. Detailed Implementation

[0030] The embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be particularly noted that the following embodiments are only used to illustrate the embodiments of this application and do not limit the scope of the embodiments of this application. Similarly, the following embodiments are only some embodiments of the embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the embodiments of this application.

[0031] When describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between itself and the other layer or region. Furthermore, if the component is flipped, the layer or region will be located "below" or "under" the other layer or region. Additionally, the features, structures, or characteristics described below can be combined in any suitable manner in one or more embodiments. It should be understood that in the description of this application, terms such as "first" and "second" are used only to distinguish similar objects and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0032] Furthermore, the directional terms mentioned in the embodiments of this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding the embodiments of this application, and not for limiting the embodiments of this application. In the various drawings, structurally similar units are represented by the same reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some related parts may not be shown in the drawings.

[0033] With the continuous development of Micro-LED display technology, it is gradually moving towards smaller size, higher brightness, and greater integration. During miniaturization, the reduction in pixel unit size leads to a corresponding increase in the proportion of light emitted from its sidewalls. This results in increasingly prominent optical crosstalk between adjacent pixel units caused by sidewall light emission, severely restricting the improvement of imaging quality and display performance of high-resolution Micro-LED display devices. Furthermore, the height difference between the cathode and anode in flip-chip structures can easily cause poor bonding contacts, affecting device reliability. In common-cathode or common-anode structures, differences in current paths lead to uneven brightness between the central and peripheral regions (i.e., the outer periphery), a problem particularly pronounced in semiconductor materials with high resistivity.

[0034] To address the aforementioned problems, this application provides a micro-light-emitting structure comprising a pixel array having multiple pixel units. Each pixel unit includes a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and a first electrode stacked sequentially, as well as a second electrode disposed in the outer peripheral region of the pixel array. A metal wall is disposed within the pixel array, forming an isolation structure between adjacent pixel units. The top surface of the metal wall is flush with the top surface of the first electrode, and the height of the metal wall is greater than the sidewall height of the light-emitting layer. The metal wall is integrally connected to the second electrode to form a conductive network. Thus, by setting the height of the metal wall to be greater than the sidewall height of the light-emitting layer, lateral light emission is effectively blocked, avoiding optical crosstalk between pixel units. Simultaneously, the top surface of the metal wall and the top surface of the first electrode remain flush, ensuring that the bonding layer can simultaneously form reliable contact with the first electrode and the second electrode (i.e., the common electrode), avoiding problems such as poor soldering or open circuits caused by height differences. Furthermore, compared to the related technologies where the second electrode is set as a common electrode in the peripheral area, which causes the current to be transmitted from the pixel unit in the central area to the peripheral area in the distance (the path is long and a high resistance difference is generated), this application significantly shortens the current transmission path and reduces the resistance difference by integrally connecting the metal wall and the second electrode to form a conductive network, thereby effectively improving the problem of uneven brightness between the central area and the peripheral area of ​​the display device in the related technologies.

[0035] The following detailed description is based on specific embodiments. It should be noted that the embodiments of this application can be presented in various forms, and some examples will be described below.

[0036] Please see Figure 1 and Figure 3 , Figure 1 This is a cross-sectional schematic diagram of the micro-light-emitting structure provided in the embodiments of this application. Figure 3 This is a top view schematic diagram of a pixel array for a micro-light-emitting structure provided in an embodiment of this application. Figure 1 and Figure 3 As shown, the micro light-emitting structure 10 includes a pixel array 300, which has multiple pixel units 301. Each pixel unit 301 includes a first semiconductor layer 130, a light-emitting layer 140, a second semiconductor layer 150, and a first electrode 170, which are stacked sequentially.

[0037] In this embodiment, each pixel unit 301 is specifically a gallium nitride mesa structure (GaN MESA). The mesa structure 302 includes a first semiconductor layer 130, a light-emitting layer 140, a second semiconductor layer 150, and a first electrode 170 sequentially stacked on a first substrate 110. The first substrate 110 supports the film structure thereon. The first substrate 110 can be a transparent substrate or a non-transparent substrate; the transparent substrate is specifically a sapphire substrate or a quartz substrate, and the non-transparent substrate is specifically a silicon substrate or a silicon carbide substrate. Figure 1 In the illustrated embodiment, the first substrate 110 is a sapphire substrate. The light-emitting layer 140 is a quantum well layer, for example, an indium gallium nitride (IGaN) quantum well layer or an IGaN / GaN multi-quantum well layer. The first semiconductor layer 130 is one of an N-type semiconductor layer and a P-type semiconductor layer, and the second semiconductor layer 150 is the other of an N-type semiconductor layer and a P-type semiconductor layer, wherein the N-type semiconductor layer is an N-type gallium nitride layer or an N-type gallium arsenide layer, and the P-type semiconductor layer is a P-type gallium nitride layer or a P-type aluminum gallium nitride layer. Figure 1 In the illustrated embodiment, the first semiconductor layer 130 is an N-type semiconductor layer, and the second semiconductor layer 150 is a P-type semiconductor layer. The first electrode 170 is disposed on the side of the second semiconductor layer 150 opposite to the light-emitting layer 140 and is electrically connected to the second semiconductor layer 150.

[0038] like Figure 1 As shown, the micro-light-emitting structure 10 also includes a buffer layer 120. The buffer layer 120 can alleviate the stress caused by lattice mismatch and thermal expansion coefficient mismatch between its upper film layer and the first substrate 110, thereby improving the reliability and lifespan of the micro-light-emitting structure 10. The material of the buffer layer 120 may include buffer materials such as silicon nitride, silicon oxide, gallium nitride, or aluminum nitride. In this embodiment, the buffer layer 120 is made of unintentionally doped gallium nitride (U-GaN) material and is disposed on the first substrate 110. The thickness of the buffer layer 120 is 1 to 3 micrometers, which can ensure sufficient stress buffering effect while also helping to control the overall thickness of the micro-light-emitting structure 10.

[0039] like Figure 3 As shown, the micro-light-emitting structure 10 also includes a second electrode 180, which is disposed in the outer peripheral region of the pixel array 300 and serves as the common electrode for all pixel units 301. Specifically, the second electrode 180 is a ring-shaped electrode structure surrounding the entire pixel array 300 to ensure uniform current distribution and effectively reduce current congestion. In this embodiment, the second electrode 180 is an N-type electrode (cathode), and the first electrode 170 is a P-type electrode (anode). The two electrodes together form a current transmission path. When an appropriate voltage is applied, current flows from the first electrode 170 to the second electrode 180, driving the micro-light-emitting structure 10 to emit light efficiently and stably.

[0040] Please refer to the following: Figure 1 and Figure 3 In the pixel array 300 of the micro-light-emitting structure 10, a metal wall 190 is disposed in the channel region S1 between adjacent pixel units 301. Further, the metal wall 190 forms an isolation structure between adjacent pixel units 301. Specifically, in the central region of the pixel array 300, the metal wall 190 forms a closed, continuous mesh structure surrounding each pixel unit 301, so that the sidewalls of the light-emitting layer 140 of each pixel unit 301 are completely surrounded by the metal wall 190, thereby achieving optical isolation between adjacent pixel units 301, while also providing a current transmission path. In the edge region of the pixel array 300, the metal wall 190 extends only at the two or three sides of the pixel unit 301 facing inwards from the pixel array 300, and is not disposed on one or both sides facing outwards from the pixel array 300, thus forming a non-closed structure. The non-closed structure formed by the metal wall 190 in the edge region extends directly to the outer periphery of the pixel array 300 and is integrally connected to the second electrode 180 disposed in the outer periphery region. Thus, the closed grid structure in the central region of the metal wall 190 and the non-closed structure in the edge region together form a conductive network that runs through the entire pixel array 300.

[0041] In some embodiments, the width of the metal wall 190 is greater than or equal to 50% and less than or equal to 80% of the channel spacing between adjacent pixel units 301. This ratio includes 50%, 55%, 60%, 68%, 72%, or 80%. This width range of the metal wall 190 maximizes the effective light-emitting area of ​​the pixel units 301 while ensuring sufficient mechanical strength, thereby optimizing overall display efficiency. Through the above structural design, the metal wall 190 in the central region utilizes its surrounding layout to form an all-around optical shield for the sidewalls of the light-emitting layer 140, effectively suppressing optical crosstalk between adjacent pixel units 301. Simultaneously, the metal wall 190 forms a current transmission path, helping to improve the uniformity of current distribution. Meanwhile, the non-closed structure formed by the metal wall 190 in the edge region maintains local optical isolation performance while being integrated with the second electrode 180, improving the uniformity of display brightness of the micro-light-emitting structure 10, as well as enhancing color contrast and response speed.

[0042] The metal wall 190, as an extension of the second electrode 180, is distributed among the pixel units 301 in the pixel array 300 region. The metal wall 190 is integrally connected with the second electrode 180, forming a complete conductive network. This structure can significantly reduce resistance loss and improve current transmission efficiency. It should be noted that the metal wall 190 and the second electrode 180 are made of the same material and are fabricated in the same process step (see the description below), ensuring structural integrity and electrical connectivity while simplifying the fabrication process.

[0043] In this embodiment, the top surface of the metal wall 190 is flush with the top surface of the first electrode 170, and the height of the metal wall 190 is greater than the sidewall height of the light-emitting layer 140, enabling the metal wall 190 to effectively block lateral light leakage and reduce optical crosstalk between pixel units 301. In some embodiments, the width of the metal wall 190 is greater than or equal to 0.5 times the width of the pixel unit 301 to provide an appropriate current transmission cross-sectional area, achieving optical isolation between adjacent pixel units 301, while maintaining structural strength and meeting the manufacturing process requirements and effective light-emitting area of ​​the micro-light-emitting structure 10. In some embodiments, the ratio of the height of the metal wall 190 to the sidewall height of the light-emitting layer 140 is greater than or equal to 1.15 and less than or equal to 1.25, effectively reducing the lateral light leakage rate. In some specific embodiments, the height of the metal wall 190 can be 1.15 times, 1.18 times, 1.20 times, 1.23 times, or 1.25 times the sidewall height of the light-emitting layer 140. In some embodiments, the lateral spacing between the sidewall of the metal wall 190 and the sidewall of the light-emitting layer 140 is greater than or equal to 1.0 micrometer and less than or equal to 1.5 micrometer, which avoids crosstalk caused by light diffraction and facilitates the stable implementation of coating processes (e.g., deposition of an insulating layer). In some specific embodiments, the lateral spacing between the sidewall of the metal wall 190 and the sidewall of the light-emitting layer 140 can be 1.0 micrometer, 1.1 micrometer, 1.3 micrometer, 1.4 micrometer, or 1.5 micrometer.

[0044] In some embodiments, the metal wall 190 is formed by directly depositing a suitable metal material, such as an aluminum / titanium / aluminum (Al / Ti / Al) composite layer or a gold / titanium (Au / Ti) composite layer, on the first semiconductor layer 130 located in the channel region S1 through a single photolithography and metal deposition process. This metal wall 190 forms a good ohmic contact with the first semiconductor layer 130 (i.e., the N-type semiconductor layer). The aforementioned metal material possesses good conductivity and reflectivity, effectively transmitting current and reflecting laterally scattered light, thereby improving light extraction efficiency and current distribution uniformity.

[0045] In other embodiments, the metal wall 190 is formed through a two-stage deposition process. Specifically, a material with high conductivity, such as a titanium / aluminum (Ti / Al) alloy, gold (Au), or platinum (Pt), is first deposited to form a first metal layer 191 with high conductivity. Then, a material with high reflectivity, such as aluminum (Al) or gold (Au), is deposited to form a second metal layer 192 with high reflectivity, thereby constituting a two-layer structure. Please refer to [link to previous document]. Figure 2 , Figure 2 This is a schematic diagram showing the structural relationship between the metal wall and the first semiconductor layer of the micro-light-emitting structure provided in this application embodiment. Figure 2 In the illustrated embodiment, the first metal layer 191 is disposed on the side close to the first semiconductor layer 130, and the second metal layer 192 is disposed on the side away from the first semiconductor layer 130. This dual-layer structure enables the metal wall 190 to possess both good conductivity and reflectivity. Furthermore, the bottom of the first metal layer 191 includes a conductive contact portion (not shown) that extends into the interior of the first semiconductor layer 130 and forms an ohmic contact with it, reducing contact resistance and thereby improving the electrical performance of the micro-light-emitting structure 10. The second metal layer 192 is used to reflect laterally scattered light and guide it back to the light-emitting area to improve light extraction efficiency. For example, the thickness ratio of the second metal layer 192 to the first metal layer 191 is 9:1 or 8:2. This thickness ratio optimizes the reflection effect while ensuring sufficient conductivity.

[0046] As mentioned above, based on the specific structural design of the metal wall 190, by setting the metal wall 190 between adjacent pixel units 301, and ensuring that the height of the metal wall 190 is greater than the height of the light-emitting layer 140 of the pixel unit 301, the lateral light emission of the light-emitting layer 140 can be effectively blocked, avoiding optical crosstalk and thus improving the contrast and color purity of the display device. Furthermore, by making the top surface of the metal wall 190 flush with the top surface of the first electrode 170, a uniform electrical connection is formed between the bonding layer and the first electrode 170 and the second electrode 180 in subsequent processes, avoiding solder joint defects or open circuits caused by height differences, thereby improving the manufacturing yield and reliability of the display device. Since the metal wall 190 is a continuation of the second electrode 180, the second electrode 180 and the metal wall 190 are integrally connected to form a complete conductive network. This integrated structure reduces the number of fabrication steps while improving the uniformity of current distribution and the mechanical stability of the structure, thereby enhancing the electrical reliability of the display device during long-term operation. Furthermore, compared to the case in related technologies where the second electrode 180 is a common electrode far from the center of the pixel, where the current needs to be transmitted from the first electrode 170 in the pixel unit 301 in the center to the second electrode 180 in the surrounding area, this long transmission path will cause a resistance gradient in the circuit. However, this application uses the metal wall 190 as a continuation of the second electrode 180, and the second electrode 180 and the metal wall 190 are connected as a whole to form a conductive network, which significantly shortens the current transmission distance and effectively reduces the resistance difference. This can significantly improve the problem of uneven brightness between the center and the surrounding area of ​​the display device in related technologies, and provide a more uniform display effect.

[0047] To achieve effective isolation between electrodes while maintaining the aforementioned effects, the micro-light-emitting structure 10 further includes an insulating layer 210. The insulating layer 210 may be made of at least one of insulating materials such as silicon oxide, silicon nitride, and aluminum oxide. The insulating layer 210 covers the surface of the pixel array 300, the metal wall 190, and the area between the pixel array 300 and the second electrode 180, effectively preventing leakage and short circuits between different electrodes. In some embodiments, a contact hole 211 is provided in the insulating layer 210, penetrating the thickness of the insulating layer 210, and located in the connection area between the first electrode 170 and the second electrode 180, so that the first electrode 170 and the second electrode 180 are electrically connected through the contact hole 211, thereby achieving electrical communication between the electrodes and improving the mechanical strength of the overall structure. It should be noted that... Figure 3 The area referred to by the numeral 250 is the area in the micro light-emitting structure 10 where the pixel array 300 is not formed. This area 250 includes a first semiconductor layer 130 and is covered with an insulating layer 210 for electrical and structural isolation from the pixel array 300 area.

[0048] Furthermore, to optimize the electrical performance of the metal wall 190, the bottom of the metal wall 190 is in direct contact with the first semiconductor layer 130, and the insulating layer 210 is not covered in the contact area between the metal wall 190 and the first semiconductor layer 130, to ensure low-impedance contact between the metal wall 190 and the first semiconductor layer 130 and reduce interface resistance. Simultaneously, the first electrode 170 is isolated from the metal wall 190 by the insulating layer 210, effectively preventing short circuits between electrodes of different polarities and improving the stability and reliability of the micro-light-emitting structure 10.

[0049] In some embodiments, to further improve photoelectric conversion efficiency, the micro-light-emitting structure 10 further includes a transparent conductive layer 160, which is disposed between the second semiconductor layer 150 and the first electrode 170. The transparent conductive layer 160 can be made of a transparent material such as indium tin oxide (ITO) or indium gallium zinc oxide (IGZO). By using the aforementioned transparent material, a combination of electrical conductivity and optical transmittance is achieved, allowing the light emitted by the light-emitting layer 140 to pass through effectively, thereby improving the luminous efficiency and brightness of the micro-light-emitting structure 10.

[0050] Please see Figures 4 to 11 , Figure 4 This is a schematic flowchart illustrating the fabrication method of the micro-luminescent structure 10 provided in this application embodiment. The following will be illustrated in conjunction with the attached diagram. Figures 4 to 11 The preparation method of the aforementioned microluminescent structure 10 is described.

[0051] See also Figure 5 Step S310: Provide a first substrate 110; sequentially form a buffer layer 120, a first semiconductor layer 130, a light-emitting layer 140, a second semiconductor layer 150 and a transparent conductive layer 160 on the first substrate 110, wherein the first semiconductor layer 130 is an N-type semiconductor layer and the second semiconductor layer 150 is a P-type semiconductor layer.

[0052] In this step, a first substrate 110 is used to support the film structure thereon. The first substrate 110 can be a transparent substrate or a non-transparent substrate. Specifically, a transparent substrate is a sapphire substrate or a quartz substrate, and a non-transparent substrate is a silicon substrate or a silicon carbide substrate. In this embodiment, the first substrate 110 is a sapphire substrate. A buffer layer 120 of 1 to 3 micrometers is formed on the sapphire substrate. The material of the buffer layer 120 can be unintentionally doped gallium nitride (U-GaN) material, but it is not limited to this. It can also be a buffer material such as silicon oxide, gallium nitride, or aluminum nitride. The buffer layer 120 can effectively alleviate the stress caused by lattice mismatch and thermal expansion coefficient mismatch between the film layer on it and the first substrate 110, thereby improving the reliability and lifespan of the micro light-emitting structure 10. Next, a first semiconductor layer 130 is formed on the buffer layer 120. In this embodiment, the first semiconductor layer 130 is N-type gallium nitride (N-GaN), which serves as an electron transport layer. A quantum well light-emitting layer 140 (MQWs) is formed on the first semiconductor layer 130. This light-emitting layer 140 can be an indium gallium nitride (IGaN) quantum well layer or an IGaN / GaN multi-quantum well layer, serving as the active region to generate photons. A second semiconductor layer 150 is formed on the light-emitting layer 140. In this embodiment, the second semiconductor layer is p-type gallium nitride (P-GaN), which serves as a hole transport layer, completing the PN structure. A transparent conductive layer 160 is formed on the second semiconductor layer 150. In this step, the transparent conductive layer 160 is deposited and formed on the surface of the second semiconductor layer 150 (i.e., the p-type semiconductor layer) using a sputtering or evaporation process. The transparent conductive layer 160 is made of indium tin oxide (ITO). This transparent conductive layer 160 has good conductivity and maintains high light transmittance, effectively enhancing the lateral current diffusion capability of the second semiconductor layer 150, reducing ohmic contact resistance, and allowing the light emitted by the light-emitting layer 140 to pass through effectively, thereby improving the luminous efficiency, brightness uniformity, and overall light extraction efficiency of the micro-light-emitting structure 10. The thickness of the transparent conductive layer 160 is typically controlled within the range of 50 to 200 nanometers to balance conductivity and light transmittance.

[0053] See also Figure 6 Step S320: Patterning and etching the transparent conductive layer 160, the second semiconductor layer 150, the light-emitting layer 140 and the first semiconductor layer 130 to form a mesa structure 302 of multiple pixel units 301, and forming a channel region S1 between adjacent pixel units 301, so that the channel region S1 extends to the first semiconductor layer 130 and exposes a portion of the first semiconductor layer 130.

[0054] In this step, photoresist is applied to the predetermined formation areas of the first electrode 170 and the second electrode 180, as well as the light-emitting area of ​​the mesa structure 302, for protection using photolithography. Then, dry etching techniques (such as reactive ion etching or inductively coupled plasma etching) are used to selectively etch the transparent conductive layer 160, the second semiconductor layer 150 (i.e., the P-type semiconductor layer), the light-emitting layer 140, and the first semiconductor layer 130 (i.e., the N-type semiconductor layer) simultaneously, forming the gallium nitride mesa structure and the pixel array 300. During etching, the etching depth is controlled to a portion of the first semiconductor layer 130, exposing part of the first semiconductor layer 130 in the channel region S1, providing a basis for the subsequent formation of the second electrode 180 (i.e., the N-type electrode) and the metal wall 190. This etching process creates physical isolation between the pixel units 301, reducing electrical and optical crosstalk between adjacent pixel units 301 to some extent.

[0055] See also Figure 7 Step S330: Form a first electrode 170 on the surface of the pixel unit 301 of the mesa structure 302.

[0056] In this step, the pattern of the first electrode 170 is defined on the transparent conductive layer 160 using photolithography. Then, a first electrode material, such as a highly reflective metal like nickel / gold (Ni / Au), aluminum (Al), or silver (Ag), is deposited using processes like evaporation or sputtering to form the first electrode 170. The thickness of the first electrode 170 can be 200–500 nanometers to ensure good conductivity. Notably, the first electrode 170 is deposited on top of the MESA-etched mesa structure 302 (i.e., on the transparent conductive layer 160 which has already been etched), with its initial deposition plane located at the highest point of the micro-light-emitting structure 10. This structural configuration of the first electrode 170 allows current to diffuse uniformly through the transparent conductive layer 160 to the entire second semiconductor layer 150, reducing current congestion and improving current injection efficiency, while avoiding the high contact resistance problem that might result from directly forming a metal electrode on the second semiconductor layer 150.

[0057] See also Figure 8 Step S340: Form a metal wall 190 and a second electrode 180 on the first semiconductor layer 130 of the channel region S1 and the outer peripheral region of the pixel array 300.

[0058] In this step, patterns of a metal wall 190 and a second electrode 180 are defined on the first semiconductor layer 130 of the channel region S1 and the outer periphery of the pixel array 300 using a photolithography process, followed by metal deposition. The metal wall 190 needs to be deposited on the first semiconductor layer 130 within the channel region S1 formed after MESA etching. Since the MESA etching causes the initial deposition plane in this region to be lower than the initial deposition plane of the first electrode 170, the total deposition thickness of the metal wall 190 must be greater than that of the first electrode 170 to achieve a height flush with the top of the first electrode 170.

[0059] In one embodiment of this step, a suitable metal material, such as an aluminum / titanium / aluminum (Al / Ti / Al) composite layer or a gold / titanium (Au / Ti) composite layer, is directly deposited on the first semiconductor layer 130 located in the channel region S1 and the outer periphery of the pixel array 300 through a single photolithography and metal deposition process. This forms a metal wall 190 and a second electrode 180 that form a good ohmic contact with the first semiconductor layer 130 (i.e., the N-type semiconductor layer). The aforementioned metal material has good conductivity and reflection characteristics, which can effectively transmit current and reflect laterally scattered light, thereby improving light extraction efficiency and current distribution uniformity.

[0060] In another embodiment, a two-stage deposition process can be employed: first, a material with high conductivity, such as a titanium / aluminum (Ti / Al) alloy, gold (Au), or platinum (Pt), is deposited to form a first metal layer with high conductivity; then, a material with high reflectivity, such as aluminum (Al) or gold (Au), is deposited to form a second metal layer with high reflectivity. The thickness ratio of the two layers is 9:1 or 8:2.

[0061] It is worth noting that, compared to the simultaneous deposition of P-type and N-type electrodes or the deposition of a single thickness used in related technologies, in the fabrication process of the micro-light-emitting structure 10 of this application, the first electrode 170 (i.e., the P-type electrode), the second electrode 180 (i.e., the N-type electrode), and the metal wall 190 are deposited in stages with different thicknesses. The first electrode 170 and the metal wall 190 (as an extension of the second electrode 180) are deposited at different thicknesses through the aforementioned photolithography and coating processes. Since the metal wall 190 needs to fill the height difference formed by MESA etching, its total thickness must be greater than that of the first electrode 170, making it impossible for the metal wall 190 to be deposited simultaneously with the first electrode 170. Although the total deposition thickness of the metal wall 190 is greater than that of the first electrode 170, due to the height difference between their initial deposition planes, the top surface of the final metal wall 190 can remain flush with the top surface of the first electrode 170. The metal wall 190 and the second electrode 180 are made of the same material and are integrally connected to form a complete conductive network, which significantly shortens the current transmission distance, effectively reduces the resistance difference, and thus improves the brightness uniformity of the micro light-emitting structure 10.

[0062] It should be noted that, in this embodiment, the lateral spacing between the sidewall of the metal wall 190 and the sidewall of the light-emitting layer 140 is greater than or equal to 1.0 micrometer and less than or equal to 1.5 micrometer, which can avoid crosstalk caused by light diffraction and facilitate the stable implementation of the etching process.

[0063] See also Figure 9 Step S350: Deposit insulating layer 210 on first electrode 170 and second electrode 180, and pattern insulating layer 210 to form contact hole 211.

[0064] In this step, after the deposition of the first electrode 170 and the second electrode 180, an insulating layer (also called a passivation layer) is deposited on the entire surface of the micro-light-emitting structure 10 using techniques such as plasma-enhanced chemical vapor deposition (PECVD). The insulating layer 210 can be made of silicon nitride, silicon oxide, or a combination thereof. The insulating layer 210 covers the entire micro-light-emitting structure 10, including the formed first electrode 170, second electrode 180, metal wall 190, and other exposed areas. The insulating layer 210 achieves surface passivation of the micro-light-emitting structure 10, preventing interface oxidation and metal migration during subsequent processes, while also providing electrical insulation.

[0065] Subsequently, through a passivation via (PV) process, selective etching is performed on the bonding region (not shown in the figure) of the insulating layer 210 to form contact holes 211 (i.e., bonding regions). This facilitates the subsequent formation of solder joints and the bonding layer in this region, enabling electrical connection with the first electrode 170 and the second electrode 180. This via process employs precise photolithography and dry etching techniques to ensure the dimensional and positional accuracy of the contact holes 211, providing a contact channel for subsequent electrical interconnection.

[0066] See also Figure 10 and Figure 11 In some embodiments, the fabrication method of the micro-light-emitting structure 10 further includes: step S360: forming a solder patch underlayer 220 and solder points 230 in the contact hole 211 region. In this step, conductive material is first deposited in the contact hole 211 region by processes such as electroplating or sputtering to form a solder patch underlayer 220 (UBM, Under Bump Metallurgy). The solder patch underlayer 220 can be made of conductive materials such as gold, titanium / gold, or titanium / platinum / gold to enhance the adhesion and stability of subsequent solder points. After the solder patch underlayer 220 is deposited, solder points 230 are formed on this layer. The solder points 230 can be made of metals such as gold (Au), tin (Tin), or indium (In), which have good conductivity and bonding performance.

[0067] Because the top surfaces of the first electrode 170 and the second electrode 180 are flush, the solder joint 230 can form a uniform electrical connection with the first electrode 170 and the second electrode 180 through the solder joint underlay 220, avoiding problems such as poor soldering or open circuits caused by height differences, and significantly improving the manufacturing yield and reliability of the micro-light-emitting structure 10. In addition, the solder joint 230 (as a bonding layer) also helps with subsequent bonding connections to the driving substrate 300. At the same time, the solder joint underlay 220 and the solder joint 230 can act as protective layers to prevent electrode oxidation or corrosion and extend the service life of the micro-light-emitting structure 10.

[0068] Optionally, in some embodiments, the fabrication method of the micro-light-emitting structure 10 further includes thinning the first substrate 110. This step is used to improve light extraction efficiency. In this step, the back side of the first substrate 110 (sapphire substrate) is thinned by processes such as mechanical grinding and / or chemical mechanical polishing (CMP). The thinned first substrate 110 can not only reduce thermal resistance and improve heat dissipation efficiency, but also reduce light absorption loss within the first substrate 110, thereby improving light extraction efficiency. In addition, the substrate thinning process helps to reduce the overall thickness of the micro-light-emitting structure 10, which is beneficial for subsequent packaging and integration applications.

[0069] Please see Figure 12 , Figure 12This is a schematic cross-sectional view of the micro light-emitting device provided in an embodiment of this application. Figure 12 As shown, the micro light-emitting device 1000 includes a micro light-emitting structure 10 and a driving substrate 300. The micro light-emitting structure 10 is bonded to the driving substrate 300 through a first electrode 170 and a second electrode 180. The micro light-emitting structure is the micro light-emitting structure 10 described above, which will not be repeated here.

[0070] In this embodiment, the micro-light-emitting structure 10 adopts a flip-chip structure with a common N-electrode, wherein the second electrode 180 (N-type electrode) serves as a common electrode shared by all pixel units 301 and extends around each pixel unit 301 through the metal wall 190, forming a complete conductive network. In the micro-light-emitting structure 10, each pixel unit 301 has an independent first electrode 170 (P-type electrode) for individual control, while the first semiconductor layer 130 (i.e., the N-type semiconductor layer) achieves uniform current distribution through the conductive network formed by the second electrode 180 and the metal wall 190. The flip-chip structure allows the micro-light-emitting structure 10 to be flipped during packaging, so that the second semiconductor layer 150 (i.e., the P-type semiconductor layer) faces and connects to the driving circuit of the driving substrate 300, and light is emitted from the side of the flipped, uppermost first semiconductor layer 130, improving light extraction efficiency. This flip-chip structure with a common N-electrode not only simplifies the driving connection but also significantly improves the uniformity of current distribution through the metal wall 190 network, thus solving the problem of uneven brightness between the central and peripheral areas of the micro-light-emitting device 1000. In addition, the common N-electrode design reduces resistance and improves overall electrical performance and power efficiency.

[0071] exist Figure 12 In the illustrated embodiment, the outermost layer of the micro-light-emitting structure 10 away from the driving substrate 300 can be a first semiconductor layer 130. In other words, the micro-light-emitting structure 10 may not include the first substrate 110 and buffer layer 120 in the aforementioned micro-light-emitting structure embodiment, thereby avoiding the first substrate 110 and buffer layer 120 from blocking the light emitted by the light-emitting layer 140, so as to improve the light extraction efficiency.

[0072] The micro-light-emitting structure 10 may further include a passivation layer 240, which covers the micro-light-emitting structure 10 to protect it and thereby improve the reliability of the device. The passivation layer 240 may be made of at least one of insulating materials such as silicon oxide, silicon nitride, and aluminum oxide.

[0073] exist Figure 12In the embodiment shown, the driving substrate 300 may include a second substrate 310, a driving circuit 320, a first driving electrode 330, and a second driving electrode 340. The driving circuit 320 is disposed on the second substrate 310, and the first driving electrode 330 and the second driving electrode 340 are disposed on the same side of the driving circuit 320 away from the second substrate 310, and are both electrically connected to the driving circuit 320.

[0074] Specifically, using the solder joints 230 formed in the aforementioned steps, the first driving electrode 330 is bonded to the first electrode 170 of the aforementioned micro-light-emitting structure 10 as a first bonding point through reflow soldering or hot pressing processes, and the second driving electrode 340 is bonded to the second electrode 180 of the aforementioned micro-light-emitting structure 10 as a second bonding point. In some examples, the material of the first driving electrode 330 may include conductive materials such as titanium (Ti), aluminum (Al), gold (Au), platinum (Pt), and / or nickel (Ni). The material of the second driving electrode 340 may also include conductive materials such as titanium (Ti), aluminum (Al), gold (Au), platinum (Pt), and / or nickel (Ni). Furthermore, in specific implementations, the materials of the first driving electrode 330 and the second driving electrode 340 may be the same, and they may be formed simultaneously.

[0075] In some examples, the driving substrate 300 is an inorganic substrate or an organic substrate. The inorganic substrate may include one of a silicon substrate, a glass substrate, a sapphire substrate, or a silicon carbide substrate, while the organic substrate may include one of a polyimide substrate, a polyethylene terephthalate substrate, or a flexible material substrate. In this embodiment, the driving substrate 300 is a silicon substrate. The driving substrate 300 can be used to drive a chip or a wafer.

[0076] The micro light-emitting device 1000 of this application embodiment has a wide range of applications. It can be used not only in the projection part of electronic devices such as optical projection and vehicle head-up display, but also in the display part of electronic devices, such as smartphones, smartwatches, laptops, tablets, dashcams, navigators, head-mounted devices, and any other devices with a display screen. It can also be used in the lighting part of electronic devices, such as vehicles, streetlights, and any other devices with lighting components.

[0077] It should be noted that the micro light-emitting device 1000 provided in this application embodiment, because it is provided with the micro light-emitting structure 10 provided in this application embodiment, can achieve the beneficial effects that any of the micro light-emitting structures 10 provided in this application embodiment can achieve. For details, please refer to the embodiments above, which will not be repeated here.

[0078] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments.

[0079] It should be noted that the micro light-emitting structure 10 and its preparation method, as well as the micro light-emitting device 1000 of the embodiments of this application, are different subjects under the same inventive concept. Features not described in detail in each embodiment can be referred to in the description of other embodiments.

[0080] It is understood that those skilled in the art, guided by the above embodiments, can combine various implementation methods in the above embodiments to obtain technical solutions with multiple implementation methods. The above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A micro-light-emitting structure, comprising a pixel array having a plurality of pixel units, each pixel unit comprising a first semiconductor layer, a light-emitting layer, a second semiconductor layer and a first electrode stacked sequentially, and a second electrode disposed in the outer peripheral region of the pixel array, characterized in that, The pixel array is provided with a metal wall, which forms an isolation structure between adjacent pixel units. The top surface of the metal wall is flush with the top surface of the first electrode, and the height of the metal wall is greater than the height of the sidewall of the light-emitting layer. The metal wall is integrally connected with the second electrode to form a conductive network.

2. The micro-light-emitting structure as described in claim 1, characterized in that, The metal wall includes a first metal layer and a second metal layer, wherein the first metal layer is disposed close to the first semiconductor layer and the second metal layer is disposed away from the first semiconductor layer, wherein the first metal layer is made of a high conductivity material and the second metal layer is made of a high reflectivity material.

3. The micro-light-emitting structure as described in claim 2, characterized in that, The bottom of the first metal layer includes a conductive contact portion, which extends into the interior of the first semiconductor layer and forms an ohmic contact with the first semiconductor layer; the material of the conductive contact portion is a titanium-aluminum alloy.

4. The micro-light-emitting structure as described in claim 1, characterized in that, The second electrode is a ring-shaped electrode arranged around the pixel array.

5. The micro-light-emitting structure as described in claim 1, characterized in that, The micro-light-emitting structure further includes an insulating layer covering the surface of the pixel array, the metal wall, and the area between the pixel array and the second electrode; the first electrode and the metal wall are isolated by the insulating layer.

6. The micro-light-emitting structure as described in claim 5, characterized in that, The insulating layer is provided with a contact hole, which is located in the connection area between the first electrode and the second electrode, so that the first electrode and the second electrode are electrically connected through the contact hole.

7. The micro-light-emitting structure as described in claim 5, characterized in that, The bottom of the metal wall is in direct contact with the first semiconductor layer, and the insulating layer does not cover the contact area between the metal wall and the first semiconductor layer.

8. The micro-light-emitting structure as described in claim 1, characterized in that, The width of the metal wall is greater than or equal to 50% and less than or equal to 80% of the channel spacing between adjacent pixel units.

9. The micro-light-emitting structure as described in claim 1, characterized in that, The lateral distance between the sidewall of the metal wall and the sidewall of the light-emitting layer is greater than or equal to 1.0 micrometer and less than or equal to 1.5 micrometer.

10. The micro-light-emitting structure as described in claim 1, characterized in that, It also includes a transparent conductive layer disposed between the second semiconductor layer and the first electrode, wherein the transparent conductive layer is made of indium tin oxide or indium gallium zinc oxide.

11. A miniature light-emitting device, characterized in that, It includes the micro light-emitting structure and driving substrate as described in any one of claims 1-10; the driving substrate is a silicon substrate, and a first bonding point and a second bonding point are disposed on the silicon substrate, the first bonding point being bonded to the first electrode and the second bonding point being bonded to the second electrode.

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