Display panel and display device

Abstract

The utility model discloses a display panel and a display device for improving display image quality. The display panel comprises a substrate, a plurality of sub-pixels arranged on the substrate, a plurality of data lines, a plurality of data connecting lines, a plurality of data outgoing lines and at least one first shielding signal line. The plurality of data lines comprise a plurality of first-class data lines and a plurality of second-class data lines, and the plurality of second-class data lines are electrically connected with the plurality of data connecting lines. The plurality of data outgoing lines comprise a plurality of first-class data outgoing lines and a plurality of second-class data outgoing lines, the plurality of first-class data outgoing lines are electrically connected with the plurality of first-class data lines, and the plurality of second-class data outgoing lines are electrically connected with the plurality of second-class data lines through the plurality of data connecting lines. The at least one first shielding signal line is configured to be at least one first type data lead-out line and at least one second type data lead-out line which are used for transmitting data signals to different types of sub-pixels in a separated mode.

Description

Technical Field

[0001] This utility model relates to, but is not limited to, the field of display technology, and particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Utility Model Content

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] To address the problem of poor display quality caused by signal coupling in the display panel, this utility model provides a display panel and a display device.

[0005] On one hand, this embodiment provides a display panel, including: a substrate, a plurality of sub-pixels disposed on the substrate, a plurality of data lines, a plurality of data connection lines, a plurality of data lead-out lines, and at least one first shielding signal line. The substrate includes a display area and a first border area located on one side of the display area along a first direction. The plurality of sub-pixels are located in the display area, and the plurality of sub-pixels include a plurality of first-type sub-pixels and a plurality of second-type sub-pixels. The plurality of data lines and the plurality of data connection lines are located in the display area, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels. The plurality of data lines include a plurality of first-type data lines and a plurality of second-type data lines, and the plurality of second-type data lines are electrically connected to the plurality of data connection lines. The plurality of data lead-out lines are located in the first border area, including a plurality of first-type data lead-out lines and a plurality of second-type data lead-out lines. The plurality of first-type data lead-out lines are electrically connected to the plurality of first-type data lines, and the plurality of second-type data lead-out lines are electrically connected to the plurality of second-type data lines through the plurality of data connection lines. At least one first shielded signal line is located in the first border area. The at least one first shielded signal line is configured to separate at least one first type data lead and at least one second type data lead. The at least one first type data lead and the at least one second type data lead separated by the at least one first shielded signal line are configured to provide signals to different types of sub-pixels.

[0006] In some exemplary embodiments, the orthographic projection of the at least one first shielding signal line on the substrate lies between the orthographic projections of the at least one first-class data lead and the at least one second-class data lead that transmit data signals to different types of sub-pixels on the substrate.

[0007] In some exemplary embodiments, the orthographic projection of the at least one first shielded signal line on the substrate does not overlap with the orthographic projections of the at least one first-class data lead and the at least one second-class data lead that are separated on the substrate.

[0008] In some exemplary embodiments, the at least one first shielded signal line and adjacent data leads are alternately arranged in different conductive layers.

[0009] In some exemplary embodiments, the display panel includes: a first gate metal layer and a second gate metal layer disposed sequentially on the substrate, wherein at least one first shielded signal line and an adjacent data lead are alternately arranged on the first gate metal layer and the second gate metal layer.

[0010] In some exemplary embodiments, four second-class data leads are provided between at least two adjacent first shielded signal lines.

[0011] In some exemplary embodiments, in a direction perpendicular to the display panel, the at least one first shielded signal line is located between the at least one first type data lead and the at least one second type data lead; the orthographic projection of the at least one first shielded signal line on the substrate at least partially overlaps with the orthographic projections of the at least one first type data lead and the at least one second type data lead on the substrate.

[0012] In some exemplary embodiments, the display panel includes: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer sequentially disposed on the substrate; the at least one first shielded signal line is located in the first source-drain metal layer. Alternatively, the at least one first type data lead is located in the first gate metal layer or the second gate metal layer, and the at least one second type data lead is located in the second source-drain metal layer; or, the at least one second type data lead is located in the first gate metal layer or the second gate metal layer, and the at least one first type data lead is located in the second source-drain metal layer.

[0013] In some exemplary embodiments, the plurality of first-class sub-pixels includes: a plurality of red sub-pixels and a plurality of blue sub-pixels; the plurality of second-class sub-pixels includes a plurality of green sub-pixels.

[0014] In some exemplary embodiments, the data connection line includes: a first data connection segment extending along a second direction and a second data connection segment extending along the first direction, the second direction intersecting the first direction; the first data connection segment of the data connection line is electrically connected to a second type of data line and the second data connection segment, respectively. The display panel further includes: at least one second shielded signal line located in the display area, the orthographic projection of the at least one second shielded signal line onto the substrate being at least partially located between the orthographic projections of the at least one first type of data line and the second data connection segment of the at least one data connection line onto the substrate, the at least one second shielded signal line being configured to transmit a constant voltage signal.

[0015] In some exemplary embodiments, the pixel circuits of the plurality of sub-pixels are electrically connected to a first initial signal line and a second initial signal line, and the at least one second shielded signal line is configured to be electrically connected to either the first initial signal line or the second initial signal line.

[0016] In some exemplary embodiments, the at least one second shielded signal line includes: a plurality of adapter wires extending along the first direction and alternately connected, the plurality of adapter wires being alternately arranged in different conductive layers.

[0017] In some exemplary embodiments, the pixel circuits of the plurality of sub-pixels are divided into multiple groups along the second direction. Each group of pixel circuits includes two pixel circuits symmetrically arranged about the centerline extending along the first direction of the group of pixel circuits. The orthographic projection of at least one group of pixel circuits on the substrate overlaps with the orthographic projection of at least two second data connection segments on the substrate. The data lines connected to the at least one group of pixel circuits are located on both sides of the at least two second data connection segments along the second direction.

[0018] In some exemplary embodiments, the second data connection segment and the plurality of data lines are in the same layer, and the first data connection segment is located on the side of the second data connection segment closer to the substrate.

[0019] In some exemplary embodiments, the connection vias between the first data connection segment and the second type of data line, and the connection vias between the first data connection segment and the second data connection segment, are arranged in a V-shape on the orthographic projection of the substrate.

[0020] In some exemplary embodiments, the at least one first shielded signal line is configured to transmit an electrical signal.

[0021] On the other hand, this embodiment provides a display panel, including: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data connection lines, and at least one second shielding signal line. The substrate includes a display area. The plurality of sub-pixels are disposed on the substrate and located in the display area, and at least one of the plurality of sub-pixels includes a pixel circuit. The plurality of data lines and the plurality of data connection lines are located in the display area, and the plurality of data lines are electrically connected to the pixel circuits of the plurality of sub-pixels. The plurality of data lines include: a plurality of first-type data lines and a plurality of second-type data lines extending along a first direction; the at least one data connection line includes: a first data connection segment extending along a second direction and a second data connection segment extending along the first direction, the first direction intersecting the second direction; the first data connection segment of the at least one data connection line is electrically connected to a second-type data line and the second data connection segment, respectively. The at least one second shielding signal line is located in the display area, and the orthographic projection of the at least one second shielding signal line on the substrate is at least partially located between the orthographic projections of the at least one first-type data line and the second data connection segment of the at least one data connection line on the substrate.

[0022] In some exemplary embodiments, the at least one second shielded signal line is configured to transmit an electrical signal.

[0023] In some exemplary embodiments, the pixel circuits of the plurality of sub-pixels are electrically connected to a first initial signal line and a second initial signal line; the at least one second shielded signal line is configured to be electrically connected to either the first initial signal line or the second initial signal line.

[0024] In some exemplary embodiments, the at least one second shielded signal line includes: a plurality of adapter wires extending along the first direction and alternately connected, the plurality of adapter wires being alternately arranged in different conductive layers.

[0025] In some exemplary embodiments, the pixel circuits of the plurality of sub-pixels are divided into multiple groups along the second direction. Each group of pixel circuits includes two pixel circuits symmetrically arranged about the centerline extending along the first direction of the group of pixel circuits. The orthographic projection of at least one group of pixel circuits on the substrate overlaps with the orthographic projection of at least two second data connection segments on the substrate. The data lines connected to the at least one group of pixel circuits are located on both sides of the at least two second data connection segments along the second direction.

[0026] In some exemplary embodiments, the second data connection segment and the multiple data lines are in the same layer, and the first data connection segment is located on the side of the second data connection segment closer to the substrate.

[0027] In some exemplary embodiments, the substrate further includes: a first border region located on one side of the display area along the first direction; a pixel unit located in the display area includes: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and two third sub-pixels emitting a third color light. The display panel further includes: a plurality of transition units and a plurality of data leads located in the first border region, the plurality of data leads being electrically connected to the second data connection segments of the plurality of first-type data lines and the plurality of data connection lines through the plurality of transition units; each transition unit includes a plurality of transition electrodes arranged along the second direction. The plurality of data leads are configured to provide data signals to the sub-pixels of the e-th row pixel unit in the display area during a first time period, and to provide data signals to the sub-pixels of the (e+1)-th row pixel unit in the display area during a second time period, where e is an integer greater than 0. During the first time period, the data signals transmitted by the multiple data leads connected to a switching unit are configured to correspond sequentially to the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, and the second sub-pixel; during the second time period, the data signals transmitted by the multiple data leads connected to a switching unit are configured to correspond sequentially to the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, and the first sub-pixel.

[0028] In some exemplary embodiments, the first sub-pixel is a red sub-pixel, the second sub-pixel is a blue sub-pixel, and the third sub-pixel is a green sub-pixel.

[0029] In some exemplary embodiments, a single switching unit includes eight switching electrodes arranged along the second direction, the eight switching electrodes being electrically connected one-to-one with two first-type data leads, four second-type data leads, and two first-type data leads arranged along the second direction.

[0030] In some exemplary embodiments, the eight adapter electrodes are also electrically connected one-to-one with one of the first type data lines, two data connection lines, two first type data lines, two data connection lines and another first type data line arranged along the second direction.

[0031] In some exemplary embodiments, the connection vias between the first data connection segment and the second type of data line, and the connection vias between the first data connection segment and the second data connection segment, are arranged in a V-shape on the orthographic projection of the substrate.

[0032] On the other hand, this embodiment provides a display panel, including: a substrate, multiple pixel units, multiple data lines, multiple data connection lines, multiple data lead-out lines, and multiple adapter units. The substrate includes a display area and a first border area located on one side of the display area along a first direction. The multiple pixel units are located in the display area, and each pixel unit includes a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and two third sub-pixels emitting a third color light. The multiple data lines and multiple data connection lines are located in the display area, and the multiple data lines include: multiple first-type data lines and multiple second-type data lines, which are configured to transmit data signals to the sub-pixels of the multiple pixel units, and the multiple second-type data lines are electrically connected to the multiple data connection lines. The multiple data lead-out lines and multiple adapter units are located in the first border area, and the multiple data lead-out lines are electrically connected to the multiple first-type data lines and the multiple data connection lines through the multiple adapter units; each adapter unit includes multiple adapter electrodes arranged along a second direction, which intersects the first direction. The multiple data leads are configured to provide data signals to the sub-pixels of the e-th row pixel unit within the display area during a first time period, and to provide data signals to the sub-pixels of the (e+1)-th row pixel unit within the display area during a second time period, where e is an integer greater than 0. During the first time period, the data signals transmitted by the multiple data leads connected to a switching unit are configured to sequentially correspond to the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, and the second sub-pixel; during the second time period, the data signals transmitted by the multiple data leads connected to the switching unit are configured to sequentially correspond to the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, and the first sub-pixel.

[0033] In some exemplary embodiments, a single switching unit includes eight switching electrodes arranged along the second direction, the eight switching electrodes being electrically connected one-to-one with two first-type data leads, four second-type data leads, and two first-type data leads arranged along the second direction.

[0034] In some exemplary embodiments, the eight adapter electrodes are also electrically connected one-to-one with one of the first type data lines, two data connection lines, two first type data lines, two data connection lines and another first type data line arranged along the second direction.

[0035] In some exemplary embodiments, at least one data connection line includes: a first data connection segment extending along the second direction and a second data connection segment extending along the first direction, wherein the first data connection segment of the at least one data connection line is electrically connected to a second type of data line and the second data connection segment, respectively. The connection vias between the first data connection segment and the second type of data line, and the connection vias between the first data connection segment and the second data segment, are arranged in a V-shape on the orthographic projection of the substrate.

[0036] On the other hand, this embodiment provides a display device, including the display panel as described above.

[0037] The display panel provided in this embodiment can effectively improve the impact of coupling between different data signals in the first border area on the display quality by setting a first shielded signal line to separate the first type of data lead-out lines and the second type of data lead-out lines that transmit data signals to different types of sub-pixels. This can improve the display quality of the display panel.

[0038] Other features and advantages of this invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. Other advantages of this invention can be realized and obtained by means of the solutions described in the description and drawings. Attached Figure Description

[0039] The accompanying drawings are provided to further understand the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this utility model to explain the technical solution of this utility model, and do not constitute a limitation on the technical solution of this utility model.

[0040] Figure 1 This is a schematic diagram of a display panel according to at least one embodiment of the present invention;

[0041] Figure 2A This is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present invention;

[0042] Figure 2B This is another partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of the arrangement of sub-pixels in the display area of ​​at least one embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of the connection between the data cable and the data connection line of the display panel in at least one embodiment of the present invention;

[0045] Figure 5 This is a schematic diagram of the transmission sequence of a data signal;

[0046] Figure 6 This is a partial planar schematic diagram of the first border area of ​​the display panel according to at least one embodiment of the present invention;

[0047] Figure 7 This is another partial planar schematic diagram of the first border area of ​​the display panel of at least one embodiment of the present invention;

[0048] Figure 8 This is another partial planar schematic diagram of the first border area of ​​the display panel of at least one embodiment of the present invention;

[0049] Figure 9 This is a partial cross-sectional view of the first frame area of ​​the display panel according to at least one embodiment of the present invention;

[0050] Figure 10 This is another partial cross-sectional view of the first bezel area of ​​the display panel according to at least one embodiment of the present invention;

[0051] Figure 11 This is another partial cross-sectional view of the first bezel area of ​​the display panel according to at least one embodiment of the present invention;

[0052] Figure 12 This is an equivalent circuit diagram of the pixel circuit of at least one embodiment of the present invention;

[0053] Figure 13 This is a partial plan view of the display area of ​​the display panel of at least one embodiment of the present invention;

[0054] Figure 14A for Figure 13 A schematic diagram of the display panel after the shielding layer is formed;

[0055] Figure 14B for Figure 13 A schematic diagram of a display panel after a semiconductor layer has been formed.

[0056] Figure 14C for Figure 14B A schematic diagram of the semiconductor layer in the diagram;

[0057] Figure 14D for Figure 13 A schematic diagram of the display panel after the first conductive layer has been formed;

[0058] Figure 14E for Figure 14D A schematic diagram of the first conductive layer in the middle;

[0059] Figure 14F for Figure 13 A schematic diagram of the display panel after the second conductive layer has been formed;

[0060] Figure 14G for Figure 14F A schematic diagram of the second conductive layer in the middle;

[0061] Figure 14H for Figure 13 A schematic diagram of the display panel after the third conductive layer has been formed;

[0062] Figure 14I for Figure 14H A schematic diagram of the third conductive layer in the diagram;

[0063] Figure 14J for Figure 13 A schematic diagram of the fourth conductive layer in the diagram;

[0064] Figure 15 This is a schematic diagram of data signal transmission according to at least one embodiment of the present invention;

[0065] Figure 16 This is a plan view of the adapter unit according to at least one embodiment of the present invention;

[0066] Figure 17 This is a schematic diagram showing the sequence of data signals transmitted by the data lead-out line in at least one embodiment of the present invention;

[0067] Figure 18 This is another connection diagram of the data cable and data connection line of the display panel in at least one embodiment of the present invention;

[0068] Figure 19 This is a schematic diagram of a display device according to at least one embodiment of the present invention. Detailed Implementation

[0069] The embodiments of this utility model will now be described in detail with reference to the accompanying drawings. The embodiments can be implemented in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this utility model. Therefore, this utility model should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this utility model can be arbitrarily combined with each other.

[0070] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, one aspect of the invention is not necessarily limited to these dimensions, and the shape and size of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of the invention is not limited to the shapes or values ​​shown in the drawings.

[0071] The ordinal numbers "first," "second," and "third" used in this specification are provided to avoid confusion among the constituent elements, not to limit the quantity. In this utility model, "multiple" refers to two or more items.

[0072] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this utility model. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the described constituent elements. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as needed.

[0073] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or a joint; they can refer to a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the meaning of these terms in this utility model according to the context. "Joining" can include "electrical connection," which can include situations where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the term "component having a certain electrical function," as long as it allows for the transmission of electrical signals between the connected constituent elements. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0074] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0075] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0076] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0077] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0078] In this specification, "approximately" and "about" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this utility model, "same" includes cases where the numerical values ​​differ by less than 10%, such as cases where the numerical values ​​differ by less than 5%.

[0079] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0080] In this specification, "A and B are of the same layer structure" and "A and B are arranged in the same layer" mean that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are at approximately the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. "Same layer" does not always mean that the layer thickness or layer height is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0081] Figure 1 This is a schematic diagram of a display panel according to at least one embodiment of the present invention. In some examples, such as... Figure 1As shown, the display panel can be a closed polygon including linear edges. The display panel can include a display area AA and a border area BB surrounding the display area AA. For example, the display area AA can include a first display edge (lower display edge) and a second display edge (upper display edge) positioned opposite each other in a first direction D1, and a third display edge (left display edge) and a fourth display edge (right display edge) positioned opposite each other in a second direction D2. The first and second display edges can be parallel linear edges, and the third and fourth display edges can also be parallel linear edges. Adjacent linear edges can be connected by curved edges (e.g., arc edges).

[0082] In some examples, such as Figure 1 As shown, the border area BB may include: a first border area B1 and a fourth border area B4 located on both sides of the display area AA along the first direction D1, and a second border area B2 and a third border area B3 located on both sides of the display area AA along the second direction D2. The first border area B1 may connect to the first display edge, the second border area B2 may connect to the third display edge, the third border area B3 may connect to the fourth display edge, and the fourth border area B4 may connect to the second display edge. The first border area B1 may connect to the second border area B2 and the third border area B3, and the third border area B4 may connect to the second border area B2 and the third border area B3. After the first border area B1, the second border area B2, the third border area B3, and the fourth border area B4 are connected, they can surround the display area AA. For example, the first border area B1 may also be called the lower border area of ​​the display panel, the second border area B2 may also be called the left border area of ​​the display panel, the third border area B3 may also be called the right border area of ​​the display panel, and the fourth border area B4 may also be called the upper border area of ​​the display panel. However, this embodiment is not limited in this respect.

[0083] In some examples, such as Figure 1 As shown, the first border region B1 may include: a first sub-region B11, a bent region B12, and a second sub-region B13 arranged sequentially along the side away from the display region AA in the first direction D1. The first sub-region B11 may also be referred to as a first fan-out region. The first sub-region B11 may be connected to the second border region B2 and the third border region B3, and to the display region AA. The bent region B12 may be connected between the first sub-region B11 and the second sub-region B13. The bent region B12 may be configured to bend the second sub-region B13 to the back side of the display region AA.

[0084] In some examples, the second sub-region B13 of the first border region B1 may include a first signal access region B131 and a second signal access region B132 sequentially arranged in the first direction D1 away from the bending region B12. The area of ​​the first signal access region B131 near the display region AA may be referred to as the trace lead-out area. The first signal access region B131 may be provided with a plurality of first contact pads, which may be configured to bond a driver chip (IC). The second signal access region B132 may be provided with a plurality of second contact pads, which may be configured to bond an external flexible circuit board (FPC). At least one first contact pad in the first signal access region B131 and at least one second contact pad in the second signal access region B135 may be connected by an inner lead bonding (ILB).

[0085] In some examples, such as Figure 1 As shown, the display area AA of the display panel may include at least: multiple sub-pixels PX, multiple gate lines GL, and multiple data lines (e.g., multiple first-type data lines DLa and multiple second-type data lines DLb). The multiple gate lines GL may extend along a second direction D2 and be arranged along a first direction D1; the multiple data lines may extend along the first direction D1 and be arranged along the second direction D2. For example, the multiple second-type data lines DLb may be located outside the multiple first-type data lines DLa in the second direction D2. The multiple data lines may be electrically connected to the multiple sub-pixels PX, and the multiple data lines may be configured to provide data signals or test data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide pixel control signals to the multiple sub-pixels PX. For example, the pixel control signals may include scan signals, or may include scan signals and light emission control signals, or may include scan signals, reset control signals, and light emission control signals.

[0086] In some examples, the second direction D2 can be the extension direction of the grid lines GL within the display area AA (e.g., the row direction); the first direction D1 can be the extension direction of the data lines within the display area AA (e.g., the column direction). The first direction D1 and the second direction D2 can intersect each other, for example, they can be perpendicular to each other.

[0087] In some examples, the display area AA may also be provided with multiple data connection lines 25. The second type data line DLb can be connected to the data lead-out line of the first sub-area B11 via the data connection line 25. The first type data line DLa can extend directly to the first sub-area B11 and connect to the data lead-out line of the first sub-area B11. The data connection line 25 may include: a first data connection segment 251 extending along the second direction D2 and a second data connection segment 252 extending along the first direction D1. The first data connection segment 251 can be connected between the second type data line DLb and the second data connection segment 252, and the second data connection segment 252 can be connected to the data lead-out line of the first sub-area B11. The second data connection segment 252 can be located on the side of the connected second type data line DLb away from the edge of the display panel in the second direction D2. In some examples, the first data connection segment 251 can be located on the side of the second data connection segment 252 closer to the substrate, and the second data connection segment 252, the first type data line DLa, and the second type data line DLb can be in the same layer. However, this embodiment is not limited to this. In other examples, the first data connection segment 241 can be located on the side of the first type data line DLa and the second type data line DLb closer to the substrate, and the second data connection segment 252 can be located on the side of the first type data line DLa and the second type data line DLb farther from the substrate. By setting data connection lines within the display area, so that the data lead-out lines within the first sub-area are connected to the second type data lines through the data connection lines, the length of the first sub-area along the first direction D1 can be effectively reduced, thereby greatly reducing the size of the bottom bezel.

[0088] In some examples, a pixel unit of the display area AA may include four sub-pixels, which may be a sub-pixel emitting a first color light (e.g., red light), a sub-pixel emitting a second color light (e.g., blue light), and two sub-pixels emitting a third color light (e.g., green light). However, this embodiment is not limited to this. In some examples, a pixel unit may include three sub-pixels, which may be a first sub-pixel emitting the first color light (e.g., red light), a second sub-pixel emitting the second color light (e.g., blue light), and a third sub-pixel emitting the third color light (e.g., green light).

[0089] In some examples, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit can be either P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the manufacturing process, reduces the manufacturing difficulty of the display panel, and improves the product yield.

[0090] In some examples, the shape of the light-emitting element of a sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0091] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0092] Figure 2A This is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present invention. Figure 2A The diagram illustrates the structure of a sub-pixel within the display area. In this example, the pixel circuitry includes both low-temperature polysilicon thin-film transistors (LTPTs) and oxide thin-film transistors (OTFTs).

[0093] In some examples, such as Figure 2AAs shown, in a direction perpendicular to the display panel, the display area of ​​the display panel may include at least: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on the substrate 10. The circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, and the pixel circuit for each sub-pixel may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels. In some other examples, the display panel may also include a touch structure layer located on the side of the encapsulation structure layer away from the substrate.

[0094] In some examples, Figure 2A The illustration uses an example where each sub-pixel includes a first-type transistor 21, a second-type transistor 22, and a capacitor 23. The first-type transistor 21 can be a low-temperature polycrystalline silicon thin-film transistor, and the second-type transistor 22 can be an oxide thin-film transistor.

[0095] In some examples, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 10. A first gate insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer; a second gate insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third gate insulating layer 103 may be disposed between the second gate metal layer and the second semiconductor layer; a fourth gate insulating layer 104 may be disposed between the second semiconductor layer and the third gate metal layer; an interlayer insulating layer 105 may be disposed between the third gate metal layer and the first source / drain metal layer; a passivation layer 106 and a first planarization layer 107 may be disposed between the first source / drain metal layer and the second source / drain metal layer, wherein the first planarization layer 107 may be located on the side of the passivation layer 106 away from the substrate 10; and a second planarization layer 108 may be disposed on the side of the second source / drain metal layer away from the substrate 10. In this embodiment, the first gate insulating layer 101, the second gate insulating layer 102, the third gate insulating layer 103, the fourth gate insulating layer 104, the interlayer insulating layer 105, and the passivation layer 106 can be inorganic insulating layers, while the first planarization layer 107 and the second planarization layer 108 can be organic insulating layers. However, this embodiment is not limited in this respect. In other examples, a buffer layer can also be provided on the side of the first semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from penetrating into the interior of the display panel and can also increase the adhesion of the film layers in the display panel to the substrate. In other examples, a bottom shielding metal layer (BSM) can also be provided on the side of the buffer layer near the substrate. The bottom shielding metal layer can be configured as an active layer that at least partially covers the transistors of the pixel circuit to avoid external light affecting the performance of the transistors. In other examples, the passivation layer can be omitted between the first source / drain metal layer and the second source / drain metal layer, and only the first planarization layer can be provided between the first source / drain metal layer and the second source / drain metal layer.

[0096] In some examples, such as Figure 2AAs shown, the first semiconductor layer of the display area may include at least: a first active layer 210 of a first type transistor 21. The first active layer 210 of the first type transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least: a first gate 213 of the first type transistor 21, and a first electrode 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first type transistor 21 onto the substrate 10 may cover the orthographic projection of the channel region 2100 of the first active layer 210 onto the substrate 10. The second gate metal layer may include at least: a second electrode 232 of the capacitor 23, and a third gate 224 of the second type transistor 22. The orthographic projections of the second electrode 232 and the first electrode 231 of the capacitor 23 onto the substrate 10 may at least partially overlap, for example, they may coincide. The second semiconductor layer may include at least: a second active layer 220 of the second type transistor 22. The third gate metal layer may include at least: a second gate 223 of the second type transistor 22. The orthographic projection of the second gate 223 of the second type transistor 22 onto the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 onto the substrate 10. The orthographic projection of the third gate 224 of the second type transistor 22 onto the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 onto the substrate 10. The third gate 224 may be the bottom gate of the second type transistor 22, and the second gate 223 may be the top gate of the second type transistor 22.

[0097] In some examples, such as Figure 2AAs shown, the first source-drain metal layer of the display area may include at least: a first source 211 and a first drain 212 of a first type transistor 21, and a second source 221 and a second drain 222 of a second type transistor 22. The interlayer insulating layer 105 may have multiple pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The interlayer insulating layer 105, the fourth gate insulating layer 104, the third gate insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the first active layer 210; the interlayer insulating layer 105, the fourth gate insulating layer 104, the third gate insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the first active layer 210. The interlayer insulating layer 105, the fourth gate insulating layer 104, and the third gate insulating layer 103 within the third and fourth pixel vias can be removed, exposing at least a portion of the surface at both ends of the second active layer 220. The first source 211 of the first type transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer may include at least a first transition electrode 241. The first transition electrode 241 can be electrically connected to the first drain 212 of the first type transistor 21 in the pixel circuit through a fifth pixel via formed by the passivation layer 106 and the first planarization layer 107. This example demonstrates the electrical connection between the pixel circuit and the light-emitting element via the first adapter electrode 241.

[0098] In some examples, the gate lines of the display area may be located, for example, on the first gate metal layer and the third gate metal layer; the data lines of the display area may be located, for example, on the second source-drain metal layer; the first power lines of the display area may be located, for example, on the second source-drain metal layer; the first data connection segment of the data connection line of the display area may be located, for example, on the first source-drain metal layer; and the second data connection segment may be located, for example, on the second source-drain metal layer. This embodiment is not limited in this respect. In other examples, the circuit structure layer of the display area may further include: a third source-drain metal layer located on the side of the second source-drain metal layer away from the substrate; and the data connection lines may be located on the third source-drain metal layer.

[0099] In some examples, such as Figure 2AAs shown, the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be disposed on the second planarization layer 108 and electrically connected to the first transition electrode 241 through a sixth pixel via formed in the second planarization layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the second planarization layer 108, and the pixel definition layer 134 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 can be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0100] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0101] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0102] In some examples, such as Figure 2A As shown, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display panel and relieve stress on the first encapsulation layer 141 and the third encapsulation layer 143. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have penetrated the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0103] Figure 2B This is another partial cross-sectional schematic diagram of the display area according to at least one embodiment of the present invention. In some examples, the transistor types of the multiple pixel transistors in the pixel circuit can be the same, for example, they can all be low-temperature polycrystalline silicon thin-film transistors. Figure 2B The illustration takes as an example that each sub-pixel includes a first-type transistor 21 and a capacitor 23.

[0104] In some examples, such as Figure 2BAs shown, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 10. A first gate insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer; a second gate insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; an interlayer insulating layer 105 may be disposed between the second gate metal layer and the first source / drain metal layer; a passivation layer 106 and a first planarization layer 107 may be disposed between the first source / drain metal layer and the second source / drain metal layer; and a second planarization layer 108 may be disposed on the side of the second source / drain metal layer away from the substrate 10. The first planarization layer 107 and the second planarization layer 108 may be organic insulating layers, and the first gate insulating layer 101, the second gate insulating layer 102, and the interlayer insulating layer 105 may be inorganic insulating layers. The remaining structure of the display area of ​​the display panel in this example can be found in [reference needed]. Figure 2A The description of the illustrated embodiment is omitted here.

[0105] Figure 3 This is a schematic diagram illustrating the arrangement of sub-pixels in a display area according to at least one embodiment of the present invention. In some examples, such as... Figure 3 As shown, each pixel unit in the display area may include: a first sub-pixel 15 emitting a first color light, a second sub-pixel 16 emitting a second color light, and two third sub-pixels 17a and 17b emitting a third color light. Multiple pixel units can be arranged in an array within the display area AA. The pixel circuits of the multiple sub-pixels can be arranged in an array along a first direction D1 and a second direction D2. Within a single pixel unit, the light-emitting elements of the four sub-pixels can be arranged in different columns along the second direction D2. The light-emitting elements of the first sub-pixel 15 and the second sub-pixel 16 can be arranged in the same row, and the light-emitting elements of the two third sub-pixels 17a and 17b can be arranged in the same row. The rows containing the light-emitting elements of the first sub-pixel 15 and the third sub-pixel 17a can be spaced apart along the first direction D1. In this example, the first sub-pixel 15 can be a red sub-pixel (R), the second sub-pixel 16 can be a blue sub-pixel (B), and the third sub-pixels 17a and 17b can be green sub-pixels (G). For example, the third sub-pixel 17a can be the first green sub-pixel (G1), and the third sub-pixel 17b can be the second green sub-pixel (G2).

[0106] In some examples, such as Figure 3As shown, multiple pixel units arranged along the second direction D2 can be considered a row of pixel units, and multiple pixel units arranged along the first direction D1 can be considered a column of pixel units. Multiple pixel units can include multiple first pixel units and multiple second pixel units, and the arrangement order of the four sub-pixels within the first and second pixel units can be different. For example, the e-th row of pixel units can include: multiple first pixel units arranged sequentially along the second direction D2; the first sub-pixel 15, third sub-pixel 17a, second sub-pixel 16, and third sub-pixel 17b of the first pixel unit are arranged sequentially along the second direction D2. The (e+1)-th row of pixel units can include: multiple second pixel units arranged sequentially along the second direction D2; the second sub-pixel 16, third sub-pixel 17b, first sub-pixel 15, and third sub-pixel 17a of the second pixel unit can be arranged sequentially along the second direction D2. A column of pixel units can include: first pixel units and second pixel units alternately arranged along the first direction D1. Where e can be an integer greater than 0. For example, the subpixels of odd-numbered rows of pixel units in the display area can be arranged in RG1BG2, and the subpixels of even-numbered rows of pixel units can be arranged in BG2RG1; or, the subpixels of odd-numbered rows of pixel units in the display area can be arranged in BG2RG1, and the subpixels of even-numbered rows of pixel units can be arranged in RG1BG2.

[0107] In some examples, multiple subpixels arranged along the first direction D1 can be a column of subpixels. The j-th column of subpixels may include: a first subpixel 15 and a second subpixel 16 alternately arranged along the first direction D1; the (j+1)-th column of subpixels may include: a third subpixel 17a and a third subpixel 17b alternately arranged along the first direction D1. j can be an integer greater than 1. The pixel circuitry of each column of subpixels can be connected to the same data line. For example, the j-th column of subpixels can be connected to data line DLj, and the (j+1)-th column of subpixels can be connected to data line DLj+1.

[0108] Figure 4 This is a schematic diagram illustrating the connection of a data cable and a data connection line for a display panel according to at least one embodiment of the present invention. In some examples, such as... Figure 4 As shown, the second data connection segment 252 of the data connection line 25 can be set in a one-in-one manner, that is, one second data connection segment 252 is inserted into one column of sub-pixels. In this example, two second data connection segments 252 can be inserted into two adjacent columns of sub-pixels, and the two second data connection segments 252 can be located between the data lines connected to the two columns of sub-pixels. This embodiment is not limited to this. In other examples, two second data connection segments can be inserted into one column of sub-pixels.

[0109] In some examples, such as Figure 4As shown, the display panel may further include: a plurality of first connection hole groups and a plurality of second connection hole groups located in the display area. The first connection hole groups may include a plurality of first connection holes F1 arranged in one direction, and the second connection hole groups may include a plurality of second connection holes F2 arranged in one direction. The first connection holes F1 can be vias connecting the second type data line DLb to the first data connection segment 251 of the data connection line 25; the second connection holes F2 can be vias connecting the first data connection segment 251 to the second data connection segment 252 of the data connection line 25. The arrangement direction of the plurality of first connection holes F1 in the first connection hole group and the arrangement direction of the plurality of second connection holes F2 in the second connection hole group may intersect, for example, they may both intersect with the first direction D1 and the second direction D2.

[0110] In some examples, in the left or right half of the display panel, the second data connection segment 252 of the data connection line 25 connected to the second type data line DLb near the edge of the display panel can be located on the side of the second data connection segment 252 of the data connection line 25 connected to the second type data line DLb near the center of the display panel, closer to the center of the display panel. The first data connection segment 251 of the data connection line 25 connected to the second type data line DLb near the edge of the display panel can be located on the side of the first data connection segment 251 of the data connection line 25 connected to the second type data line DLb near the center of the display panel, away from the first bezel area of ​​the display panel. For example, the orthographic projection of the first connection hole group and the adjacent second connection hole group onto the substrate can be arranged approximately in a V-shape.

[0111] In some examples, the first border area may be provided with multiple data leads 26. These multiple data leads 26 can extend from the first sub-region B11 through the bend area B12 to the second sub-region B13. The second sub-region B13 is provided with multiple multiplexing circuits (MUX). The multiplexing circuits (MUX) can be located on the side of the first signal access area B131 near the bend area B12. The multiple multiplexing circuits (MUX) can also be electrically connected to multiple multiplexed data lines, which can extend to be electrically connected to multiple first contact pads within the first signal access area B131.

[0112] In some examples, the multiple data leads 26 may include multiple first-type data leads 261 and multiple second-type data leads 262. The multiple first-type data leads 261 can be electrically connected to multiple first-type data lines DL1, and the multiple second-type data leads 262 can be electrically connected to the second data connection segment 252 of the multiple data connection lines 25, thereby achieving electrical connection with the multiple second-type data lines DL2. In this example, the order of data signals transmitted by the multiple data lines arranged sequentially along the second direction D2 within the display area AA is different from the order of data signals transmitted by the multiple data leads 26 arranged sequentially along the second direction D2 within the first border area B1.

[0113] Figure 5 This is a schematic diagram illustrating the transmission sequence of a data signal. In some examples, a single multiplexing circuit (MUX) can be connected to one multiplexed data line and two data leads, configured to transmit the data signal provided by one multiplexed data line to the two data leads in a time-division manner. Figure 5 Taking multiple data signals DL(j-4) to DL(j+3) as an example, each data signal is transmitted via a corresponding data lead-out line and a connected data line. Specifically, data signals DL(j), DL(j+1), DL(j+2), and DL(j+3) are transmitted via a first-class data line and a connected first-class data lead-out line; data signals DL(j-1), DL(j-2), DL(j-3), and DL(j-4) are transmitted via a second-class data line, a data connection line connected to the second-class data line, and a second-class data lead-out line. Within the display area, the second data connection segment of the data connection line transmitting data signals DL(j-1) and DL(j-2) can be located between the first-class data line transmitting data signal DL(j) and the first-class data line transmitting data signal DL(j+1); the second data connection segment of the data connection line transmitting data signals DL(j-3) and DL(j-4) can be located between the first-class data line transmitting data signal DL(j+2) and the first-class data line transmitting data signal DL(j+3). Within the first border area, the second type of data leads for transmitting data signals DL(j-1) and DL(j-2) can be located between the first type of data leads for transmitting data signal DL(j) and the first type of data leads for transmitting data signal DL(j+1); the second type of data leads for transmitting data signals DL(j-3) and DL(j-4) can be located between the first type of data leads for transmitting data signal DL(j+2) and the first type of data leads for transmitting data signal DL(j+3).

[0114] In some examples, such as Figure 5 As shown, the display of a 1dot overloaded screen is used as an example for explanation. The characteristic of a 1dot overloaded screen is that the sub-pixels in the same row and column alternate between bright and dark. Figure 5 In the diagram, G0 indicates that the grayscale value of the green sub-pixel is 0, and G255 indicates that the grayscale value of the green sub-pixel is 255. For data signal DL(j-2), the grayscale values ​​of the data signals of the adjacent green sub-pixels on the left and right sides of this data signal are 0 and 255 respectively, and their coupling cancels each other out. For data signal DL(j+2), the grayscale values ​​of the data signals of the adjacent green sub-pixels on the left and right sides of this data signal are both 255, and the adjacent data signals will couple, causing the brightness of the sub-pixel receiving data signal DL(j+2) (such as the blue sub-pixel) to increase. As a result, brightness differences will appear in the display area with data connection lines (for example, vertical stripes will appear in the display area of ​​the display panel), affecting the display quality.

[0115] This embodiment provides a display panel, including: a substrate, a plurality of sub-pixels disposed on the substrate, a plurality of data lines, a plurality of data connection lines, a plurality of data lead-out lines, and at least one first shielding signal line. The substrate includes a display area and a first border area located on one side of the display area along a first direction. The plurality of sub-pixels are located in the display area, and the plurality of sub-pixels include a plurality of first-type sub-pixels and a plurality of second-type sub-pixels. The plurality of data lines and the plurality of data connection lines are located in the display area, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels. The plurality of data lines include a plurality of first-type data lines and a plurality of second-type data lines, and the plurality of second-type data lines are electrically connected to the plurality of data connection lines. The plurality of data lead-out lines are located in the first border area and include a plurality of first-type data lead-out lines and a plurality of second-type data lead-out lines. The plurality of first-type data lead-out lines are electrically connected to the plurality of first-type data lines, and the plurality of second-type data lead-out lines are electrically connected to the plurality of second-type data lines through the plurality of data connection lines. At least one first shielded signal line is located in the first border region. This first shielded signal line is configured to separate at least one first-class data lead and at least one second-class data lead. The at least one first-class data lead and the at least one second-class data lead, separated by the first shielded signal line, are configured to provide signals to different types of sub-pixels. In some examples, the plurality of first-class sub-pixels may include a plurality of red sub-pixels and a plurality of blue sub-pixels, and the plurality of second-class sub-pixels may include a plurality of green sub-pixels.

[0116] The display panel provided in this embodiment can effectively improve the display quality by separating the first type of data lead-out lines and the second type of data lead-out lines that transmit data signals to different types of sub-pixels by setting a first shielding signal line. This can effectively reduce the impact of the coupling between different data signals due to the setting of the data connection line in the first frame area on the display quality.

[0117] In some exemplary embodiments, the first shielding signal line can be configured to transmit electrical signals. For example, the first shielding signal line can be configured to transmit a DC regulated signal, such as a first power supply signal VDD connected to the pixel circuit, a second power supply signal VSS connected to the light-emitting element, a high-level signal VGH connected to the gate drive circuit, or a low-level signal VGL, etc. In this example, by setting the first shielding signal line to transmit a constant voltage signal, a better shielding effect can be achieved between the first type of data leads and the second type of data leads, thereby effectively improving the impact of coupling between different data signals in the first bezel area on display quality due to the location of the data connection lines, and reducing the impact of the first shielding signal line on other traces. In other examples, the first shielding signal line may not transmit electrical signals; in other words, the first shielding signal line may be floating and not electrically connected to the traces transmitting electrical signals. The first shielding signal line configured in this example can, to a certain extent, improve the impact of coupling between the first type of data leads and the second type of data leads on display quality.

[0118] In some exemplary embodiments, the orthographic projection of at least one first shielding signal line onto the substrate may lie between the orthographic projections of the at least one first-class data lead and the at least one second-class data lead transmitting data signals to different types of sub-pixels onto the substrate. In some examples, at least one first shielding signal line and adjacent data leads may be alternately arranged on different conductive layers. For example, the orthographic projection of the at least one first shielding signal line onto the substrate may not overlap with the orthographic projections of the separated at least one first-class data lead and the at least one second-class data lead onto the substrate. This example effectively shields crosstalk coupling between the different data signals transmitted by the first-class data leads and the second-class data leads by inserting at least one first shielding signal line between the first-class data leads and the second-class data leads transmitting data signals to different types of sub-pixels.

[0119] In some exemplary embodiments, in a direction perpendicular to the display panel, the at least one first shielding signal line may be located between the at least one first-type data lead and the at least one second-type data lead; the orthographic projection of the at least one first shielding signal line on the substrate at least partially overlaps with the orthographic projections of the at least one first-type data lead and the at least one second-type data lead on the substrate. This example effectively shields crosstalk coupling between the different data signals transmitted by the first-type data lead and the second-type data lead by using a layered, separated layout design for the data lead transmitting different data signals and inserting a first shielding signal line between the two layers of different data signals.

[0120] The following examples illustrate the solutions in this embodiment.

[0121] Figure 6 This is a partial planar schematic diagram of the first bezel area of ​​a display panel according to at least one embodiment of the present invention. In this example, the data lead-out lines transmitting data signals DL(j-4) to DL(j+3) are used as an example for explanation. The data signals DL(j-4), DL(j-2), DL(j), and DL(j+2) can be transmitted to first-type sub-pixels (including red and blue sub-pixels), and the data signals DL(j-3), DL(j-1), DL(j+1), and DL(j+3) can be transmitted to second-type sub-pixels (including green sub-pixels).

[0122] In some examples, such as Figure 6 As shown, the first bezel area of ​​the display panel can be provided with multiple data lead-out lines 26 and multiple first shielded signal lines (e.g., including first shielded signal lines 271 and 272). The first shielded signal lines 271 and 272 can be configured to transmit constant voltage signals, such as high-level DC regulated signals or low-level DC regulated signals.

[0123] In some examples, the multiple data leads 26 may include multiple first-type data leads 261 and multiple second-type data leads 262. Specifically, the data leads transmitting data signals DL(j), DL(j+1), DL(j+2), and DL(j+3) can be first-type data leads 261, and the data leads transmitting data signals DL(j-1), DL(j-2), DL(j-3), and DL(j-4) can be second-type data leads 262. The first-type data leads 261 are electrically connected to the first-type data lines of the display area, and the second-type data leads 262 are electrically connected to the second-type data lines via data connection lines.

[0124] In some examples, the first shielding signal line can be configured to separate the first type data lead 261 transmitting data signals to the first type of sub-pixels and the second type data lead 262 transmitting data signals to the second type of sub-pixels; or it can be configured to separate the second type data lead 262 transmitting data signals to the first type of sub-pixels and the first type data lead 261 transmitting data signals to the second type of sub-pixels. In this example, the two first shielding signal lines 271 and 272 can be arranged adjacently and located between the second type data lead 262 transmitting data signals DL(j-2) and the first type data lead 261 transmitting data signals DL(j+1). This example does not limit the number of first shielding signal lines arranged between adjacent first type data leads 261 and second type data leads 262. In other examples, the number of first shielding signal lines located between the second type data lead 262 transmitting data signals DL(j-2) and the first type data lead 261 transmitting data signals DL(j+1) can be one, three, or more.

[0125] In some examples, the multiple data leads 26 and multiple first shielded signal lines in the first border region can be alternately arranged in different conductive layers. For example, the multiple data leads 26 and multiple first shielded signal lines can be alternately arranged in the first gate metal layer and the second gate metal layer. For instance, the first shielded signal line 271 can be located in the first gate metal layer, and the first shielded signal line 272 can be located in the second gate metal layer; the second type of data lead 262 transmitting the data signal DL(j-2) can be located in the second gate metal layer, and the first type of data lead 261 transmitting the data signal DL(j+1) can be located in the first gate metal layer.

[0126] This example uses a first shielding signal line to separate the first type of data lead-out line and the second type of data lead-out line that transmit data signals to different types of sub-pixels. This can effectively shield the interference and coupling between different data signals and avoid the occurrence of vertical lines in the display area.

[0127] Figure 7 This is another partial planar schematic diagram of the first bezel area of ​​the display panel according to at least one embodiment of the present invention. In some examples, such as Figure 7As shown, the first bezel area of ​​the display panel can be provided with multiple data lead-out lines 26 and multiple first shielded signal lines (e.g., including first shielded signal lines 273 and 274). The multiple data lead-out lines 26 and multiple first shielded signal lines can be alternately arranged in different conductive layers (e.g., a first gate metal layer and a second gate metal layer). Two data lead-out lines 26 (e.g., including a second type data lead-out line 262 for transmitting data signal DL(j-2) and a second type data lead-out line 262 for transmitting data signal DL(j-1)) can be provided between the first type data lead-out line 261 for transmitting data signal DL(j) and the second type data lead-out line 262 for transmitting data signal DL(j-1), and the first shielded signal line 274 can be provided between the first type data lead-out line 261 for transmitting data signal DL(j+1) and the second type data lead-out line 262 for transmitting data signal DL(j-2). The way the first shielding signal line is configured in this example can separate the first type of data lead-out lines and the second type of data lead-out lines that transmit data signals to different types of sub-pixels, thereby effectively shielding interference and coupling between different data signals and avoiding the occurrence of vertical stripes in the display area. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0128] Figure 8 This is another partial planar schematic diagram of the first bezel area of ​​the display panel according to at least one embodiment of the present invention. In some examples, such as Figure 8 As shown, the first bezel area of ​​the display panel can be provided with multiple data leads 26 and multiple first shielded signal lines (e.g., including first shielded signal lines 275 to 278). The multiple data leads 26 and multiple first shielded signal lines can be alternately arranged in different conductive layers (e.g., a first gate metal layer and a second gate metal layer). First shielded signal lines 275 and 276 can be located between a first-type data lead 261 transmitting data signal DL(j) and a second-type data lead 262 transmitting data signal DL(j-1); first shielded signal lines 277 and 278 can be located between a first-type data lead 261 transmitting data signal DL(j+1) and a second-type data lead 262 transmitting data signal DL(j-4). Four second-type data leads 262 can be provided between first shielded signal lines 276 and 277. This example centrally positions four Type II data leads between the Type I data leads and uses a first shielding signal line to separate the Type I and Type II data leads. This effectively shields interference and coupling between different data signals, thereby preventing vertical lines from appearing on the display area. Further details regarding the display panel in this example can be found in the description of the foregoing embodiments and will not be repeated here.

[0129] Figure 9 This is a partial cross-sectional schematic diagram of the first bezel area of ​​a display panel according to at least one embodiment of the present invention. In some examples, such as... Figure 9 As shown, the first bezel area of ​​the display panel can be provided with multiple data leads 26 and at least one first shielding signal line (e.g., including a first shielding signal line 279). The multiple data leads 26 can include: a first group of data leads 263 transmitting data signals to first-type sub-pixels (including red and blue sub-pixels), and a second group of data leads 264 transmitting data signals to second-type sub-pixels (including green sub-pixels). Each group of data leads can include multiple data leads arranged adjacent to each other. The first group of data leads 263 can be arranged on the same layer, and the second group of data leads 264 can be arranged on the same layer. The first shielding signal line 279 can separate the first group of data leads 263 and the second group of data leads 264. For example, the first group of data leads 263 can be located on the side of the first shielding signal line 279 away from the substrate 10, and the second group of data leads 264 can be located on the side of the first shielding signal line 279 closer to the substrate 10. For example, the first shielding signal line 279 can be located in the first source / drain metal layer, the first set of data leads 263 can be located in the second source / drain metal layer, and the second set of data leads 264 can be located in the first gate metal layer. The orthographic projection of the first shielding signal line 279 onto the substrate can at least partially overlap with the orthographic projections of the first set of data leads 263 and the second set of data leads 264 onto the substrate. For example, the orthographic projection of the first shielding signal line 279 onto the substrate can cover the orthographic projections of the first set of data leads 263 and the second set of data leads 264 onto the substrate. This example, by arranging the first shielding signal line and the data leads that provide data signals to different types of sub-pixels in a layered manner, can effectively shield interference and coupling between different data signals, thereby avoiding the occurrence of vertical stripes in the display area. Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0130] Figure 10 This is another partial cross-sectional schematic diagram of the first bezel area of ​​the display panel according to at least one embodiment of the present invention. In some examples, such as Figure 10As shown, the multiple data leads 26 may include: a first set of data leads 263 transmitting data signals to a first type of sub-pixels (including red and blue sub-pixels), and a second set of data leads 264 transmitting data signals to a second type of sub-pixels (including green sub-pixels). The first set of data leads 263 may be located in the second source-drain metal layer, and the second set of data leads 264 may be located in the second gate metal layer. The first shielding signal line 279 may be located in the first source-drain metal layer. The first shielding signal line 279 may separate the first set of data leads 263 and the second set of data leads 264. This example, by arranging the first shielding signal line and the data leads providing data signals to different types of sub-pixels in a layered manner, can effectively shield interference and coupling between different data signals, thereby avoiding the occurrence of vertical stripes in the display area. Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0131] Figure 11 This is another partial cross-sectional schematic diagram of the first bezel area of ​​the display panel according to at least one embodiment of the present invention. In some examples, such as Figure 11 As shown, the multiple data leads 26 may include: a first set of data leads 263 for transmitting data signals to first-type sub-pixels (including red and blue sub-pixels), and a second set of data leads 264 for transmitting data signals to second-type sub-pixels (including green sub-pixels). The multiple data leads within the second set of data leads 264 may be alternately arranged in the first gate metal layer and the second gate metal layer. Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0132] In other examples, the first set of data leads transmitting data signals to the first type of sub-pixels may be located in the first gate metal layer, or the second gate metal layer, or both the first gate metal layer and the second gate metal layer; the second set of data leads transmitting data signals to the second type of sub-pixels may be located in the second source-drain metal layer; and the first shielding signal line may be located in the first source-drain metal layer. Further details regarding this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0133] The display panel provided in this embodiment provides a first shielding signal line in the first border area. The first shielding signal line separates the first type of data lead-out line and the second type of data lead-out line that transmit data signals to different types of sub-pixels. This effectively shields the interference and coupling between different data signals in the first border area and avoids the occurrence of vertical lines in the display area.

[0134] Figure 12 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present invention. The pixel circuit of this exemplary embodiment is described using a 7T1C structure as an example. In some examples, such as... Figure 12 As shown, the pixel circuit in this example may include: a first transistor (also referred to as a first reset transistor) T1, a second transistor (also referred to as a threshold compensation transistor) T2, a third transistor (also referred to as a driving transistor) T3, a fourth transistor (also referred to as a data writing transistor) T4, a fifth transistor (also referred to as a first light-emitting control transistor) T5, a sixth transistor (also referred to as a second light-emitting control transistor) T6, a seventh transistor (also referred to as a second reset transistor) T7, and a storage capacitor Cst. The light-emitting element EL may include a first electrode, a second electrode, and a light-emitting functional layer disposed between the first electrode and the second electrode. The first electrode of the light-emitting element EL may be an anode, and the second electrode of the light-emitting element EL may be a cathode.

[0135] In some examples, such as Figure 12 As shown, the display panel may include: a scan line GAL, a data line DL, a first power line PL1, a second power line PL2, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 can be configured to provide a constant first power signal VDD to the pixel circuit, and the second power line PL2 can be configured to provide a constant second power signal VSS to the cathode of the light-emitting element EL, wherein the first power signal VDD is greater than the second power signal VSS. The scan line GAL can be configured to provide a scan signal to the pixel circuit, the data line DL can be configured to provide a data signal to the pixel circuit, the light emission control line EML can be configured to provide a light emission control signal to the pixel circuit, the first reset control line RST1 can be configured to provide a first reset control signal to the pixel circuit, and the second reset control line RST2 can be configured to provide a second reset control signal to the pixel circuit. In some examples, the second reset control line RST2 electrically connected to the pixel circuit in the e-th row and the first reset control line RST1 electrically connected to the pixel circuit in the (e+1)-th row can be an integral structure. Where e is a positive integer. This reduces the number of signal lines on the display panel, enabling a narrow bezel design.

[0136] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first and second initial signals may be constant voltage signals, the magnitude of which may be, for example, between a first power supply signal and a second power supply signal, but is not limited thereto. In other examples, the first and second initial signals may be the same, and only the first initial signal line may be configured to provide the first initial signal.

[0137] In some examples, such as Figure 12 As shown, the third transistor T3 is electrically connected to the light-emitting element EL, and outputs a driving current to drive the light-emitting element EL to emit light under the control of signals such as the scan signal, data signal, first power signal, and second power signal. The gate of the fourth transistor T4 is electrically connected to the scan line GAL, the first terminal of the fourth transistor T4 is electrically connected to the data line DL, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the third transistor T3. The gate of the second transistor T2 is electrically connected to the scan line GAL, the second terminal of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the first terminal of the second transistor T2 is electrically connected to the second terminal of the driving transistor T3. The gate of the fifth transistor T5 is electrically connected to the light-emitting control line EML, the first terminal of the fifth transistor T5 is electrically connected to the first power line PL1, and the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the light-emitting control line EML, the first terminal of the sixth transistor T6 is electrically connected to the second terminal of the third transistor T3, and the second terminal of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The gates of the first transistor T1 and the third transistor T3 are electrically connected, and the third transistor T3 is configured to reset its gate. The seventh transistor T7 is electrically connected to the anode of the light-emitting element EL, and the seventh transistor T7 is configured to reset its anode. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0138] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3, and the second transistor T2; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, and the third transistor T3; the third node N3 is the connection point of the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0139] Figure 13 This is a partial planar schematic diagram of the display area of ​​the display panel of at least one embodiment of the present invention. Figure 13 The diagram shows a partial planar schematic of the circuit structure layer of the display area. Figure 13The diagram illustrates a partial planar structure with four columns (e.g., including columns j-1 to j+2) and two rows (e.g., including rows e-1 and e). In some examples, the multiple pixel circuits of the display area can be divided into multiple groups along the second direction D2, and each group of pixel circuits can include two pixel circuits symmetrically arranged about a centerline extending along the first direction D1 of that group. Figure 13 As shown, adjacent columns of pixel circuits can be symmetrically arranged about the center line extending along the first direction D1. Specifically, the j-th column and the (j+1)-th column of pixel circuits can be symmetrically arranged about the center line O1 extending along the first direction D1. The pixel circuit in the e-th row and j-th column and the pixel circuit in the e-th row and (j+1)-th column can be a set of pixel circuits, and these two sets can be symmetrically arranged about the center line O1.

[0140] In some examples, the multiple pixel circuits in the display area can be divided into multiple groups along the second direction D2. Each group may include two columns of pixel circuits symmetrically arranged about a centerline extending along the first direction. For example, the j-th and j+1-th column pixel circuits may be a group of pixel circuits, the j+2-th and j+3-th column pixel circuits may be a group of pixel circuits, and the j-2-th and j-1-th column pixel circuits may be a group of pixel circuits. The orthographic projection of a group of pixel circuits onto the substrate may overlap with the orthographic projection of at least two second data connection segments 252 onto the substrate, and the data lines connected to the group of pixel circuits may be located on both sides of the at least two second data connection segments 252 along the second direction D2.

[0141] The structure of a display panel is illustrated below through the fabrication process of the display panel. The "patterning process" described in this invention includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This invention does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0142] The fabrication process of the display panel in this example may include the following steps. The following explanation uses the pixel circuit in the j-th column and e-th row as an example.

[0143] (1) Providing a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, a rigid substrate can be, but is not limited to, one or more of glass and quartz; a flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0144] (2) Forming a shielding layer. In some examples, a shielding film is deposited on the substrate, and the shielding film is patterned by a patterning process to form a shielding layer disposed on the substrate. In some examples, the shielding layer may also be referred to as a bottom shielding metal (BSM).

[0145] Figure 14A for Figure 13 A schematic diagram of the display panel after the shielding layer has been formed. In some examples, such as... Figure 14A As shown, the shielding layer 31 of the display panel may include multiple first shielding blocks 311, multiple second shielding blocks 312, and multiple third shielding blocks 313. The first shielding blocks 311 may be connected to the second shielding blocks 312, and the second shielding blocks 312 may be connected to the third shielding blocks 313. The first shielding blocks 311, second shielding blocks 312, and third shielding blocks 313 may be an integral structure. The second shielding block 312 located in the j-th column pixel circuit is connected to the second shielding block 312 located in the (j+1)-th column pixel circuit, and the first shielding block 311 located in the j-th column pixel circuit may be connected to the first shielding block 311 located in the (j-1)-th column pixel circuit.

[0146] (3) Forming a semiconductor layer. In some examples, a first insulating film and a semiconductor film are deposited on the substrate on which the aforementioned pattern is formed, and the semiconductor film is patterned by a patterning process to form a first insulating layer and a semiconductor layer disposed on the substrate. In some examples, the material of the semiconductor layer may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, or oxide semiconductor (e.g., IGZO).

[0147] Figure 14B for Figure 13 A schematic diagram of a display panel after a semiconductor layer has been formed. Figure 14C for Figure 14B A schematic diagram of the semiconductor layer. In some examples, such as... Figure 14B and Figure 14C As shown, the semiconductor layer of the display area may include: active layers of transistors for multiple pixel circuits. The active layers T10, T20, T30, T40, T50, T60, and T60 of the first transistor, and the active layer of the seventh transistor in the same pixel circuit can be a single integrated structure. The active layer T70 of the seventh transistor in the j-th and j+1-th columns of the pixel circuits in the same row (e.g., row e-1) can be a single integrated structure. The active layers T10 of the first transistor in the j-1-th and j-th columns of the pixel circuits in the same row (e.g., row e) can be a single integrated structure, and the active layer T50 of the fifth transistor in the j-1-th and j-th columns of the pixel circuits in the same row (e.g., row e) can be a single integrated structure.

[0148] In some examples, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The semiconductor layer material may include, for example, polysilicon or oxide (e.g., indium gallium zinc oxide (IGZO)). The channel region of the transistor may be undoped and possess semiconductor properties. The first and second regions may be doped regions on either side of the channel region and are doped with impurities, thus possessing conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source or drain electrodes of the transistor. For example, the first region of the active layer may be interpreted as the first electrode of the transistor, and the second region of the active layer may be interpreted as the second electrode of the transistor. The portions of the active layer between transistors may be interpreted as doped wiring that can be used to electrically connect the transistors. This embodiment is not limited in this respect.

[0149] In some examples, the orthographic projection of the first blocking block 311 onto the substrate may at least partially overlap with the orthographic projection of the active layer T30 of the third transistor onto the substrate, and the orthographic projection of the channel region of the active layer T30 of the third transistor onto the substrate may be within the orthographic projection range of the first blocking block 311 onto the substrate. Similarly, the orthographic projection of the second blocking block 312 onto the substrate may at least partially overlap with the orthographic projection of the active layer T20 of the second transistor onto the substrate, and the orthographic projection of the channel region of the active layer T20 of the second transistor onto the substrate may be within the orthographic projection range of the second blocking block 312 onto the substrate. Likewise, the orthographic projection of the third blocking block 313 onto the substrate may at least partially overlap with the orthographic projection of the active layer T10 of the first transistor onto the substrate, and the orthographic projection of the channel region of the active layer T10 of the first transistor onto the substrate may be within the orthographic projection range of the third blocking block 313 onto the substrate. This example uses blocking layers to block the channel regions of the active layers of the first, second, and third transistors in the pixel circuit, thus ensuring the performance of the transistors in the pixel circuit.

[0150] (4) Forming a first conductive layer. In some examples, a second insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed. The first conductive film is then patterned using a patterning process to form a second insulating layer and a first conductive layer disposed on the second insulating layer. In this example, the second insulating layer can be the aforementioned first gate insulating layer, and the first conductive layer can be the aforementioned first gate metal layer.

[0151] Figure 14D for Figure 13 A schematic diagram of the display panel after the first conductive layer has been formed. Figure 14E for Figure 14D A schematic diagram of the first conductive layer in the image. In some examples, such as... Figure 14D and Figure 14E As shown, the first conductive layer of the display area may include: multiple scan lines (e.g., scan line GAL(e)), light emission control lines (e.g., light emission control lines EML(e), EML(e-1)), a first reset control line (e.g., first reset control line RST1(e)), and the gates of transistors of multiple pixel circuits.

[0152] In some examples, the scan line GAL(e), the emission control line EML(e), EML(e-1), and the first reset control line RST1(e) can all extend along the second direction D2. The orthographic projection of the scan line GAL(e) onto the substrate can lie between the orthographic projections of the emission control line EML(e) and the first reset control line RST1(e) onto the substrate.

[0153] In some examples, the overlap between the first reset control line RST1(e) and the active layer T10 of the first transistor T1 in the e-th row and j-th column pixel circuit can serve as the gate of the first transistor T1. Similarly, the overlap between the first reset control line RST1(e) and the active layer T70 of the seventh transistor T7 in the (e-1)-th row and j-th column pixel circuit can serve as the gate of the seventh transistor T7. The overlap between the scan line GAL(e) and the active layer T20 of the second transistor T2 in the e-th row and j-th column pixel circuit can serve as the gate of the second transistor T2, and the overlap with the active layer T40 of the fourth transistor T4 in the e-th row and j-th column pixel circuit can serve as the gate of the fourth transistor T4. The overlap between the light emission control line EML(e) and the active layer T50 of the fifth transistor T5 in the e-th row and j-th column pixel circuit can serve as the gate of the fifth transistor T5, and the overlap with the active layer T60 of the sixth transistor T6 in the e-th row and j-th column pixel circuit can serve as the gate of the sixth transistor T6. The gate T31 of the third transistor T3 in the pixel circuit of row e and column j can also serve as the first electrode Cst-1 of the storage capacitor.

[0154] (5) Forming a second conductive layer. In some examples, a third insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed. The second conductive film is patterned using a patterning process to form a third insulating layer and a second conductive layer disposed on the third insulating layer. In this example, the third insulating layer can be the aforementioned second gate insulating layer, and the second conductive layer can be the aforementioned second gate metal layer.

[0155] Figure 14F for Figure 13 A schematic diagram of the display panel after the second conductive layer has been formed. Figure 14G for Figure 14F A schematic diagram of the second conductive layer. In some examples, such as... Figure 14F and Figure 14G As shown, the second conductive layer of the display area may include: the second electrode Cst-2 of the storage capacitors of multiple pixel circuits, multiple first initial signal lines (e.g., first initial signal line INIT1(e)) and multiple second initial signal lines (e.g., second initial signal lines INIT2(e-1), INIT2(e)), and multiple shielding blocks 321. The first initial signal line INIT1(e) and the second initial signal lines INIT2(e-1), INIT2(e) may extend along the second direction D2. The first initial signal line INIT1(e) may be located between the second initial signal lines INIT2(e-1) and INIT2(e). The shielding block 321 may be located on the side of the first initial signal line INIT1(e) away from the second initial signal line INIT2(e-1). The second electrode Cst-2 of the storage capacitors of multiple pixel circuits in the same row may be a single structure.

[0156] (6) Forming a fourth insulating layer. In some examples, a fourth insulating film is deposited on the substrate on which the aforementioned structure is formed, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer. The fourth insulating layer in this example can be the aforementioned interlayer insulating layer. In some examples, the fourth insulating layer can have multiple vias, such as a first type of via exposing a portion of the surface of the semiconductor layer, a second type of via exposing a portion of the surface of the first conductive layer, and a third type of via exposing a portion of the surface of the second conductive layer.

[0157] (7) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate on which the aforementioned structure is formed, and the third conductive film is patterned by a patterning process to form a third conductive layer disposed on the fourth insulating layer. In this example, the third conductive layer can be the aforementioned first source / drain metal layer.

[0158] Figure 14H for Figure 13 A schematic diagram of the display panel after the third conductive layer has been formed. Figure 14I for Figure 14H A schematic diagram of the third conductive layer. In some examples, such as... Figure 14H and Figure 14I As shown, the third conductive layer of the display area may include: multiple connection electrodes (e.g., first connection electrodes 331 to sixth connection electrodes 336), multiple adapter lines (e.g., first adapter line 341 and second adapter line 342), and a first data connection segment 251 of multiple data connection lines. The first data connection segment 251 may extend along the second direction D2 and is located within the gap between two adjacent rows of pixel circuits.

[0159] In some examples, the first connection electrode 331 can be connected to the first region of the active layer T10 of the first transistor T1 in the e-th row and j-th column pixel circuit, and also to the first initial signal line INIT1(e). The second connection electrode 332 can be connected to the first region of the active layer T40 of the fourth transistor T4 in the e-th row and j-th column pixel circuit. The third connection electrode 333 can be connected to the gate of the third transistor T3 in the e-th row and j-th column pixel circuit, and also to the first region of the active layer T20 of the second transistor T2. The fourth connection electrode 334 can be connected to the first region of the active layer T50 of the fifth transistor T5 in the e-th row and j-th column pixel circuit, and also to the second electrode Cst-2 of the storage capacitor. The fifth connection electrode 335 can be connected to the second region of the active layer T60 of the sixth transistor T6 in the e-th row and j-th column pixel circuit. The sixth connection electrode 336 can be connected to the second electrode Cst-2 of the storage capacitor, and also to the shielding block 321.

[0160] In some examples, the first adapter line 341 and the second adapter line 342 may extend along the first direction D1. The first adapter line 341 may be connected to the first initial signal line INIT1(e). The second adapter line 342 may be connected to the first region of the active layer T70 of the seventh transistor T7 of the pixel circuit in the (e-1)th row, jth column and j+1th column, and may also be connected to the second initial signal line INIT2(e).

[0161] (8) Forming the fifth insulating layer and the sixth insulating layer. In some examples, a fifth insulating film is deposited on the substrate on which the aforementioned structure is formed, and then a sixth insulating film is coated. The sixth insulating film and the fifth insulating film are patterned by a patterning process to form the fifth insulating layer and the sixth insulating layer disposed on the fifth insulating layer. In other examples, after depositing the fifth insulating film, the fifth insulating layer can be formed by a patterning process, and then the sixth insulating film is coated, and the sixth insulating layer is formed by a second patterning process. This embodiment is not limited to this. In this example, the fifth insulating layer can be the aforementioned passivation layer, and the sixth insulating layer can be the aforementioned first planarization layer. In some examples, the sixth insulating layer of the display area can have multiple vias to expose a portion of the surface of the third conductive layer.

[0162] (9) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate on which the aforementioned structure is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer disposed on the sixth insulating layer. In this example, the fourth conductive layer can be the aforementioned second source / drain metal layer.

[0163] Figure 14J for Figure 13 A schematic diagram of the fourth conductive layer. In some examples, such as... Figure 13 and Figure 14J As shown, the fourth conductive layer of the display area may include: multiple data lines (e.g., data lines DLj-1, DLj, DLj+1, and DLj+2), multiple second data connection segments 252, multiple first power lines PL1, multiple seventh connection electrodes 337, and multiple adapter cables (e.g., including a third adapter cable 343 and a fourth adapter cable 344). The seventh connection electrode 337 may be connected to the sixth connection electrode 336 and subsequently connected to the first electrode of the light-emitting element.

[0164] In some examples, the first power line PL1 can be connected to the second electrode Cst-2 of the storage capacitor. The data line can be connected to the corresponding pixel circuit via the second connection electrode 332. The second data connection segment 252 can be connected to the corresponding first data connection segment 251. The third adapter line 343 and the fourth adapter line 344 can extend along the first direction D1. The two ends of the third adapter line 343 can be connected to two adjacent first adapter lines 341 respectively, enabling the transmission of the first initial signal along the first direction D1. The two ends of the fourth adapter line 344 can be connected to two adjacent second adapter lines 342 respectively, enabling the transmission of the second initial signal along the first direction D1.

[0165] In some examples, multiple data lines, multiple first power lines PL1, and multiple second data connection segments 252 can extend along the first direction D1. Two second data connection segments 252 can be provided within the j-th and j+1-th column pixel circuits, and these two second data connection segments 252 can be arranged adjacent to each other in the second direction D2. Each second data connection segment 252 can be connected to a corresponding first data connection segment 251. The data line DLj connected to the j-th column pixel circuit and the data line DLj+1 connected to the j+1-th column pixel circuit can be located on either side of the two second data connection segments 252 in the second direction D2. A first power line PL1 is provided between the data line DLj-1 connected to the j-1-th column pixel circuit and the data line DLj connected to the j-th column pixel circuit.

[0166] In some examples, the orthographic projection of the third adapter cable 343 onto the substrate can be located between data line DLj and the second data connection segment 252, and the orthographic projection of the fourth adapter cable 344 onto the substrate can be located between data line DLj+1 and the second data connection segment 252. The third adapter cable 343, the first adapter cable 341, and the first initial signal line can be connected in the display area to form a mesh transmission structure for the first initial signal, and the fourth adapter cable 344, the second adapter cable 342, and the second initial signal line can be connected in the display area to form a mesh transmission structure for the first initial signal.

[0167] In some examples, a seventh insulating film is coated on the substrate forming the aforementioned structure, and the seventh insulating film is patterned using a patterning process to form a seventh insulating layer. This completes the fabrication of the circuit structure layer. In this example, the seventh insulating layer can be the aforementioned second planarization layer.

[0168] In this example, the multiple second shielded signal lines may include: a shielded trace formed by alternating connections of a first adapter cable 341 and a third adapter cable 343 transmitting a first initial signal along the first direction D1; and a shielded trace formed by alternating connections of a second adapter cable 342 and a fourth adapter cable 344 transmitting a second initial signal along the first direction D1. The second shielded signal lines in this example can separate the second data connection segment and the data line, avoiding signal interference and coupling-related display defects, thereby improving display quality.

[0169] In some examples, multiple second shielded signal lines extending to the first frame region may be electrically connected to multiple first shielded signal lines in the first frame region. However, this embodiment is not limited to this. For example, the constant voltage signal transmitted by the first shielded signal lines in the first frame region may be different from the constant voltage signal transmitted by the second shielded signal lines.

[0170] Figure 15 This is a schematic diagram of data signal transmission according to at least one embodiment of the present invention. Figure 16 This is a plan view of the adapter unit according to at least one embodiment of the present invention. Figure 17 This is a schematic diagram showing the sequence of data signals transmitted by the data lead-out line in at least one embodiment of the present invention.

[0171] In some examples, such as Figure 15 As shown, the example illustrates eight data signals DL(j-4) to DL(j+3) transmitted via eight data lines DLj-4 to DLj+3. Data lines DLj, DLj+1, DLj+2, and DLj+3 can be type 1 data lines, while data lines DLj-4, DLj-3, DLj-2, and DLj-1 can be type 2 data lines. These are inserted into the type 1 data lines via data connection cables and led out to the first border area B1. Multiple data lines and multiple data connection cables can be connected to multiple data lead-out lines via multiple adapter units. These multiple data lead-out lines can be configured to provide data signals to the sub-pixels of the e-th row pixel unit within the display area AA during the first time period, and to provide data signals to the sub-pixels of the e+1-th row pixel unit within the display area AA during the second time period, where e is an integer greater than 0. In the first time period, the data signals transmitted by the multiple data leads connected to a single switching unit are configured to correspond sequentially to the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, and the second sub-pixel. In the second time period, the data signals transmitted by the multiple data leads connected to the switching unit are configured to correspond sequentially to the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the first sub-pixel. In some examples, the first sub-pixel can be a red sub-pixel, the second sub-pixel can be a blue sub-pixel, and the third sub-pixel can be a green sub-pixel.

[0172] In some examples, a single data lead connected to the multiplexing circuit MUX can provide data signals to the red and blue sub-pixels in a time-division multiplexing manner. For instance, in the first time period, the data signals transmitted by multiple data leads connected to a single switching unit correspond sequentially to the red, green, green, blue, red, green, green, and blue sub-pixels; in the second time period, the data signals transmitted by multiple data leads connected to the same switching unit correspond sequentially to the blue, green, green, red, blue, green, green, and red sub-pixels. For example, in the first time period, the data signals transmitted by the multiple data leads connected to a single switching unit correspond to blue sub-pixels, green sub-pixels, green sub-pixels, red sub-pixels, blue sub-pixels, green sub-pixels, green sub-pixels, and red sub-pixels in sequence; in the second time period, the data signals transmitted by the multiple data leads connected to the switching unit correspond to red sub-pixels, green sub-pixels, green sub-pixels, blue sub-pixels, red sub-pixels, green sub-pixels, green sub-pixels, and blue sub-pixels in sequence.

[0173] In some examples, such as Figure 16As shown, the data lines located on both sides of the first power line PL1 are first-class data lines DLa, and the two second data connection segments 252 can be disposed in the gap between the two first-class data lines DLa on the side away from the first power line PL1. A single adapter unit may include eight adapter electrodes (e.g., the first adapter electrode 511 to the eighth adapter electrode 518 arranged sequentially along the second direction D2). The eight adapter electrodes can be electrically connected one-to-one with one first-class data line, two data connection lines, two first-class data lines, two data connection lines, and another first-class data line disposed along the second direction D2. The first adapter electrode 511 can connect the first-class data line DLa and a data lead (first-class data lead) located in the second gate metal layer, and the second adapter electrode 512 can connect a second data connection segment 252 and another data lead (second-class data lead) located in the second gate metal layer. The first adapter electrode 511 and the second adapter electrode 512 can be located in the first source / drain metal layer. The third transition electrode 513 may be located in the second source / drain metal layer and connected to a first-type data line DLa and a data lead (first-type data lead) located in the first gate metal layer. The fourth transition electrode 514 may be located in the first gate metal layer and connected to a second data connection segment 252 and a data lead (second-type data lead) located in the first gate metal layer. The fifth transition electrode 515 may be located in the second source / drain metal layer and connected to a first-type data connection line DLa and another data lead (first-type data lead) located in the first gate metal layer. The sixth transition electrode 516 may be located in the first source / drain metal layer and connected to a second data connection segment 252 and another data lead (second-type data lead) located in the first gate metal layer. The seventh transition electrode 517 may be located in the first source / drain metal layer and connected to a second data connection segment 252 and another data lead (second-type data lead) located in the second gate metal layer. The eighth transition electrode 518 can be located in the first source / drain metal layer and connected to a first-type data line DLa and another data lead (first-type data lead) located in the second gate metal layer. The eight transition electrodes can sequentially connect two first-type data leads, four second-type data leads, and two first-type data leads along the second direction D2. The data leads connected to the eight connecting electrodes can be alternately arranged in the first gate metal layer and the second gate metal layer.

[0174] In some examples, after the data signal transmission is adjusted via the switching unit, the order of the data signals transmitted by the multiple data leads changes compared to the order in which the multiple Class 1 data lines and multiple data connection lines are introduced into the first border area. For example... Figure 17 As shown, taking the display of a 1dot overload screen as an example, no interaction occurs between the different data signals transmitted by multiple data leads, as in... Figure 5The coupling shown can avoid interference and coupling between different data signals transmitted by multiple data leads within the first border area, and can avoid the occurrence of vertical lines in the display area, which is conducive to ensuring display quality.

[0175] This example adjusts the order in which data lines and data connection lines are introduced into the first border area by setting an adapter unit within the first border area. This prevents interference and coupling of data signals transmitted by the data lead-out lines in the first border area, thereby improving the resulting vertical stripe display.

[0176] Figure 18 This is another connection diagram of the data cable and data connection line of the display panel, which is at least one embodiment of the present invention. In some examples, such as... Figure 18 As shown, the orthographic projections of the first connecting hole group and the adjacent second connecting hole group onto the substrate may not follow a standard V-shaped arrangement. The remaining descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and therefore will not be repeated here. The display panel in this example is applicable to… Figure 15 The illustrated embodiment improves the vertical stripe display caused by interference and coupling between data leads transmitting different data signals within the first border area.

[0177] This embodiment also provides a display panel, including: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data connection lines, and at least one second shielding signal line. The plurality of sub-pixels are disposed on the substrate and located in a display area, and at least one of the plurality of sub-pixels includes a pixel circuit. The plurality of data lines and the plurality of data connection lines are located in the display area, and the plurality of data lines are electrically connected to the pixel circuits of the plurality of sub-pixels. The plurality of data lines include: a plurality of first-type data lines and a plurality of second-type data lines extending along a first direction. The at least one data connection line includes: a first data connection segment extending along a second direction and a second data connection segment extending along the first direction, the first direction intersecting the second direction; the first data connection segment of the at least one data connection line is electrically connected to a second-type data line and the second data connection segment, respectively. The at least one second shielding signal line is located in the display area, and the orthographic projection of the at least one second shielding signal line on the substrate is at least partially located between the orthographic projections of the at least one first-type data line and the second data connection segment of the at least one data connection line on the substrate.

[0178] This embodiment separates the data line and the second data connection segment by setting a second shielded signal line in the display area, which can avoid signal interference and coupling that cause display defects, thereby improving the display quality.

[0179] In some exemplary embodiments, the second shielding signal line can be configured to transmit electrical signals. For example, the second shielding signal line can be configured to transmit a DC regulated signal, such as a first initial signal or a second initial signal. In this example, by setting the second shielding signal line to transmit a constant voltage signal, better shielding can be achieved between the data line and the second data connection segment, thereby avoiding display defects caused by mutual signal interference and coupling, and reducing the impact of the second shielding signal line on other circuit structures. In other examples, the second shielding signal line may not transmit electrical signals; in other words, the second shielding signal line can be floating and not electrically connected to the traces transmitting electrical signals. The second shielding signal line configured in this example can, to some extent, improve the avoidance of display defects caused by signal interference and coupling between the data line and the second data connection segment.

[0180] In some exemplary embodiments, the pixel circuits of the plurality of sub-pixels are electrically connected to a first initial signal line and a second initial signal line; the at least one second shielding signal line is configured to be electrically connected to either the first initial signal line or the second initial signal line. In some examples, the at least one second shielding signal line includes a plurality of alternating adapter lines extending along the first direction and alternately connected, the plurality of adapter lines being alternately arranged on different conductive layers. For example, the at least one second shielding signal line may include the aforementioned first and third adapter lines alternately connected; the at least one second shielding signal line may include the aforementioned second and fourth adapter lines alternately connected. This example arrangement can effectively utilize the routing space.

[0181] In some exemplary embodiments, the pixel circuits of the plurality of sub-pixels are divided into multiple groups along the second direction. Each group of pixel circuits includes two pixel circuits symmetrically arranged about a centerline extending along the first direction. The orthographic projection of at least one group of pixel circuits on the substrate overlaps with the orthographic projection of at least two second data connection segments on the substrate. The data lines connected to the at least one group of pixel circuits are located on both sides of the at least two second data connection segments along the second direction. In some examples, the second data connection segments and the plurality of data lines are in the same layer, with the first data connection segment located on the side of the second data connection segment closer to the substrate. This example arrangement can effectively utilize the routing space.

[0182] In some exemplary embodiments, the substrate may further include: a first border region located on one side of the display area along the first direction; a pixel unit located in the display area includes: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and two third sub-pixels emitting a third color light. The display panel may further include: a plurality of transition units and a plurality of data leads located in the first border region, the plurality of data leads being electrically connected to the second data connection segments of the plurality of first-type data lines and the plurality of data connection lines through the plurality of transition units; each transition unit includes a plurality of transition electrodes arranged along the second direction. The plurality of data leads are configured to provide data signals to the sub-pixels of the e-th row pixel unit in the display area during a first time period, and to provide data signals to the sub-pixels of the (e+1)-th row pixel unit in the display area during a second time period, where e is an integer greater than 0. In the first time period, the data signals transmitted by multiple data leads connected to a switching unit are configured to correspond sequentially to a first sub-pixel, a third sub-pixel, a third sub-pixel, a second sub-pixel, a first sub-pixel, a third sub-pixel, a third sub-pixel, and a second sub-pixel. In the second time period, the data signals transmitted by multiple data leads connected to a switching unit are configured to correspond sequentially to a second sub-pixel, a third sub-pixel, a third sub-pixel, a first sub-pixel, a second sub-pixel, a third sub-pixel, a third sub-pixel, and a first sub-pixel. In some examples, a single switching unit includes eight switching electrodes arranged along the second direction, which are electrically connected one-to-one to one of a first-class data line, two data connection lines, two first-class data lines, two data connection lines, and another first-class data line arranged along the second direction; the eight switching electrodes are also electrically connected one-to-one to two first-class data leads, four second-class data leads, and two first-class data leads arranged along the second direction. This example adjusts the order in which data lines and data connection lines are introduced into the first border area by setting an adapter unit within the first border area. This prevents interference and coupling of data signals transmitted by the data lead-out lines in the first border area, thereby improving the resulting vertical stripe display.

[0183] Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0184] This embodiment also provides a display panel, including: a substrate, multiple pixel units, multiple data lines, multiple data connection lines, multiple data lead-out lines, and multiple adapter units. The substrate includes a display area and a first border area located on one side of the display area along a first direction. The multiple pixel units are located in the display area, each pixel unit including a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and two third sub-pixels emitting a third color light. The multiple data lines and multiple data connection lines are located in the display area, the multiple data lines including: multiple first-type data lines and multiple second-type data lines, the multiple data lines being configured to transmit data signals to the sub-pixels of the multiple pixel units, the multiple second-type data lines being electrically connected to the multiple data connection lines. The multiple data lead-out lines and multiple adapter units are located in the first border area, the multiple data lead-out lines being electrically connected to the multiple first-type data lines and the multiple data connection lines through the multiple adapter units; each adapter unit includes multiple adapter electrodes arranged along a second direction, the second direction intersecting the first direction. The multiple data leads are configured to provide data signals to the sub-pixels of the e-th row pixel unit within the display area during a first time period, and to provide data signals to the sub-pixels of the (e+1)-th row pixel unit within the display area during a second time period, where e is an integer greater than 0. During the first time period, the data signals transmitted by the multiple data leads connected to a switching unit are configured to sequentially correspond to the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, and the second sub-pixel; during the second time period, the data signals transmitted by the multiple data leads connected to the switching unit are configured to sequentially correspond to the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, and the first sub-pixel.

[0185] This embodiment adjusts the order in which data lines and data connection lines are introduced into the first border area by setting a switching unit in the first border area, so that the order of data signals transmitted by the data lead-out line can avoid interference and coupling in the first border area, thereby improving the vertical stripe display caused by this.

[0186] In some exemplary embodiments, a single switching unit includes eight switching electrodes arranged along the second direction, each of which is electrically connected to two Type 1 data leads, four Type 2 data leads, and two Type 1 data leads arranged along the second direction. In some examples, the eight switching electrodes are also electrically connected to one Type 1 data line, two data connection lines, two Type 1 data lines, two data connection lines, and another Type 1 data line arranged along the second direction.

[0187] In some exemplary embodiments, at least one data connection line includes: a first data connection segment extending along the second direction and a second data connection segment extending along the first direction, wherein the first data connection segment of the at least one data connection line is electrically connected to a second type of data line and the second data connection segment, respectively; the connection vias between the first data connection segment and the second type of data line, and the connection vias between the first data connection segment and the second data connection segment are arranged in a V-shape on the orthographic projection of the substrate.

[0188] Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0189] Figure 19 This is a schematic diagram of a display device according to at least one embodiment of the present invention. In some examples, such as... Figure 19 As shown, the display device 91 may include a display panel 910. The display panel 910 may be an OLED display panel. The display device 91 may be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited to this.

[0190] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0191] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A display panel, characterized in that, include: The substrate includes a display area and a first border area located on one side of the display area along a first direction; Multiple sub-pixels are disposed on the substrate and located in the display area, the multiple sub-pixels including multiple first-type sub-pixels and multiple second-type sub-pixels; Multiple data lines and multiple data connection lines are located in the display area. The multiple data lines are configured to provide data signals to the multiple sub-pixels. The multiple data lines include: multiple first-type data lines and multiple second-type data lines. The multiple second-type data lines are electrically connected to the multiple data connection lines. Multiple data leads are located in the first border area, including multiple first-type data leads and multiple second-type data leads. The multiple first-type data leads are electrically connected to the multiple first-type data lines, and the multiple second-type data leads are electrically connected to the multiple second-type data lines through the multiple data connection lines. At least one first shielded signal line is located in the first border area. The at least one first shielded signal line is configured to separate at least one first type data lead and at least one second type data lead. The at least one first type data lead and the at least one second type data lead separated by the at least one first shielded signal line are configured to transmit data signals to different types of sub-pixels.

2. The display panel according to claim 1, characterized in that, The orthographic projection of the at least one first shielding signal line on the substrate lies between the orthographic projections of the at least one first-class data lead and the at least one second-class data lead that transmit data signals to different types of sub-pixels on the substrate.

3. The display panel according to claim 2, characterized in that, The orthographic projection of the at least one first shielded signal line on the substrate does not overlap with the orthographic projections of the at least one first-class data lead and the at least one second-class data lead that are separated on the substrate.

4. The display panel according to claim 2, characterized in that, The at least one first shielded signal line and the adjacent data lead are alternately arranged in different conductive layers.

5. The display panel according to claim 4, characterized in that, The display panel includes: a first gate metal layer and a second gate metal layer sequentially disposed on the substrate, wherein at least one first shielded signal line and an adjacent data lead-out line are alternately arranged on the first gate metal layer and the second gate metal layer.

6. The display panel according to claim 2, characterized in that, At least two adjacent first-shielded signal lines are provided with four Class 2 data leads.

7. The display panel according to claim 1, characterized in that, In a direction perpendicular to the display panel, the at least one first shielded signal line is located between the at least one first type data lead and the at least one second type data lead; the orthographic projection of the at least one first shielded signal line on the substrate at least partially overlaps with the orthographic projections of the at least one first type data lead and the at least one second type data lead on the substrate.

8. The display panel according to claim 7, characterized in that, The display panel includes: a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer sequentially disposed on the substrate; the at least one first shielded signal line is located in the first source / drain metal layer; The at least one first-type data lead is located in the first gate metal layer or the second gate metal layer, and the at least one second-type data lead is located in the second source-drain metal layer; or, the at least one second-type data lead is located in the first gate metal layer or the second gate metal layer, and the at least one first-type data lead is located in the second source-drain metal layer.

9. The display panel according to claim 1, characterized in that, The plurality of first-type sub-pixels includes: a plurality of red sub-pixels and a plurality of blue sub-pixels; the plurality of second-type sub-pixels includes a plurality of green sub-pixels.

10. The display panel according to claim 1, characterized in that, The data connection line includes: a first data connection segment extending along a second direction and a second data connection segment extending along the first direction, wherein the second direction intersects the first direction; the first data connection segment of the data connection line is electrically connected to a second type of data line and the second data connection segment, respectively. The display panel further includes: at least one second shielded signal line located in the display area, wherein the orthographic projection of the at least one second shielded signal line on the substrate is at least partially located between the orthographic projection of at least one first-class data line and at least one data connection line on the substrate, and the at least one second shielded signal line is configured to transmit a constant voltage signal.

11. The display panel according to claim 10, characterized in that, The pixel circuits of the plurality of sub-pixels are electrically connected to a first initial signal line and a second initial signal line, and the at least one second shielded signal line is configured to be electrically connected to either the first initial signal line or the second initial signal line.

12. The display panel according to claim 10, characterized in that, The at least one second shielded signal line includes: a plurality of adapter wires extending along the first direction and alternately connected, the plurality of adapter wires being alternately arranged in different conductive layers.

13. The display panel according to claim 10, characterized in that, The pixel circuits of the plurality of sub-pixels are divided into multiple groups along the second direction. Each group of pixel circuits includes two pixel circuits symmetrically arranged about the centerline extending along the first direction of the group of pixel circuits. The orthographic projection of at least one group of pixel circuits on the substrate overlaps with the orthographic projection of at least two second data connection segments on the substrate. The data lines connected to the at least one group of pixel circuits are located on both sides of the at least two second data connection segments along the second direction.

14. The display panel according to claim 10, characterized in that, The second data connection segment and the multiple data lines are in the same layer, and the first data connection segment is located on the side of the second data connection segment closer to the substrate.

15. The display panel according to claim 10, characterized in that, The connection vias between the first data connection segment and the second type of data line, and the connection vias between the first data connection segment and the second data connection segment, are arranged in a V-shape on the orthographic projection of the substrate.

16. The display panel according to claim 1, characterized in that, The at least one first shielded signal line is configured to transmit electrical signals.

17. A display panel, characterized in that, include: The substrate, including the display area; Multiple sub-pixels are disposed on the substrate and located in the display area, and at least one of the multiple sub-pixels includes a pixel circuit. Multiple data lines and multiple data connection lines are located in the display area. The multiple data lines are electrically connected to the pixel circuits of the multiple sub-pixels. The multiple data lines include: multiple first-type data lines and multiple second-type data lines extending along a first direction; at least one data connection line includes: a first data connection segment extending along a second direction and a second data connection segment extending along the first direction, wherein the first direction and the second direction intersect; the first data connection segment of the at least one data connection line is electrically connected to a second-type data line and a second data connection segment, respectively. At least one second shielded signal line is located in the display area, and the orthographic projection of the at least one second shielded signal line on the substrate is at least partially located between the orthographic projections of at least one first-class data line and at least one data connection line on the substrate.

18. The display panel according to claim 17, characterized in that, The at least one second shielded signal line is configured to transmit electrical signals.

19. The display panel according to claim 18, characterized in that, The pixel circuits of the plurality of sub-pixels are electrically connected to the first initial signal line and the second initial signal line; the at least one second shielded signal line is configured to be electrically connected to the first initial signal line or the second initial signal line.

20. The display panel according to claim 18, characterized in that, The at least one second shielded signal line includes: a plurality of adapter wires extending along the first direction and alternately connected, the plurality of adapter wires being alternately arranged in different conductive layers.

21. The display panel according to claim 18, characterized in that, The pixel circuits of the plurality of sub-pixels are divided into multiple groups along the second direction. Each group of pixel circuits includes two pixel circuits symmetrically arranged about the centerline extending along the first direction of the group of pixel circuits. The orthographic projection of at least one group of pixel circuits on the substrate overlaps with the orthographic projection of at least two second data connection segments on the substrate. The data lines connected to the at least one group of pixel circuits are located on both sides of the at least two second data connection segments along the second direction.

22. The display panel according to claim 18, characterized in that, The second data connection segment and multiple data lines are in the same layer structure, and the first data connection segment is located on the side of the second data connection segment closer to the substrate.

23. The display panel according to claim 18, characterized in that, The substrate further includes: a first border region located on one side of the display area along the first direction; a pixel unit located in the display area includes: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and two third sub-pixels emitting a third color light; The display panel further includes: a plurality of adapter units and a plurality of data leads located in the first frame area, wherein the plurality of data leads are electrically connected to the second data connection segments of the plurality of first-type data lines and the plurality of data connection lines through the plurality of adapter units; each adapter unit includes a plurality of adapter electrodes arranged along the second direction; The multiple data lead-out lines are configured to provide data signals to the sub-pixels of the e-th row pixel unit in the display area during a first time period, and to provide data signals to the sub-pixels of the (e+1)-th row pixel unit in the display area during a second time period, where e is an integer greater than 0; During the first time period, the data signals transmitted by the multiple data leads connected to a switching unit are configured to correspond sequentially to the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, and the second sub-pixel; during the second time period, the data signals transmitted by the multiple data leads connected to a switching unit are configured to correspond sequentially to the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, and the first sub-pixel.

24. The display panel according to claim 23, characterized in that, The first sub-pixel is a red sub-pixel, the second sub-pixel is a blue sub-pixel, and the third sub-pixel is a green sub-pixel.

25. The display panel according to claim 23, characterized in that, A single adapter unit includes eight adapter electrodes arranged along the second direction, which are electrically connected one-to-one with two first-class data leads, four second-class data leads, and two first-class data leads arranged along the second direction.

26. The display panel according to claim 25, characterized in that, The eight adapter electrodes are also electrically connected one-to-one with one of the first type data lines, two data connection lines, two first type data lines, two data connection lines and another first type data line arranged along the second direction.

27. The display panel according to any one of claims 17 to 26, characterized in that, The connection vias between the first data connection segment and the second type of data line, and the connection vias between the first data connection segment and the second data connection segment, are arranged in a V-shape on the orthographic projection of the substrate.

28. A display panel, characterized in that, include: The substrate includes a display area and a first border area located on one side of the display area along a first direction; Multiple pixel units are located in the display area, and each pixel unit includes a first sub-pixel that emits a first color light, a second sub-pixel that emits a second color light, and two third sub-pixels that emit a third color light. Multiple data lines and multiple data connection lines are located in the display area. The multiple data lines include multiple first-type data lines and multiple second-type data lines. The multiple data lines are configured to transmit data signals to the sub-pixels of the multiple pixel units. The multiple second-type data lines are electrically connected to the multiple data connection lines. Multiple data lead-out lines and multiple adapter units are located in the first frame area. The multiple data lead-out lines are electrically connected to the multiple first-type data lines and the multiple data connection lines through the multiple adapter units. Each adapter unit includes multiple adapter electrodes arranged along a second direction, which intersects the first direction. The multiple data lead-out lines are configured to provide data signals to the sub-pixels of the e-th row pixel unit in the display area during a first time period, and to provide data signals to the sub-pixels of the (e+1)-th row pixel unit in the display area during a second time period, where e is an integer greater than 0; During the first time period, the data signals transmitted by the multiple data leads connected to a switching unit are configured to correspond sequentially to the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, and the second sub-pixel; during the second time period, the data signals transmitted by the multiple data leads connected to the switching unit are configured to correspond sequentially to the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, and the first sub-pixel.

29. The display panel according to claim 28, characterized in that, A single adapter unit includes eight adapter electrodes arranged along the second direction, which are electrically connected one-to-one with two first-class data leads, four second-class data leads, and two first-class data leads arranged along the second direction.

30. The display panel according to claim 29, characterized in that, The eight adapter electrodes are also electrically connected one-to-one with one of the first type data lines, two data connection lines, two first type data lines, two data connection lines and another first type data line arranged along the second direction.

31. The display panel according to claim 28, characterized in that, At least one data connection line includes: a first data connection segment extending along the second direction and a second data connection segment extending along the first direction, wherein the first data connection segment of the at least one data connection line is electrically connected to a second type of data line and the second data connection segment, respectively. The connection vias between the first data connection segment and the second type of data line, and the connection vias between the first data connection segment and the second data connection segment, are arranged in a V-shape on the orthographic projection of the substrate.

32. A display device, characterized in that, It includes the display panel as described in any one of claims 1 to 16; or the display panel as described in any one of claims 17 to 27; or the display panel as described in any one of claims 28 to 31.

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