YAO32 development mainboard

Abstract

The utility model relates to the field of embedded electronic circuits, discloses a YAO32 development mainboard, and aims to overcome the defects of an existing development board in the aspects of compatibility, electrical characteristics and cost control. The clock module, the debugging and downloading module, the external interface module, the key module, the indicator light module, the power management module and the USB module are connected with the master control module, the master control module adopts a YAO32F107Q100 chip, and the functional modules are compact in design, reasonable in matching and convenient to use. The system has the advantages of perfect interface signal lead-out, flexible debugging mode, stable power supply system and the like. According to the development mainboard, by optimizing a USB circuit, power supply voltage stabilization, clock source configuration and external pin layout, the adaptability and debugging supporting capacity of the development mainboard and a YAO32F107Q100 chip are enhanced, the complexity and manufacturing cost of the whole system are remarkably reduced on the premise that the function practicability is guaranteed, and the development mainboard is suitable for development and evaluation scenes of the chip.

Description

Technical Field

[0001] This utility model relates to the field of embedded electronic circuits, and in particular to a YAO32 development motherboard. Background Technology

[0002] As a hardware experimental platform for embedded system development, microcontroller development boards often have general-purpose designs that cannot meet the optimization requirements of specific chips. Existing development boards cannot meet the debugging compatibility, interface electrical characteristics, and power timing issues of the YAO32F107Q100 chip. At the same time, existing development boards have redundant functions and high costs. Utility Model Content

[0003] To address the aforementioned issues, the purpose of this invention is to provide a low-cost YAO32 development motherboard that is compatible with the YAO32F107Q100 chip, exhibiting good versatility and debugging adaptability.

[0004] The technical solution adopted in this utility model is as follows:

[0005] A YAO32 development motherboard includes a main control module and connected to it a clock module, a debug download module, an external interface module, a button module, an indicator light module, a power management module, and a USB module. The modules are designed to work closely together, with clear functions and a reasonable structure, which significantly reduces system complexity and cost.

[0006] Furthermore, the core of the aforementioned main control module is the YAO32F107Q100 chip (U1).

[0007] The Micro-USB circuit (USB2) of the aforementioned USB module is connected to the USB OTG FS pin of the MCU. The USB_DP and USB_DM signals of the MCU are connected to the D+ and D- pins of the Micro-USB circuit through a 22Ω series resistor, respectively. A 1.5kΩ pull-up resistor is connected to 3.3V on the USB_DP line. The ID pin of the Micro-USB circuit is connected to the USB_ID input of the MCU, and the VBUS pin of the Micro-USB is connected to the power management module.

[0008] Furthermore, the input and output terminals of the YAO1117ST-3.3 in the voltage regulation circuit of the aforementioned power management module are equipped with a 10µF electrolytic capacitor and a 0.1µF decoupling capacitor, respectively. The input terminal is connected to a +5V power supply, and the output terminal outputs 3.3V.

[0009] Furthermore, the aforementioned external interface module consists of three multi-pin connectors, which bring out the function pins of the MCU's memory interface (FSMC), analog-to-digital converter (ADC), serial communication (USART, SPI, I2C), timer (TIM), debug interface (JTAG), and USB.

[0010] Furthermore, the main clock crystal X2 (8MHz) of the above clock module is connected to the OSC_IN and OSC_OUT pins of the MCU through 20pF load capacitors at both ends, and an internal 1MΩ resistor is connected in parallel. The low-speed clock crystal X1 (32.768kHz) is connected to the OSC32_IN and OSC32_OUT pins of the MCU through two 10pF load capacitors.

[0011] Furthermore, the aforementioned debugging and download module comprises two parts: a USB-to-serial circuit and a hardware debugging interface. The USB D+ and D- pins of the CH340N circuit are connected to the Type-C interface socket via a 22Ω resistor and pulled down to GND via a 5.1kΩ resistor. The CH340N integrates a 3.3V voltage regulator, with a 0.1µF capacitor added to its V3 pin for decoupling. The CH340N's UART interface pins TXD and RXD are connected to the MCU's USART pin via configurable jumpers. The middle pin of the Boot mode selection jumper circuit H4 is connected to the MCU's BOOT0 and BOOT1 pins respectively. One side of the pin is connected to a 3.3V power supply, and the other side is grounded. Each pin is pulled down to ground (BOOT0 by default) or pulled up / down to a fixed level via a 10kΩ resistor.

[0012] Furthermore, one end of the KEY3 of the aforementioned button module is connected to the NRST pin of the MCU, and the other end is grounded. One end of the user buttons KEY1 and KEY2 is connected to the general-purpose input pin of the MCU, and the other end is grounded. Pull-up resistors are configured at the pins of the MCU.

[0013] Furthermore, the anode of the aforementioned indicator module LED2 is connected to a +3.3V power supply via a current-limiting resistor, and the cathode is grounded; LED0 and LED1 are respectively connected between two GPIO pins of the MCU and the power supply / ground via current-limiting resistors. Attached Figure Description

[0014] Figure 1 This is the circuit schematic diagram of the main control module of this utility model;

[0015] Figure 2 This is the circuit schematic diagram of the clock module of this utility model;

[0016] Figure 3 This is the circuit schematic diagram of the debugging and downloading module of this utility model;

[0017] Figure 4 This is the circuit schematic diagram of the external interface module of this utility model;

[0018] Figure 5 This is the circuit schematic diagram of the button module of this utility model;

[0019] Figure 6 This is the circuit schematic diagram of the indicator light module of this utility model;

[0020] Figure 7 This is the circuit schematic diagram of the power management module of this utility model;

[0021] Figure 8 This is the circuit schematic diagram of the USB module of this utility model;

[0022] Figure 9 This is a structural block diagram of the YAO32 development motherboard of this utility model. Detailed Implementation

[0023] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Unless otherwise specified, the techniques used in the embodiments are conventional means well known to those skilled in the art.

[0024] It should be noted that, unless otherwise stated, the technical or scientific terms used in this utility model should be understood in their ordinary sense by those skilled in the art to which this utility model pertains. Terms such as "connection" and "linked" should be interpreted broadly. For example, they can refer to a mechanical connection or an electrical connection; they can be a direct connection or an indirect connection via an intermediate medium. The terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the included element.

[0025] like Figures 1 to 9As shown, a YAO32 development motherboard includes a main control module and connected to it a clock module, a debug download module, an external interface module, a button module, an indicator light module, a power management module, and a USB module. The modules are designed to work closely together, with streamlined and practical functions, significantly reducing system complexity and cost, thereby addressing the shortcomings of existing development boards in terms of debugging compatibility, interface electrical characteristics, and power timing.

[0026] The aforementioned power management module provides a stable power supply to all parts of the system board. The +5V input is connected to pin 1 (VIN) of the ME6211C low-dropout regulator chip U2. This chip provides a stable voltage to the analog power supply module. Pin 2 is grounded (GND), and pin 3 is the chip enable control pin (CE), which in this design is directly connected to the +5V power supply to keep the chip continuously operational. Pin 5 (VOUT) of U2 outputs the analog power supply, connected to the VDDA power network to supply the MCU analog module. A 1μF capacitor C5 and a 0.1μF capacitor C6 are connected in parallel between this output and ground for low-frequency and high-frequency ripple filtering, respectively. Capacitors C3 and C4 (0.1μF and 1μF) are connected in parallel between the input VIN and ground for power input stabilization and transient interference suppression. The digital power supply section is implemented using the YAO1117ST-3.3 linear regulator chip U3. Its pin 3 (VIN) is connected to the +5V main power supply, pin 1 (ADJ) is the adjustment pin connected to ground, and pin 2 (VOUT) is the output terminal, providing a stable 3.3V voltage to the digital section of the main control chip. A 0.1μF capacitor C7 and a 10μF capacitor C8 are connected in parallel between the input terminal and ground of U3; a 0.1μF capacitor C9 and a 10μF capacitor C10 are connected in parallel at the output terminal to ensure power supply stability and overshoot suppression. Five 0.1μF ceramic capacitors C11 to C16 are connected in parallel on the output bus, with one end of each capacitor connected to VCC and the other end grounded. This distributed filtering design further improves the power system's anti-interference capability and transient response speed. Pins 1, 3, 5, and 7 of pin header H1 are connected to the RXD and TXD signals of the CH340N chip, respectively. Pins 2, 4, 6, and 8 are connected to the USART1_TX, USART1_RX, USART2_TX, and USART2_RX signal ports of the main control chip, respectively, for serial data interaction.

[0027] The aforementioned external interface module is used to bring out the pin signals of the main control chip, facilitating external circuit connection and functional expansion. This module uses dual-row headers J1, J2, and J3 to bring out most of the GPIOs and peripheral function ports of the main control module U1 according to their functions. Pins 1, 2, 3, 4, 5, 26, 27, 28, 29, and 30 of header J1 are connected to PE2-PE11 of the main control module U1, pins 9, 10, 11, 12, 21, and 22 are connected to PC0-PC5 of the main control module U1, pins 6, 7, and 8 are connected to PC13-PC15 of the main control module U1, pins 13-20 are connected to PA0-PA7 of the main control module U1, pins 23-25 ​​are connected to PB0-PB2 of the main control module U1, and pins 31 and 32 are grounded. Pins 5 to 8 of header J2 are connected to PE12 to PE15 of U1 of the main control module, pins 9 to 14 are connected to PB10 to PB14 of U1 of the main control module, pins 15 to 22 are connected to PD8 to PD15 of U1 of the main control module, pins 23 to 26 are connected to PC6 to PC9 of U1 of the main control module, pins 27 to 30 are connected to PA9 to PA12 of U1 of the main control module, pins 1 to 4 are grounded, and pins 31 and 32 are connected to VCC. Pins 11 and 12 of header J3 are connected to PA8 and PA15 of U1 of the main control module, respectively. Pins 13 to 15 are connected to PC10 to PC12 of U1 of the main control module, respectively. Pins 16 to 23 are connected to PD0 to PD7 of U1 of the main control module, respectively. Pins 24 to 30 are connected to PB3 to PB9 of U1 of the main control module, respectively. Pins 31 and 32 are connected to PE0 and PE1 of U1 of the main control module, respectively. Pins 1 to 4 are connected to +5V power supply, and pins 5 to 10 are connected to VCC.

[0028] The aforementioned clock module includes two crystal oscillator circuits, one for high-frequency operation and one for low-frequency operation. The master clock crystal oscillator X2 (8MHz) is connected to the OSC_IN and OSC_OUT pins of the main control module's U1 via 20pF load capacitors. An internal 1MΩ resistor is connected in parallel to stabilize the oscillation and provide the main clock frequency for the main control module. The low-speed clock crystal oscillator X1 (32.768kHz) is connected to the OSC32_IN and OSC32_OUT pins of the main control module's U1 via two 10pF load capacitors, providing an independent clock source for the real-time clock (RTC).

[0029] The aforementioned debugging and download module is used for program burning and debugging communication. Pins 1 to 6 of H2 are grounded. Pins 1 and 4 of the SWD interface H3 are grounded and VCC respectively, and pins 2 and 3 are connected to PA14 and PA13 of the main control module U1 respectively, allowing direct connection to debuggers such as ST-LINK for online simulation debugging and firmware download. Pins 1 and 2 and pins 3 and 4 of the BOOT selection circuit H4 are connected to VCC and ground respectively, and pins 3 and 4 are connected to BOOT0 and PB2 pins of the main control module U1 respectively. By inserting and removing jumpers, the connection of the BOOT0 / 1 pin can be selected to be high or low, thus conveniently switching the startup mode of the main control module.

[0030] The aforementioned button module is used for manual control reset and providing user input signals. The button module includes a reset button circuit and two user button circuits. The reset button KEY1 is a self-reset switch, with one end connected to the NRST pin of the main control module U1 and the other end grounded. A 10kΩ resistor pulls the NRST pin up to 3.3V. A 0.1µF capacitor is connected in series between NRST and ground as a reset delay capacitor, generating a power-on reset signal for the main control module U1 upon power-on. Pressing the button immediately pulls NRST low to achieve manual reset, thus ensuring reliable reset and restart of the main control module. One end of the user button KEY2 is connected to the PE2 pin of the main control module U1, and the other end is grounded. A capacitor is connected in parallel with the user button KEY2. One end of the user button KEY3 is connected to the PE3 pin of the main control module U1, and the other end is grounded. A capacitor is connected in parallel with the user button KEY3.

[0031] The aforementioned indicator module is used to indicate power status and provide operation prompts. LED2 serves as a power indicator, with its anode connected to a +3.3V power supply via a current-limiting resistor and its cathode grounded. LED0 and LED1 are programmable indicator lights, with one end connected to PE0 and PE1 of the main control module U1 via current-limiting resistors, respectively, and the other end grounded.

[0032] The aforementioned USB module is used to implement USB communication functions and power management. It includes a Type-C interface (USB1), a Micro-USB interface (USB2), a CH340N serial port chip, and its peripheral circuitry. This enables data communication between the main control chip and the host computer, and allows switching between USB OTG and USB-to-serial functions via jumper connections. Multiple VBUS pins (A4, A9, B4, B9) of USB1 are connected to the +5V_IN power supply terminal, via an overcurrent protection device F1 to ensure power-on safety. The GND pins (A1, A12, B12, etc.) are grounded, forming a power supply loop. Pin A5 is grounded through a 5.1kΩ resistor. A 1.5kΩ pull-up resistor R5 is further connected in series to VCC on the D+ signal branch. Pin 1 (VBUS) of USB2 is connected to +5V_IN, protected by fuse F1, providing power input. Pin 5 (GND) is grounded. Pins 2 and 3 are D− and D+ signal lines, respectively. Pin 4 (ID) is not connected, indicating that the USB interface is in device mode by default. The CH340N chip is used for USB-to-serial communication. Its pins 1 (UD+) and 2 (UD−) are directly connected to the USB data line, supporting high-speed serial data communication. Pin 3 is grounded, pin 5 is connected to VCC, and a 0.1μF decoupling capacitor C24 is connected in parallel. Pins 6 and 7 are used as serial port output TXD and input RXD, respectively. Pin 8 (V3) can configure the chip's operating voltage mode. A jumper selection structure SW1 is set in the USB_DP and USB_DM lines. The USB differential signal connection target is selected by a physical jumper cap. It can be connected to the MCU port to support USB peripheral or host functions, or connected to the CH340N as a virtual serial port. A 0.1μF filter capacitor C21 is placed between +5V_IN and ground. The above structure ensures that when the system is using an external 5V power supply, it can stably provide 3.3V and VDDA voltages to the analog and digital circuits respectively, and improve the overall anti-interference performance of the power supply through a sufficient number of decoupling and filtering capacitors, thereby meeting the accuracy and stability requirements of the main control module and peripheral modules for the power supply voltage.

[0033] This invention provides a solution that meets all the development and debugging needs of the YAO32F107Q100 chip at a lower cost. Compared with the interface incompatibility and signal interference problems that may exist in traditional development boards, this invention provides more stable and reliable peripheral connection performance, overcomes the defects of existing development boards that do not support the chip's boot mode or debugging interface, and provides a low-cost YAO32 development motherboard adapted to the YAO32F107Q100 chip.

[0034] The above description is only a preferred embodiment of the present utility model, and not a limitation thereof. Any equivalent changes and modifications made in accordance with the scope of the present utility model without departing from the spirit and scope of the present utility model shall be within the scope of patent protection of the present utility model.

Claims

1. A YAO32 development motherboard, characterized in that, The YAO32 development motherboard includes a main control module and connected to it a clock module, a debug download module, an external interface module, a button module, an indicator light module, a power management module, and a USB module. The USB module includes a Type-C interface (USB1) circuit, a Micro-USB interface (USB2) circuit, and a CH340N USB to serial port circuit. The DP signal line of the Type-C interface (USB1) circuit is connected to the USB_DP pin of the main control module via resistor R24, and the DM signal line is connected to the USB_DM pin of the main control module via resistor R25. The DP signal line is connected to a 3.3V power supply via a pull-up resistor, and the VBUS pin is grounded via a decoupling capacitor. The Micro-USB interface (USB2) circuit includes a power switch SW1 and a fuse F1. The external interface module consists of three multi-pin connectors, which bring out the MCU's memory interface (FSMC), analog-to-digital converter (ADC), serial communication (USART, SPI, I2C), timer (TIM), debug interface (JTAG), and USB function pins of the main control module.

2. The YAO32 development motherboard according to claim 1, characterized in that, The main control module uses the YAO32F107Q100 chip, and its multiple GPIO pins, PA0 to PA15, PB0 to PB15, and PC0 to PC15, are connected to other modules.

3. The YAO32 development motherboard according to claim 1, characterized in that, The voltage regulator chip in the power management module is model YAO1117ST-3.

3. Its input terminal VIN is grounded through a capacitor, and its output terminal TAB is grounded through a capacitor.

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