Substrate, display panel including substrate, and electronic device including display device

Abstract

The utility model relates to a substrate, a display panel including the substrate, and an electronic device including the display device. The substrate includes: a first base layer; an adhesive layer on the first base layer, the adhesive layer including at least one trench; a second base layer on the adhesive layer; and a barrier overlapping the at least one trench, the at least one trench penetrating the adhesive layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0047216, filed on April 8, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure relate to a substrate, a display panel including the substrate, and an electronic device including a display device. Background Technology

[0004] With the development of technology, display devices may include electronic components for performing various functions therein. When the electronic components are driven, at least some electromagnetic waves (e.g., static electricity) may be generated, and the corresponding electromagnetic waves may be introduced into the display device.

[0005] The information disclosed in this background section is intended to enhance the understanding of the background technology of this disclosure, and therefore may contain information that does not constitute prior art. Utility Model Content

[0006] When the substrate of a display device is made of plastic, it may be susceptible to electrostatic discharge (ESD) (e.g., highly susceptible to ESD). For example, introduced electromagnetic waves may charge at least a portion of the substrate. Consequently, the operation of electronic components may be affected, and there is a risk that the reliability of the display device's drive may decrease.

[0007] Embodiments of this disclosure may relate to substrates, display panels, and electronic devices in which static electricity introduced from the outside is relatively stably shielded, thereby improving the reliability of the drive.

[0008] According to one or more embodiments of the present disclosure, the substrate includes: a first base layer; an adhesive layer on the first base layer, the adhesive layer including at least one trench; a second base layer on the adhesive layer; and a barrier overlapping the at least one trench. The at least one trench penetrates the adhesive layer.

[0009] In one implementation, the barrier may be located in the edge region surrounding the central region of the substrate.

[0010] In an implementation, the central region may include: a first side; a second side opposite to the first side; a third side connecting the first and second sides; and a fourth side opposite to the third side. The barrier may include: a first barrier adjacent to the corner between the first and fourth sides; a second barrier adjacent to the corner between the second and third sides; and a third barrier adjacent to the corner between the first and third sides.

[0011] In some implementations, the barrier may include a dielectric material.

[0012] In this implementation, the first base layer and the second base layer may be flexible.

[0013] In this embodiment, the first base layer and the second base layer may include polyimide.

[0014] In some embodiments, the adhesive layer may include amorphous silicon.

[0015] According to one or more embodiments of the present disclosure, a display panel includes: a ground layer; a first base layer on the ground layer; an adhesive layer on the first base layer; a second base layer on the adhesive layer; and a barrier in contact with a surface of the adhesive layer and connected to the ground layer.

[0016] In one implementation, the barrier may surround the display area and may be located in a non-display area different from the display area.

[0017] In one implementation, the barrier may come into contact with the first base layer.

[0018] In this implementation, the barrier may come into contact with the second base layer.

[0019] In an implementation, the grounding layer may have a grounding potential.

[0020] According to one or more embodiments of the present disclosure, an electronic device includes: a processor for providing input image data; and a display device for displaying an image based on the input image data, the display device including: a ground layer; a first base layer; an adhesive layer on the first base layer and including at least one trench; a second base layer on the adhesive layer; and a barrier overlapping with the at least one trench and penetrating the adhesive layer.

[0021] In an implementation, the grounding layer may have a grounding potential.

[0022] In one implementation, the barrier may have higher conductivity than the adhesive layer.

[0023] In one implementation, the barrier may surround the display area and may be located in a non-display area different from the display area.

[0024] In this implementation, the barrier can be connected to the grounding layer via a connecting wire.

[0025] In this implementation, the connecting line may overlap with the non-display area.

[0026] In one embodiment, the electronic device may further include: a display panel configured to display an image through a display area; and a data driver configured to provide data signals to the display panel and located on one side of the display panel. The barrier may not be located on one side of the display panel.

[0027] In an embodiment, the electronic device may further include a bias supply configured to provide a bias voltage to the barrier, and the bias voltage may have a low-level voltage during the cycle. Attached Figure Description

[0028] The above and other aspects and features of this disclosure will become clearer from the following detailed description of exemplary, non-limiting embodiments with reference to the accompanying drawings.

[0029] Figure 1 This is a schematic perspective view showing a display device according to an embodiment of the present disclosure.

[0030] Figure 2 It is shown Figure 1 A plan view of the components of the display device shown.

[0031] Figure 3 It is shown schematically. Figure 2 The cross-sectional view of the stacked structure of the display panels shown.

[0032] Figure 4 It is shown that it includes Figure 2 A plan view of an embodiment of the substrate in the display panel shown.

[0033] Figure 5 It is along Figure 2 The cross-sectional view of the display panel is taken by line I-I'.

[0034] Figure 6 It is shown Figure 5 A cross-sectional view of an embodiment of the substrate shown.

[0035] Figure 7 It is shown Figure 6 A plan view of an embodiment of the adhesive layer and barrier unit shown.

[0036] Figure 8 It is shown Figure 6 A plan view of an embodiment of the adhesive layer and barrier unit shown.

[0037] Figure 9 It is shown Figure 6 A plan view of an embodiment of the adhesive layer and barrier unit shown.

[0038] Figure 10 It shows the voltage applicator and Figure 5A cross-sectional view of an embodiment of the substrate shown.

[0039] Figure 11 It is shown by Figure 10 The waveform diagram shows an embodiment of the bias voltage provided by the voltage applicator shown.

[0040] Figure 12 It is shown Figure 5 A cross-sectional view of an embodiment of the substrate shown.

[0041] Figure 13 It is shown Figure 5 A cross-sectional view of an embodiment of the substrate shown.

[0042] Figure 14 This is a block diagram illustrating an electronic device including a display device according to one or more embodiments of the present disclosure. Detailed Implementation

[0043] In the following description, embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals throughout denote the same elements. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, unnecessary processes, elements, and techniques for a full understanding of the aspects and features of this disclosure by those skilled in the art are omitted from description. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore redundant descriptions thereof are not required.

[0044] When a particular implementation can be carried out differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0045] Furthermore, as those skilled in the art will understand, in consideration of the entirety of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with one another, and may be technically interlocked and operated in a variety of suitable ways, and each embodiment may be implemented independently of one another or in combination with one another in any suitable way, unless otherwise stated or implied.

[0046] In the accompanying drawings, for clarity, the relative dimensions, thicknesses, and ratios of elements, layers, and regions may be exaggerated and / or simplified. For ease of illustration, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” “upper,” etc., may be used herein to describe the relationship of one element or feature to another(s) as shown in the drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will consequently be oriented “above” other elements or features. Thus, the exemplary terms “below” and “below” can encompass both above and below orientations. The device may have other orientations (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0047] Furthermore, it should be anticipated that the shapes shown in the accompanying drawings may vary in practice depending on, for example, tolerances and / or manufacturing techniques. Therefore, embodiments of this disclosure should not be construed as limited to the specific shapes shown in the figures, and should be interpreted in light of possible changes in shape due to, for example, manufacturing processes. Consequently, the shapes shown in the figures may not depict the actual shape of an area of ​​the device, and this disclosure is not limited thereto.

[0048] In the accompanying figures, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other or substantially perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0049] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, first component, first region, first layer, or first portion described below may be referred to as a second element, second component, second region, second layer, or second portion.

[0050] It will be understood that when an element or layer is referred to as being "on," "connected to," or "attached to" another element or layer, it may be directly on, directly connected to, or directly attached to the other element or layer, or there may be one or more intervening elements, layers, regions, or components. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it may be directly electrically connected to the other layer, region, or element, and / or may be indirectly electrically connected with one or more intervening layers, regions, or elements therebetween. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0051] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit this disclosure. As used herein, the singular forms “a” and “an” are intended to also include the plural forms unless the context clearly indicates otherwise. It will also be understood that, when used in this specification, the terms “comprising,” “including,” “including,” “having,” “having,” and “possessing” designate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” refers to A, B, or A and B. When following an element in a list, expressions such as “at least one of” modify the elements of the entire list rather than individual elements in the list. For example, the expressions “at least one of a, b and c” and “at least one of the group consisting of a, b and c” mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof.

[0052] As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent biases in measured or calculated values ​​that will be recognized by those skilled in the art. Furthermore, the use of “may” in describing embodiments of this disclosure means “one or more embodiments of this disclosure.” As used herein, the terms “use,” “using,” and “used” are to be understood as synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0054] Figure 1 This is a schematic perspective view showing a display device according to an embodiment of the present disclosure.

[0055] Figure 2 It is shown Figure 1 The diagram shows a plan view of the components of the display device.

[0056] refer to Figure 1 The display device DD may include a display area DD_DA in which an image is displayed, and a non-display area DD_NDA disposed at at least one side of the display area DD_DA (e.g., disposed in or on at least one side of the display area DD_DA). The non-display area DD_NDA may be an area in which no image is displayed.

[0057] Figure 1 The display device DD shown can be configured in various suitable shapes. For example, the display device DD can be configured as a rectangular plate shape with two pairs of parallel or substantially parallel sides, but this disclosure is not limited thereto. When the display device DD is configured as a rectangular plate shape, either pair of sides can be configured to be longer than the other pair of sides. In some embodiments, for ease of illustration, the display device DD is shown as a rectangular shape with a pair of long sides and a pair of short sides. The direction of extension of the long side is indicated as a second direction DR2. The direction of extension of the short side is indicated as a first direction DR1. The thickness direction of the display device DD is indicated as a third direction DR3. In a display device DD configured as a rectangular plate shape, the corner portion where one long side and one short side contact each other can have a rounded shape.

[0058] At least a portion of the display device DD may be flexible. For example, the display device DD may include a flexible portion, and the flexible portion of the display device DD may be bent. However, this disclosure is not limited thereto.

[0059] refer to Figure 2 The display device DD may include a display panel DP (e.g., display unit or pixel unit), a driving circuit chip DIC (or data driver), and a printed circuit board PCB.

[0060] The display panel DP may include the display area DP_DA in which the image is displayed, and the non-display area DP_NDA located around the display area DP_DA.

[0061] The display panel DP may include multiple pixels PXL. For example, the display panel DP may include pixels PXL disposed in the display area DP_DA. Each pixel PXL may include at least one light-emitting element and pixel circuitry for driving the light-emitting element. The pixel circuitry may include, for example, a switching transistor for transmitting a data signal in response to a gate signal, a storage capacitor for storing the data signal transmitted through the switching transistor, and a driving transistor for providing a driving current corresponding to the stored data signal to at least one light-emitting element.

[0062] The display panel (DP) may include multiple signal lines (SGL). The signal lines (SGL) may include a gate line (GSL), a data line (DSL), a power line (PL), and a control signal line (CSL). The power line (PL) may be connected to the pixel (PXL). The control signal line (CSL) provides control signals to the scan drive circuit (GDC).

[0063] Each of the gate lines GSL can be connected to a corresponding pixel in the pixel PXL. Each of the data lines DSL can be connected to a corresponding pixel in the pixel PXL. For example, any one of the pixels PXL can be connected to both the gate line GSL and the data line DSL, and can emit light with a brightness corresponding to the data signal (e.g., data voltage) in response to a gate signal. The gate signal can be provided through the gate line GSL, and the data signal can be provided through the data line DSL.

[0064] The gate line GSL can extend along the first direction DR1 and can be arranged along the second direction DR2. The data line DSL can extend along the second direction DR2 and can be arranged along the first direction DR1.

[0065] The scan drive circuit GDC can generate multiple gate signals and output them sequentially to the gate line GSL. The gate signals may include a start pulse and a clock signal (e.g., a scan clock signal and a carry clock signal).

[0066] The driving circuit chip DIC can be disposed on one side of the display panel DP. For example, the driving circuit chip DIC can be disposed on the side of the display panel DP in the direction opposite to the second direction DR2. Therefore, one side of the display panel DP can be less susceptible to the effects of static electricity introduced from the outside. For example, at least a portion of the static electricity introduced into the display panel DP from the outside can be blocked by the driving circuit chip DIC disposed on one side of the display panel DP.

[0067] The driver circuit chip (DIC) can be connected to the data line (DSL) and the control signal line (CSL). In some embodiments, the driver circuit chip (DIC) may include data driver circuitry for generating data signals.

[0068] The driver circuit chip (DIC) and the printed circuit board (PCB) can exchange electrical signals. For example, the DIC and PCB can be connected via signal line CL. The DIC receives data control signals and image data from the PCB via signal line CL. Therefore, the DIC can generate data signals corresponding to the image data. The DIC can provide the generated data signals to the display panel (DP). Image data can be generated by rearranging input data (e.g., raw image data) provided from an external source (e.g., from a processor).

[0069] Figure 3 It is shown schematically. Figure 2 The cross-sectional view of the stacked structure of the display panels shown.

[0070] refer to Figure 3 The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and a packaging layer ENC.

[0071] The substrate SUB can form the bottom surface of the display panel DP. The pixel circuit layer PCL, the display element layer DPL, and the encapsulation layer ENC can be sequentially disposed on the substrate SUB. However, this disclosure is not limited thereto. For example, Figure 3 In addition to the pixel circuit layer PCL, display element layer DPL, and encapsulation layer ENC shown (e.g., besides...), Figure 3 The layers shown (excluding the pixel circuit layer PCL, display element layer DPL, and encapsulation layer ENC) can be disposed on the substrate SUB.

[0072] The pixel circuit layer (PCL) can be disposed on the substrate (SUB) and can include multiple transistors and signal lines connected to the transistors. For example, each transistor can be configured such that a semiconductor layer, a gate electrode, a first terminal, and a second terminal are stacked sequentially with an insulating layer interposed therebetween. The semiconductor layer can include amorphous silicon, monocrystalline silicon, polycrystalline silicon, low-temperature polycrystalline silicon, organic semiconductors, and / or oxide semiconductors. The gate electrode, the first terminal, and the second terminal can include one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo), but this disclosure is not limited thereto. Furthermore, the pixel circuit layer (PCL) can include at least one insulating layer.

[0073] The display element layer (DPL) can be disposed on the pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements for emitting light. The light-emitting elements may include organic light-emitting diodes (OLEDs), inorganic light-emitting diodes (LEDs), etc. However, this disclosure is not limited thereto. For example, the light-emitting elements may include quantum dot LEDs, etc.

[0074] The encapsulation layer ENC can be disposed on the display element layer DPL. The encapsulation layer ENC can be an encapsulation substrate, or it can be configured as a multi-layer encapsulation layer. When the encapsulation layer ENC is configured as such, it can include inorganic and / or organic layers. For example, the encapsulation layer ENC can be configured such that inorganic layers, organic layers, and inorganic layers are stacked sequentially. The encapsulation layer ENC can prevent or substantially prevent external air and / or moisture from penetrating into the display element layer DPL and the pixel circuit layer PCL.

[0075] Figure 4 It is shown that it includes Figure 2 A plan view of an embodiment of the substrate in the display panel shown.

[0076] refer to Figure 4 The display panel DP may include a substrate SUB and multiple pixels PXL disposed on the substrate SUB. Figure 4 The substrate SUB shown can be compared with the above reference. Figure 3 The substrates described are the same or substantially the same. Therefore, redundant descriptions of them will not be repeated below.

[0077] The substrate SUB can be formed as a region with a rectangular shape (e.g., a region). However, the number of regions disposed in the substrate SUB can be varied depending on the needs or expectations, and the shape of the substrate SUB can be varied depending on the regions disposed in the substrate SUB.

[0078] The substrate SUB may include a suitable flexible material (e.g., it may be made of a suitable flexible material) to bend or fold, and may have a single-layer or multi-layer structure. For example, the substrate SUB may include a polyimide substrate. However, the materials constituting the substrate SUB are not limited thereto. For example, the substrate SUB may include an insulating material such as glass or resin (e.g., it may be made of an insulating material).

[0079] The substrate SUB may include a display area (e.g., a central area) EA and a non-display area (e.g., an edge area) NEA. The display area EA may be an area in which pixels PXL are set to display an image, and the non-display area NEA may be an area in which pixels PXL are not set, such that the image is not displayed in the non-display area NEA. Figure 4The display area EA and the non-display area NEA shown can be respectively associated with the above references. Figure 2 The description includes the display area DP_DA and the non-display area DP_NDA. Additionally... Figure 4 The display area EA and the non-display area NEA shown can respectively correspond to the above references. Figure 1 The display device DD is described as having a display area DD_DA and a non-display area DD_NDA.

[0080] The non-display area NEA may correspond to the bezel area of ​​the display device DD. A portion of the driving unit (e.g., driver, driving circuit, or driving integrated circuit) for driving the pixel PXL and a portion of the line unit (e.g., fan-out line) connecting the pixel PXL and the driving unit to each other may be disposed in the non-display area NEA. The driving unit may include the scan driving circuit GDC (e.g., see...). Figure 2 (and the driver circuit chip DIC. However, this disclosure is not limited thereto.)

[0081] Pixels PXL can be disposed in the display area EA of the substrate SUB. Each of the pixels PXL can be the smallest unit for displaying an image. Each of the pixels PXL can include a light-emitting element for emitting white light and / or colored light. Each of the pixels PXL can emit light of any desired color from red, green, and blue. However, this disclosure is not limited thereto, and each of the pixels PXL can emit light of a desired color such as cyan, magenta, or yellow.

[0082] Pixels PXL can be arranged in a matrix form along rows (e.g., pixel rows) extending in a first direction DR1 and columns (e.g., pixel columns) extending in a second direction DR2 that intersects or crosses the first direction DR1. However, the arrangement of pixels PXL is not particularly limited to this, and pixels PXL can be arranged in various suitable forms. In the figures, pixels PXL are shown as having a rectangular shape. However, this disclosure is not limited to this, and pixels PXL can have various suitable shapes. Furthermore, when multiple pixels PXL are provided, the multiple pixels PXL can be configured to have different areas (e.g., sizes) from each other. For example, in the case where pixels PXL emit different colors of light from each other, pixels PXL can be configured to have different areas (e.g., different sizes) from each other, or can have different shapes from each other depending on each color.

[0083] Figure 5 It is along Figure 2 The cross-sectional view of the display panel is taken by line I-I'.

[0084] refer to Figure 5The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and a packaging layer ENC.

[0085] Figure 5 The substrate SUB, pixel circuit layer PCL, display element layer DPL, and encapsulation layer ENC shown can be compared with the above reference. Figure 3 The substrate (SUB), pixel circuit layer (PCL), display element layer (DPL), and encapsulation layer (ENC) are described as being the same or substantially the same. Therefore, redundant descriptions of them need not be repeated.

[0086] The substrate SUB may include a ground layer GL, a first base layer BL1, an adhesive layer AL, and a second base layer BL2.

[0087] The ground layer GL can be the rear surface of the substrate SUB. For example, a first base layer BL1, an adhesive layer AL, and a second base layer BL2 can be sequentially disposed on the ground layer GL. However, this disclosure is not limited thereto. For example, in the following description, the ground layer GL is described in more detail as an assembly of the substrate SUB. However, the ground layer GL can be an assembly separate from the substrate SUB. For example, the ground layer GL can be disposed on the rear surface of the substrate SUB.

[0088] A ground plane GL can attenuate the intensity of electromagnetic waves introduced from the outside. For example, the ground plane GL can have a grounding potential. Therefore, the ground plane GL can absorb at least a portion of the electromagnetic waves introduced from the outside. The electromagnetic waves absorbed by the ground plane GL can be converted into electrical and magnetic energy, and the intensity of the electromagnetic waves introduced from the outside can be attenuated. In some embodiments, the ground plane GL can absorb electromagnetic waves on the display panel DP and / or printed circuit board PCB (e.g., see...). Figure 2 It is a part of the electromagnetic waves formed in the atmosphere.

[0089] The grounding layer GL may include copper (Cu). However, this disclosure is not limited thereto. For example, the grounding layer GL may include at least one metal selected from a variety of suitable metallic materials or any suitable alloy including such metal, including aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), etc., or may be formed as a multilayer structure or a single layer including the respective material.

[0090] A first base layer BL1 may be disposed on a ground layer GL. The first base layer BL1 may comprise a suitable material that is flexible. For example, the first base layer BL1 may comprise polyimide (PI). However, this disclosure is not limited thereto. For example, the first base layer BL1 may comprise polyethersulfone (PES), polyarylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polycarbonate (PC), cellulose triacetate (CTA), and / or cellulose acetate propionate (CAP). Furthermore, the first base layer BL1 may comprise an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon nitride.

[0091] An adhesive layer AL can be disposed on the first base layer BL1. The adhesive layer AL can also be disposed between the first base layer BL1 and the second base layer BL2. Therefore, the adhesive layer AL allows the first base layer BL1 and the second base layer BL2 to adhere to each other.

[0092] The adhesive layer AL can be formed from a silicon layer. For example, the adhesive layer AL can include amorphous silicon, silicon oxide, silicon nitride, etc. However, this disclosure is not limited thereto.

[0093] A second base layer BL2 may be disposed on the adhesive layer AL. The second base layer BL2 may comprise a suitable material that is flexible. The second base layer BL2 may comprise the same material as the first base layer BL1 (e.g., it may be made of the same material as the first base layer BL1). For example, the second base layer BL2 may comprise polyimide.

[0094] The pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV, which are sequentially stacked on the substrate SUB along the third direction DR3.

[0095] The buffer layer (BFL) can be entirely disposed on the substrate (SUB). The buffer layer (BFL) can prevent or substantially prevent impurities from diffusing into the transistor (TR). The buffer layer (BFL) can be an inorganic insulating layer comprising inorganic materials. The buffer layer (BFL) can include silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon nitride oxide (SiO) x N y ) and aluminum oxide (AlO) x At least one of the following. The buffer layer BFL can be a single layer, but can also be a multilayer structure comprising at least two layers. When the buffer layer BFL is a multilayer structure, the layers can be formed of the same material or can be formed of different materials. The buffer layer BFL can be omitted as needed or desired, depending on the material of the substrate SUB, process conditions, etc.

[0096] The gate insulating layer GI may be entirely disposed on the buffer layer BFL. The gate insulating layer GI may comprise the same material as the buffer layer BFL, or may comprise a suitable material from (e.g., selected from) the aforementioned materials used for the buffer layer BFL. In an example, the gate insulating layer GI may be an inorganic insulating layer comprising an inorganic material.

[0097] The interlayer insulating layer (ILD) may be entirely disposed on and / or formed on the gate insulating layer (GI). The interlayer insulating layer (ILD) may comprise the same material as the gate insulating layer (GI), or may comprise a suitable material from (e.g., selected from) the aforementioned materials used for the gate insulating layer (GI).

[0098] The passivation layer PSV can be entirely disposed on and / or formed on the interlayer insulating layer (ILD). The passivation layer PSV can be an inorganic insulating layer comprising inorganic materials, or an organic insulating layer comprising organic materials. The inorganic insulating layer can include, for example, silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO) x N y ) and aluminum oxide (AlO) x At least one of the following. The organic insulating layer may include, for example, organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB) resin.

[0099] A transistor TR may include a semiconductor layer SCL, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0100] The semiconductor layer SCL can be disposed on the buffer layer BFL. The semiconductor layer SCL may include a source region and a drain region that are in contact with the source electrode SE and the drain electrode DE, respectively. The region between the source region and the drain region may be a channel region.

[0101] The semiconductor layer SCL can be a semiconductor pattern including amorphous silicon, monocrystalline silicon, polycrystalline silicon, oxide semiconductors, etc. (e.g., made of amorphous silicon, monocrystalline silicon, polycrystalline silicon, oxide semiconductors, etc.). The channel region can be an intrinsic semiconductor pattern without doping. Impurities such as n-type impurities, p-type impurities, and other suitable metals can be used as impurities. The source and drain regions can correspond to semiconductor patterns with doping.

[0102] The gate electrode GE can be located on the gate insulating layer GI. The gate electrode GE can overlap with the semiconductor layer SCL corresponding to the gate electrode GE.

[0103] The source electrode SE can be located on the interlayer insulating layer ILD, thereby contacting the source region of the semiconductor layer SCL corresponding to the source electrode SE through a contact hole penetrating the interlayer insulating layer ILD and the gate insulating layer GI. In the example, the source electrode SE of the transistor TR can contact the source region of the semiconductor layer SCL corresponding to the source electrode SE through a first contact hole CH1 penetrating the interlayer insulating layer ILD and the gate insulating layer GI.

[0104] The drain electrode DE can be located on the interlayer insulating layer ILD, thereby contacting the drain region of the semiconductor layer SCL corresponding to the drain electrode DE through a contact hole penetrating the interlayer insulating layer ILD and the gate insulating layer GI. In the example, the drain electrode DE of the transistor TR can contact the drain region of the semiconductor layer SCL corresponding to the drain electrode DE through a second contact hole CH2 penetrating the interlayer insulating layer ILD and the gate insulating layer GI.

[0105] The passivation layer PSV can completely cover the transistor TR. Therefore, the passivation layer PSV can cover the transistor TR. The passivation layer PSV may include a third contact hole CH3 that exposes a portion of the drain electrode DE.

[0106] The display element layer (DPL) can be disposed on the passivation layer (PSV). The display element layer (DPL) may include a light-emitting element (LD).

[0107] A light-emitting element (LD) may include a first electrode AE ​​and a second electrode CE, and a light-emitting layer EML disposed between the two electrodes AE and CE. Either the first electrode AE ​​or the second electrode CE may be an anode, and the other may be a cathode. For example, the first electrode AE ​​may be an anode, and the second electrode CE may be a cathode. When the light-emitting element LD is a top-emitting organic light-emitting element, the first electrode AE ​​may be a reflective electrode, and the second electrode CE may be a transmissive electrode. In this embodiment, the light-emitting element LD may be a top-emitting organic light-emitting element, and the first electrode AE ​​may be an anode.

[0108] The first electrode AE ​​can be electrically connected to the drain electrode DE through the third contact hole CH3 penetrating the passivation layer PSV. The first electrode AE ​​may include a reflective layer capable of reflecting light and a transparent conductive layer disposed on top or bottom of the reflective layer. At least one of the transparent conductive layer and the reflective layer can be electrically connected to the drain electrode DE.

[0109] The display element layer DPL may also include a pixel defining layer PDL having an opening OP that exposes a portion of the first electrode AE ​​(e.g., a portion of the top surface of the first electrode AE).

[0110] Each of the pixels PXL disposed in the display panel DP can be disposed in a pixel region included in the display area EA. In an embodiment, the pixel region may include an emitting region EMA and a non-emitting region NEMA adjacent to the emitting region EMA. The non-emitting region NEMA may surround the emitting region EMA (e.g., around the periphery of the emitting region EMA). In an embodiment, the emitting region EMA may be defined to correspond to a portion of the first electrode AE ​​exposed by the opening OP of the pixel defining layer PDL.

[0111] The Display Component Layer (DPL) may include a Hole Control Layer (HCL) and an Electron Control Layer (ECL).

[0112] The hole control layer (HCL) can be commonly disposed in the emitter region (EMA) and the non-emitter region (NEMA). Common layers such as the hole control layer (HCL) and the electronic control layer (ECL) can be commonly formed in multiple pixels (PXL).

[0113] The emissive layer EML can be disposed on the hole control layer HCL. The emissive layer EML can be disposed in the region corresponding to the opening OP. In other words, the emissive layer EML can be individually disposed in each of a plurality of pixels PXL. The emissive layer EML can include organic and / or inorganic materials. In some embodiments, the emissive layer EML can be formed by patterning. However, in some embodiments, the emissive layer EML can be commonly disposed in the pixels PXL. The color of the light generated in the emissive layer EML can be one of red, green, blue, and white. However, this disclosure is not limited thereto. For example, the color of the light generated in the emissive layer EML can be one of magenta, cyan, and yellow.

[0114] An electronic control layer (ECL) can be disposed on the emissive layer (EML). The ECL can be commonly formed in the pixel PXL and can inject and / or transfer electrons to the emissive layer EML.

[0115] The second electrode CE can be disposed on the electronic control layer ECL. The second electrode CE can also be disposed in the pixel PXL.

[0116] The encapsulation layer ENC covering the second electrode CE can be applied to the second electrode CE.

[0117] The encapsulation layer ENC can be a single layer or a multi-layer structure. The encapsulation layer ENC may include multiple insulating layers covering the light-emitting element (LD). More specifically, the encapsulation layer ENC may include at least one inorganic layer and at least one organic layer. For example, the encapsulation layer ENC may have a structure in which inorganic and organic layers are alternately stacked. In some embodiments, the encapsulation layer ENC may be an encapsulation substrate covering the light-emitting element (LD) and bonded to a substrate SUB by a sealant.

[0118] Figure 6 It is shown Figure 5 A cross-sectional view of an embodiment of the substrate shown.

[0119] refer to Figure 6 The substrate SUB may include a ground layer GL, a first base layer BL1, an adhesive layer AL, a second base layer BL2, and a barrier unit (e.g., a barrier or conductive barrier) BU. Figure 6 The grounding layer GL, the first base layer BL1, the adhesive layer AL, and the second base layer BL2 can be referenced above. Figure 5 The grounding layer GL, the first base layer BL1, the adhesive layer AL, and the second base layer BL2 are described as being the same or substantially the same. Therefore, redundant descriptions of them will not be repeated below.

[0120] The adhesive layer AL may include at least one trench TRH. For example, the adhesive layer AL may include a trench TRH that penetrates at least a portion of the adhesive layer AL.

[0121] The barrier unit BU can be disposed in the trench TRH. For example, the barrier unit BU can be disposed in the trench TRH to penetrate the adhesive layer AL. The barrier unit BU can contact the first base layer BL1 and the second base layer BL2, while penetrating the adhesive layer AL.

[0122] The barrier unit BU can be configured to overlap with the non-display area NEA. The barrier unit BU can also be configured not to overlap with the display area EA. For example, the barrier unit BU can overlap with an outer region of the substrate SUB that does not overlap with the display area EA.

[0123] The barrier unit BU can have a higher conductivity than the adhesive layer AL. For example, static electricity introduced into the adhesive layer AL can move to the barrier unit BU. In other words, the barrier unit BU can discharge static electricity introduced into the adhesive layer AL to the ground layer GL.

[0124] The barrier unit BU can be connected to the ground plane GL. For example, the barrier unit BU can be connected to the ground plane GL via a connection line ESL. The connection line ESL can be configured to overlap with the non-display area NEA. However, this disclosure is not limited thereto, and the connection line ESL can be modified in various ways as needed or desired, as long as the connection line ESL can connect the barrier unit BU and the ground plane GL to each other.

[0125] The barrier unit BU can allow the substrate SUB to maintain a constant or substantially constant potential level. For example, the barrier unit BU may include a dielectric material, and the adhesive layer AL may include amorphous silicon (e.g., it may be made of amorphous silicon) to have a relatively high dielectric constant. In some embodiments, the barrier unit BU may include at least one of ceramic, glass, and plastic. From the display device DD (e.g., see...) Figure 1 Static electricity (e.g., electromagnetic waves) generated from external sources may be introduced into the display panel DP (e.g., see [reference]). Figure 5 In the process of electrostatic discharge (ESD), the adhesive layer AL (e.g., silicon included in the adhesive layer AL) can be charged. The charged adhesive layer AL may then charge the transistor TR (e.g., see [link to relevant documentation]). Figure 5 This can affect the operation of the display panel and may reduce the reliability of the DP driver.

[0126] According to some embodiments of this disclosure, the barrier unit BU can relatively reduce the risk of static electricity being generated in the substrate SUB. For example, the barrier unit BU can be connected to a ground layer GL having a ground potential. The barrier unit BU can allow static electricity introduced into the substrate SUB to flow into the ground layer GL, and thus can improve the reliability of driving the display device DD.

[0127] Figure 7 It is shown Figure 6 A plan view of an embodiment of the adhesive layer and barrier unit shown. Figure 8 It is shown Figure 6 A plan view of an embodiment of the adhesive layer and barrier unit shown. Figure 9 It is shown Figure 6 A plan view of an embodiment of the adhesive layer and barrier unit shown.

[0128] exist Figures 7 to 9 In each of these diagrams, for ease of illustration, the adhesive layer AL and barrier unit BU of the substrate SUB are shown as viewed in the opposite direction to DR3 (e.g., in a plan view). (See, for example, [reference needed]). Figure 6 ).

[0129] refer to Figure 7 The adhesive layer AL can include the display area EA_AL and the non-display area NEA_AL. Figure 7 The display area EA_AL and the non-display area NEA_AL shown can be the same as those mentioned above. Figure 6The description refers to the regions corresponding to the display area EA and the non-display area NEA. For example, the display area EA_AL can be a region that overlaps with the display area EA on a plane (e.g., in a plan view). Similarly, the non-display area NEA_AL can be a region that overlaps with the non-display area NEA on a plane (e.g., in a plan view). The non-display area NEA_AL can be formed around the display area EA_AL (e.g., around the periphery of the display area EA_AL). For example, both the display area EA_AL and the non-display area NEA_AL can have quadrilateral shapes. However, this disclosure is not limited thereto.

[0130] The adhesive layer AL may include a trench TRH recessed in a third direction DR3. The trench TRH may be an opening recessed in the thickness direction of the adhesive layer AL and extending in one direction. For example, the trench TRH may be an opening recessed in a direction opposite to the third direction DR3 and extending in a first direction DR1 and / or a second direction DR2. The trench TRH may be formed as an opening surrounding the display area EA_AL (e.g., around the periphery of the display area EA_AL). However, this disclosure is not limited thereto. For example, four trench TRHs may be configured, and the four trench TRHs may be connected to each other to surround the display area EA_AL (e.g., around the periphery of the display area EA_AL).

[0131] A trench TRH can be set in the non-display area NEA_AL. A trench TRH does not need to overlap with the display area EA_AL, but it can be set in the non-display area NEA_AL.

[0132] The trench TRH can be configured to surround the display area EA_AL (e.g., around the periphery of the display area EA_AL). For example, the trench TRH can be configured to be located outside the display area EA_AL and can be configured to surround all edges of the display area EA_AL (e.g., around the periphery of all edges of the display area EA_AL).

[0133] The barrier unit (e.g., a barrier or conductive barrier) BU can be configured to correspond to the trench TRH. In other words, the barrier unit BU can be configured to penetrate the adhesive layer AL while overlapping with the trench TRH.

[0134] The barrier unit BU can be set in the non-display area NEA_AL. For example, the barrier unit BU does not need to overlap with the display area EA_AL, but can be set in the non-display area NEA_AL.

[0135] The barrier element BU can be connected to the ground plane GL. For example, the barrier element BU can be connected to the ground plane GL via a connection line ESL (see, for example, see...). Figure 6Therefore, the barrier unit BU can transfer static electricity introduced from the outside to the grounding layer GL.

[0136] The barrier unit BU can be configured to surround the display area EA_AL (e.g., around the periphery of the display area EA_AL). Therefore, the barrier unit BU prevents externally introduced static electricity from flowing into the display area EA_AL. In other words, the barrier unit BU can prevent or substantially prevent externally introduced static electricity from flowing into the display area EA_AL. For example, the display area EA_AL can have a quadrilateral shape. The barrier unit BU can be configured to surround the four sides of the display area EA_AL (e.g., around the periphery of the four sides of the display area EA_AL). Therefore, the barrier unit BU can reduce the risk of static electricity being introduced into the display area EA_AL.

[0137] refer to Figure 8 The adhesive layer AL' may include a trench TRH'. For example, the adhesive layer AL' may include a trench TRH' recessed in a third direction DR3. The trench TRH' may be an opening recessed in the thickness direction of the adhesive layer AL' and extending in one direction. Figure 8 The adhesive layer AL', trench TRH', and barrier unit (e.g., barrier or conductive barrier) BU' shown can be related to the above references. Figure 7 The adhesive layer AL, trench TRH, and barrier unit BU are described as being the same or substantially the same. Therefore, redundant descriptions of them will not be repeated below.

[0138] The trench TRH' can be set in the non-display area NEA_AL. The trench TRH' can have a U-shape on a plane (e.g., in a planar view). In other words, the adhesive layer AL' can include an opening with a U-shape.

[0139] The display area EA_AL can be quadrilateral in shape. The display area EA_AL can include multiple sides EA_S. For example, the display area EA_AL can include the first side EA_S1 to the fourth side EA_S4.

[0140] The first edge EA_S1 can be the display area EA_AL in the first direction DR1 of multiple edges EA_S. The second edge EA_S2 can be the display area EA_AL in the opposite direction to the first direction DR1 of multiple edges EA_S. The second edge EA_S2 can be the edge facing the first edge EA_S1 (or opposite to the first edge EA_S1). The third edge EA_S3 can be the display area EA_AL in the opposite direction to the second direction DR2 of multiple edges EA_S. The fourth edge EA_S4 can be the display area EA_AL in the second direction DR2 of multiple edges EA_S. The fourth edge EA_S4 can be the edge facing the third edge EA_S3 (or opposite to the third edge EA_S3).

[0141] The barrier unit BU' may have a shape corresponding to the trench TRH'. For example, the barrier unit BU' may have a U-shape in a plane (e.g., when viewed from above or in a plan view). The barrier unit BU' may be configured to surround the first side EA_S1 to the third side EA_S3 (e.g., around the periphery of the first side EA_S1 to the third side EA_S3). The barrier unit BU' may not surround the fourth side EA_S4 (e.g., not around the periphery of the fourth side EA_S4). The fourth side EA_S4 may be a display device DD (e.g., see...). Figure 1 The driver circuit chip DIC (for example, see...) Figure 2 The fourth side EA_S4 can be provided. Therefore, the amount of static electricity introduced from the outside via the fourth side EA_S4 can be relatively small. According to some embodiments of this disclosure, although the barrier unit BU' is provided only around the first side EA_S1 to the third side EA_S3 (e.g., only around the periphery of the first side EA_S1 to the third side EA_S3), static electricity can be effectively prevented from being introduced from the outside.

[0142] refer to Figure 9 The adhesive layer AL may include trenches TRH. For example, the adhesive layer AL may include first trenches TRH1 to third trenches TRH3. Figure 9 The adhesive layer AL", trench TRH", and barrier unit (e.g., barrier or conductive barrier) BU shown above can be used in conjunction with the above references. Figure 7 The adhesive layer AL, trench TRH, and barrier unit BU are described as being the same or substantially the same. Therefore, redundant descriptions of them will not be repeated below.

[0143] The "groove TRH" can include a first groove TRH1 to a third groove TRH3. Each of the first grooves TRH1 to the third groove TRH3 can be adjacent to any one of the edges EA_S of the display area EA. For example, the first groove TRH1 can be adjacent to the first edge EA_S1. In other words, the first groove TRH1 can be adjacent to the corner between the first edge EA_S1 and the fourth edge EA_S4. The second groove TRH2 can be adjacent to the second edge EA_S2. In other words, the second groove TRH2 can be adjacent to the corner between the second edge EA_S2 and the third edge EA_S3. The third groove TRH3 can be adjacent to the third edge EA_S3. In other words, the third groove TRH3 can be adjacent to the corner between the first edge EA_S1 and the third edge EA_S3.

[0144] The "barrier unit BU" may include first barrier units BU1 to third barrier units BU3 (e.g., first barrier or conductive barrier BU1 to third barrier or conductive barrier BU3). First barrier units BU1 to third barrier units BU3 may correspond to first trenches TRH1 to third trenches TRH3, respectively. For example, first barrier unit BU1 may overlap with first trench TRH1 to be adjacent to the corner between first side EA_S1 and fourth side EA_S4. Second barrier unit BU2 may overlap with second trench TRH2 to be adjacent to the corner between second side EA_S2 and third side EA_S3. Third barrier unit BU3 may overlap with third trench TRH3 to be adjacent to the corner between first side EA_S1 and third side EA_S3.

[0145] Each of the first barrier unit BU1 to the third barrier unit BU3 can be connected to the ground plane GL via a connecting line ESL (see, for example, see...). Figure 6 Therefore, the first barrier unit BU1 to the third barrier unit BU3 can transfer static electricity introduced from the outside to the grounding layer GL.

[0146] According to some embodiments of this disclosure, the first barrier unit BU1 to the third barrier unit BU3 can effectively block static electricity introduced from the outside while occupying a relatively small area in the display area EA_AL. For example, the corners of the display area EA_AL may be relatively susceptible to static electricity introduced from the outside. Each of the first barrier unit BU1 to the third barrier unit BU3 can be configured to be closer to the corners of the display area EA_AL. Therefore, the first barrier unit BU1 to the third barrier unit BU3 can effectively block static electricity introduced from the display panel DP (e.g., see...). Figure 4 The externally introduced static electricity is transferred to the ground plane GL, thereby improving the reliability of the display panel DP driving.

[0147] Figure 10It shows the voltage applicator and Figure 5 A cross-sectional view of an embodiment of the substrate shown. Figure 11 It is shown by Figure 10 The waveform diagram shows an embodiment of the bias voltage provided by the voltage applicator shown.

[0148] refer to Figure 10 The substrate SUB may include a ground layer GL, a first base layer BL1, an adhesive layer AL, a second base layer BL2, and a barrier unit (e.g., a barrier or conductive barrier) BU. Figure 10 The grounding layer GL, the first base layer BL1, the adhesive layer AL, and the second base layer BL2 shown can be compared with the above reference. Figure 6 The grounding layer GL, the first base layer BL1, the adhesive layer AL, and the second base layer BL2 are described as being the same or substantially the same. Therefore, redundant descriptions of them will not be repeated below.

[0149] refer to Figure 10 and Figure 11 A bias supply (e.g., a voltage applicator) VDC can provide a voltage (e.g., a predetermined voltage) to the barrier unit BU. For example, the bias supply VDC can apply a bias voltage BV.

[0150] The bias voltage BV can have a ground level voltage GND and a low level voltage VGL. For example, the bias supply VDC can apply the ground level voltage GND to the barrier cell BU. Therefore, static electricity introduced from the outside can be transferred to the ground layer GL via the barrier cell BU. Thereafter, the bias supply VDC can apply the low level voltage VGL to the barrier cell BU during the first cycle P1 (e.g., only during the first cycle P1). For example, during the first cycle P1, the static electricity introduced from the outside can be positively charged. When the amount of static charge is very large, even if the ground level voltage GND is applied to the barrier cell BU, it may not be able to block the static electricity effectively. Accordingly, the substrate SUB may be charged by static electricity, and the display device DD (e.g., see...) Figure 1 The reliability of the drive may deteriorate.

[0151] According to some embodiments of this disclosure, the bias supply VDC can apply a low-level voltage VGL to the barrier cell BU during a period when the amount of static charge introduced from the outside is very large (e.g., the first period P1). Therefore, even though the amount of static charge introduced from the outside is very large, the risk of the substrate SUB being charged by static electricity can be reduced.

[0152] In some implementations, the bias voltage BV can be related to the scan drive circuit GDC (e.g., see [link]). Figure 2The bias voltage BV is synchronized with the gate signal applied to pixel PXL by the scan drive circuit GDC. In other words, the bias voltage BV can be synchronized with the gate electrode GE of the transistor TR included in pixel PXL by the scan drive circuit GDC (see, for example, see...). Figure 5 The gate signal is synchronized. For example, when the gate signal is high, the bias voltage BV can be the ground level voltage GND. Furthermore, when the gate signal is low, the bias voltage BV can be the low level voltage VGL. However, this disclosure is not limited thereto.

[0153] Figure 12 It is shown Figure 5 A cross-sectional view of an embodiment of the substrate shown. Figure 13 It is shown Figure 5 A cross-sectional view of an embodiment of the substrate shown.

[0154] refer to Figure 12 and Figure 13 The substrate SUB may include a ground layer GL, a first base layer BL1, an adhesive layer AL, a second base layer BL2, and a barrier unit (e.g., a barrier or conductive barrier) BU. Figure 12 and Figure 13 The grounding layer GL, the first base layer BL1, the adhesive layer AL, and the second base layer BL2 shown can be compared with the above reference. Figure 6 The grounding layer GL, the first base layer BL1, the adhesive layer AL, and the second base layer BL2 are described as being the same or substantially the same. Therefore, redundant descriptions of them will not be repeated below.

[0155] The barrier unit BU can be disposed on one surface of the adhesive layer AL. For example, the barrier unit BU can be disposed on the top surface of the adhesive layer AL. In another example, the barrier unit BU can be disposed on the bottom surface of the adhesive layer AL.

[0156] The barrier cell BU can be connected to the ground plane GL. For example, the barrier cell BU can be connected to the ground plane GL having a ground potential. Therefore, the barrier cell BU can allow the substrate SUB to maintain a constant or substantially constant potential level. For example, the barrier cell BU can be disposed on one surface of the adhesive layer AL to receive at least a portion of the static electricity charged to the adhesive layer AL. Therefore, the barrier cell BU allows the received static electricity to flow into the ground plane GL and can improve the display device DD (e.g., see...). Figure 1 The reliability of the drive.

[0157] Figure 14 This is a block diagram illustrating an electronic device including a display device according to one or more embodiments of the present disclosure.

[0158] refer to Figure 14The electronic device ED may include a processor PRC, a memory device MEM, a storage device SD, an input / output (I / O) device IO, a power supply PS, and a display device 1400. The display device 1400 may be as described above. Figure 1 The described display device DD. Furthermore, the electronic device ED may also include ports capable of communicating with video cards, sound cards, memory cards, USB devices, etc., or with other systems. In one embodiment, the electronic device ED can be implemented as a smartphone. In another embodiment, the electronic device ED can be implemented as a tablet PC. However, this disclosure is not limited thereto, and the electronic device ED can be any suitable device including the display device DD. For example, the electronic device ED can be implemented as a mobile phone, video phone, smart tablet, smartwatch, vehicle navigation system, computer monitor, laptop computer, head-mounted display device, etc.

[0159] A processor PRC can perform various calculations or tasks. In some implementations, the processor PRC can be a microprocessor, a central processing unit, an application processor, etc. The processor PRC can be connected to other components via address buses, control buses, data buses, etc. In some implementations, the processor PRC can be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus. In some implementations, the processor PRC can provide input image data.

[0160] A memory device (MEM) can store data used for the operation of an electronic device (ED). For example, a memory device (MEM) may include non-volatile memory devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), or ferroelectric random access memory (FRAM) and / or volatile memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), or mobile DRAM.

[0161] Storage devices (SDs) can include solid-state drives (SSDs), hard disk drives (HDDs), CD-ROMs, etc.

[0162] I / O device 10 may include input devices or devices such as a keyboard, keypad, touchscreen, or mouse, and output devices or devices such as a speaker or printer. In some embodiments, display device 1400 may be included in I / O device 10.

[0163] The power supply PS can provide power for the operation of the electronic device ED. For example, the power supply PS can be a power management integrated circuit (PMIC). In some implementations, the power supply PS can provide a bias voltage BV (e.g., see...). Figure 11 For example, the bias supply VDC (see, for example, see...). Figure 10 () can be a component of the power supply PS. However, this disclosure is not limited thereto.

[0164] Display device 1400 can display an image corresponding to the visual information of electronic device ED. For example, display device 1400 can display an image based on an input image. Display device 1400 can be an organic light-emitting display device or a quantum dot light-emitting display device, but this disclosure is not limited thereto. Display device 1400 can be connected to other components via a bus or another communication link.

[0165] In the substrate, display panel, and electronic device according to some embodiments of the present disclosure, static electricity introduced from the outside can be stably shielded, thereby improving the reliability of the display device's driving.

[0166] The foregoing description is an example of some embodiments of this disclosure and should not be construed as limiting it. Although some embodiments have been described, those skilled in the art will readily understand that various modifications may be made to the embodiments without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those skilled in the art, unless specifically indicated otherwise, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, it should be understood that the foregoing description is an example of various exemplary embodiments and should not be construed as limiting to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined by the appended claims and their equivalents.

Claims

1. A substrate, characterized by, include: First basic layer; An adhesive layer, on the first base layer, includes at least one trench; The second base layer is on the adhesive layer; as well as Barrier, overlapping with the at least one trench, In this case, at least one groove penetrates the adhesive layer.

2. The substrate of claim 1, wherein, The barrier is located in the edge region surrounding the central region of the substrate.

3. The substrate of claim 2, wherein, The central area includes: First side; The second side is opposite to the first side; The third side connects to the first side and the second side; and The fourth side, opposite to the third side, and The barrier includes: The first barrier is adjacent to the corner between the first side and the fourth side; The second barrier is adjacent to the corner between the second side and the third side; and The third barrier is adjacent to the corner between the first side and the third side.

4. The substrate of claim 1, wherein The barrier comprises a dielectric material.

5. The substrate of claim 1, wherein The first base layer and the second base layer are flexible.

6. The substrate of claim 5, wherein, The first base layer and the second base layer comprise polyimide.

7. The substrate of claim 1, wherein The adhesive layer comprises amorphous silicon.

8. A display panel, characterized by, include: Grounding layer; The first base layer is on the grounding layer; An adhesive layer is applied to the first base layer; The second base layer is on the adhesive layer; as well as The barrier is in contact with one surface of the adhesive layer and connected to the grounding layer.

9. The display panel of claim 8, wherein, The barrier surrounds the display area and is located in a non-display area different from the display area.

10. The display panel of claim 9, wherein, The barrier is in contact with the first base layer.

11. The display panel of claim 9, wherein, The barrier is in contact with the second base layer.

12. The display panel of claim 9, wherein, The grounding layer has a grounding potential.

13. An electronic device, comprising: include: A processor used to provide input image data; as well as A display device for displaying an image based on the input image. The display device includes: Grounding layer; First basic layer; An adhesive layer is provided on the first base layer and includes at least one groove. A second base layer, on the adhesive layer; and A barrier that overlaps with the at least one trench and penetrates the adhesive layer.

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