High performance server based on multipath to strong processor platform

Abstract

The utility model discloses a high-performance server based on a multipath-to-strong processor platform, which comprises a mainboard consisting of a CPU (central processing unit), a CPU plugging unit, a system hard disk unit, an RAID (redundant array of independent disks) control unit, a gigabit network unit, a BMC (baseboard management controller) monitoring unit, a display unit, an IO (input / output) unit, a CPLD (complex programmable logic device) unit, a clock unit, a power supply unit and a hot plug unit. The CPU unit is electrically connected with the CPU plugging unit, the system hard disk unit, the RAID control unit, the gigabit network unit, the BMC monitoring unit, the display unit, the IO unit, the CPLD unit, the clock unit, the power supply unit and the hot plug unit. According to the high-performance server based on the multipath-to-strong processor platform, an FCLGA3647 socket is adopted for a mainboard, a double-path-to-strong processor is installed, a WX1860AL4 with four ports and a WX1860AL2 with two ports are connected with a CPU0 through PCIE3.0 * 4, a 5-path gigabit network is provided for the outside to bear service data, and a gigabit Ethernet interface is provided for the outside to bear management data.

Description

Technical Field

[0001] This utility model belongs to the field of computer technology, specifically relating to a high-performance server based on a multi-processor Xeon processor platform. Background Technology

[0002] With the rapid development of cloud computing, big data, and high-performance computing (HPC), data centers are placing higher demands on the performance, density, reliability, and maintainability of computing servers. Traditional server architectures have limitations in scalability, heat dissipation efficiency, and modular design, making it difficult to meet the needs of high-density deployment and flexible expansion. Blade servers, due to their high integration, modular design, and shared infrastructure (such as power supply and cooling), have become a key solution for data centers to improve computing performance and energy efficiency.

[0003] Most mainstream blade servers currently use general-purpose x86 architecture processors (such as the Intel Xeon series), which need to meet requirements such as multi-core parallel computing, high-speed interconnect, large-capacity memory, and storage redundancy. However, in existing technologies, the collaborative efficiency of multi-processor systems is insufficient: the interconnect bandwidth and latency between dual or more processors affect overall performance.

[0004] Therefore, the aforementioned problems need to be addressed. Utility Model Content

[0005] The purpose of this invention is to provide a high-performance server based on a multi-processor Xeon processor platform to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, this utility model provides the following technical solution: a high-performance server based on a multi-processor Xeon processor platform, including a motherboard, which is composed of a CPU unit, a system hard disk unit, a RAID control unit, a gigabit network unit, a BMC monitoring unit, a display unit, an I / O unit, a CPLD unit, a clock unit, a power supply unit, and a hot-swappable unit;

[0007] The CPU unit includes dual Xeon processors, which are electrically connected to each other.

[0008] The dual Xeon processors are electrically connected to the motherboard via an FCLGA3647 socket;

[0009] The CPU unit is electrically connected to the system hard disk unit, the RAID control unit, the gigabit network unit, the BMC monitoring unit, the display unit, the I / O unit, the CPLD unit, the clock unit, the power supply unit, and the hot-swappable unit.

[0010] Preferably, the CPU unit includes a dual-socket Xeon processor, a memory chip, and a PCH controller. The dual-socket Xeon processor is an Intel Xeon Gold processor and is electrically connected via two UPI interfaces.

[0011] The memory chip type is DDR4 2133MHz, and the memory chip is MT40A2G8VA-062E IT:E;

[0012] The PCH controller is an EY82C621, FCBGA1310 package;

[0013] The dual Xeon processors are electrically connected to the PCH controller. Each of the dual Xeon processors uses a 4-channel interconnect board to mount 64GB DDR4 memory chips with ECC. The memory chips are mounted in both directions and are MT40A2G8VA-062E IT:E.

[0014] Preferably, the system hard disk unit is a SATA3.0 protocol SSD with an mSATA port and is electrically connected to the PCH controller.

[0015] Preferably, the RAID control unit uses the 88RC9580 chip, which integrates an embedded ARM processor, a PCIe controller, a DDR3 controller, and a SATA controller.

[0016] The 88RC9580 chip is electrically connected to the dual-socket Xeon processor via a PCIe 2.0 x8 bus, and the 88RC9580 chip is electrically connected to the BMC controller.

[0017] Preferably, the gigabit network unit includes a WX1860AL2 chip and a WX1860AL4 chip.

[0018] Preferably, the BMC monitoring unit uses an AST2500 chip.

[0019] Preferably, the IO unit includes a USB interface and an RS232 interface, wherein the RS232 interface uses an F81804 chip.

[0020] Preferably, the hot-swap unit includes a BT9352 hot-swap circuit.

[0021] The high-performance server based on the multi-processor Xeon processor platform described above includes a chassis, and the blades are fixed in the chassis guide slots by air-cooled cold plates.

[0022] Preferably, the blade is quickly inserted and removed via a front panel ejector inside the chassis.

[0023] The technical effects and advantages of this utility model are as follows: The CPU unit adopts an Intel Xeon Gold series processor, the motherboard adopts an FCLGA3647 socket, the main frequency is 2.3GHz, 16 cores and 32 threads, the cores share 22MB of L3 instruction / data cache, the memory chip supports a maximum memory capacity of 1TB, the CPU0 brings out two PCIe 3.0 x4 ports, and a 4-port WX1860AL4 and a 2-port WX1860AL2 are used to implement 5-way Gigabit Ethernet, carrying service data and providing a Gigabit Ethernet interface to carry management data. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the principle of this utility model;

[0025] Figure 2 This is a block diagram of the RAID controller unit of this utility model;

[0026] Figure 3 This is a block diagram of the BMC unit design of this utility model;

[0027] Figure 4 This is a block diagram illustrating the principle of the IO unit of this utility model;

[0028] Figure 5 This is a power-on timing diagram of the mainboard of this utility model;

[0029] Figure 6 This is a reset topology diagram of the present invention;

[0030] Figure 7 This is a design drawing of the power rail for this utility model.

[0031] Figure 8 This is a block diagram of the hot-swap design of this utility model. Detailed Implementation

[0032] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0033] This utility model provides a high-performance server based on a multi-processor Xeon processor platform, as shown in Figure 1, including a motherboard. The motherboard consists of a CPU unit, a system hard disk unit, a RAID control unit, a gigabit network unit, a BMC monitoring unit, a display unit, an I / O unit, a CPLD unit, a clock unit, a power supply unit, and a hot-swappable unit. The CPU unit is electrically connected to the system hard disk unit, the RAID control unit, the gigabit network unit, the BMC monitoring unit, the display unit, the I / O unit, the CPLD unit, the clock unit, the power supply unit, and the hot-swappable unit.

[0034] The CPU unit uses an Intel Xeon Gold series processor, the motherboard uses an FCLGA3647 socket, the clock speed is 2.3GHz, 16 cores and 32 threads, the cores share 22MB of L3 instruction / data cache, the memory chip specifications support a maximum memory capacity of 1TB, the memory chip type is DDR4 2133MHz, the maximum memory channel is 6, and it also supports ECC memory. The processor package size is 76×56.5mm, the maximum allowable temperature (Tcase) is 87℃, and the memory type is DDR4 2133MHz. When using it, other similar dual-socket Xeon processors can be directly replaced with the current motherboard.

[0035] The main technical specifications of the dual-socket Xeon processor are as follows:

[0036] Supports Turbo Boost technology and Hyper-Threading 2.0.

[0037] Supports virtualization technology, Intel VT instruction set SSE4.2, AVX, AVX2, AVX512, 64-bit;

[0038] Supports Intel Speed ​​Shift Technology (which dynamically adjusts CPU frequency and voltage);

[0039] It features volume management device technology;

[0040] One Advanced Vector Extension 512 Unit (AVX-512FMA);

[0041] Optimization techniques for new AES instructions;

[0042] Trusted execution technology ensures the security and reliability of the system;

[0043] Pattern-based execution control (MBE).

[0044] The technical specifications achieved by the CPU unit are as follows:

[0045] It uses two Intel(R) Xeon(R) Gold CPUs, each with a clock speed of 2.3GHz and 16 cores;

[0046] Each Xeon processor has 4 channels of surface-mount DIMM memory chips, with a DIMM capacity of 64GB REG ECC DDR4 memory; the total DIMM capacity is 128GB REG ECC DDR4 memory.

[0047] The SPI FLASH is 256MB and is provided with the motherboard BIOS.

[0048] The memory chips used are 16Gb Micron Technology's Double Data Rate Synchronous Dynamic High Performance Random Access Memory (DDR4) MT40A2G8VA-062E IT:E. Each processor is configured with 64GB of ECC memory, requiring 36 memory chips. The theoretical bandwidth of 4 channels is 2133 * 64bit * 4 = 68.2GB / s. The memory chips in each channel are mounted on both sides.

[0049] The PCH controller uses Intel's EY82C621, FCBGA1310 package, and provides four 1Gb Ethernet ports, up to ten USB 3.0 ports, four USB 2.0 ports, fourteen SATA ports, and supports up to twenty PCIe 3.0 lanes. It features Quick Assist technology for accelerating computationally intensive tasks.

[0050] The specific connection relationship of the dual Xeon processors is as follows:

[0051] The dual Xeon processors (CPU0 and CPU1) are interconnected via two high-speed UPI interfaces. Intel UPI uses a chip-to-chip consistent protocol, which increases the running speed to up to 10.4GT / s.

[0052] CPU0 and PCH are interconnected via a DMI 3.0 x4 high-speed interface and a PCIe 3.0 x1 UpLink interface, enabling high-speed data engine management of the CPU's PCIe bus and memory.

[0053] CPU0 has one PCIe x8 bus connected to the RAID controller and two PCIe x4 buses connected to two Gigabit Ethernet controllers respectively.

[0054] Furthermore, the system hard disk unit adopts a SATA3.0 protocol SSD with an mSATA port and a capacity of 128G or more. The system disk is directly connected to the SATA interface of the PCH and is used to install the system. The system hard disk interface is interconnected with the PCIe 3.0 x4 bus of the PCH controller.

[0055] Please refer to the attached document. Figure 2As shown, the RAID control unit uses MARVELL's 88RC9580 chip, which has one PCIe x8 and eight 6Gbps SAS / SATA interfaces. The RAID control unit mainly provides six SATA 3.0 interfaces for the system RAID disk group. It is mainly composed of the RAID controller 88RC9580, DDR3 SDRAM (NT5CC64M16GP-DI), and SPI FLASH (GD25Q64CSIG). The 88RC9580 is interconnected through the PCIe 2.0 x8 bus of CPU0 and interconnected with the BMC controller through the I2C bus, outputting six SATA 3.0 interfaces to the VPX connector.

[0056] The technical specifications of the 88RC9580 chip are as follows:

[0057] Eight SAS / SATA ports;

[0058] Supports PCIe 2.0 x1, x2, x4, and x8 host interfaces;

[0059] Integrated embedded 800MHz Marvell 88SV581 ARM V6 CPU core for adding and unloading full RAID functionality;

[0060] Supports I2O and Marvell Universal Message Interface (UMI);

[0061] Supports three serial device bus (I2C) controllers for communicating with the hardware monitoring and management controller;

[0062] Supports two industry standard 57600 UARTs;

[0063] Supports two SGPIO ports compliant with SFF-8485;

[0064] Supports automatic detection of SAS or local SATA devices;

[0065] Up to 4096 concurrent I / O operations (2048 per 4 ports);

[0066] Up to 128 concurrent SATA devices (64 devices per 4 ports);

[0067] There is no limit to the number of devices supported;

[0068] 55nm CMOS process, 1.0V digital core voltage, 2.5V / 1.8V analog power supply, 1.5V / 1.8V DDR I / O and 3.3V I / O power supply;

[0069] Estimated power (4 ports): 8W;

[0070] Estimated power (8 ports): 9W;

[0071] Up to 42 LED / GPIO ports;

[0072] Supports hardware RAID 5 and RAID 6 acceleration;

[0073] Supports Data Path Parity Protection (DPP);

[0074] FCBGA676 package, chip size 27mm x 27mm.

[0075] The gigabit network unit uses Netcom's gigabit Ethernet controller chips WX1860AL2 and WX1860AL4, which support four-port and dual-ended gigabit Ethernet designs respectively. It has four fully integrated gigabit Ethernet media access control (MAC) and physical layer (PHY) modules and four RGMII interfaces that can be connected to external PHYs. The CPU0 brings out two PCIe 3.0 x4 ports, and a five-way gigabit network is implemented using one four-port WX1860AL4 and one two-port WX1860AL2.

[0076] The main technical specifications of the gigabit network unit are as follows:

[0077] Supports 4-port or 2-port 1GbE network interfaces;

[0078] Supports PCIe Gen2x4 host interface;

[0079] Supports 1000Base-T / 100Base-T / 10Base-T, RGMII;

[0080] Internally integrated gigabit MAC and PHY module;

[0081] Supports network protocol acceleration (TCP / UDP, IP);

[0082] Supports 8 virtual machines (SRTOV);

[0083] Supports Wake-on-LAN (WoL);

[0084] Supports sideband management protocols;

[0085] Supports Remote Network Boot Protocol (PXE);

[0086] Supports flow control;

[0087] Supports tunneling protocols;

[0088] Supports SM2 / SM3 / SM4 algorithms;

[0089] 40nm process, 2.5W power consumption;

[0090] Operating temperature: -40℃~+85℃.

[0091] For further details, please refer to the appendix. Figure 3 As shown, the BMC monitoring unit uses the AST2500 chip from the server management chip family. This is a fourth-generation high-end server management chip from Ascend Technology, designed for high-end PCIe graphics and remote management. It provides system management solutions for high-performance servers, enabling management from external remote platforms. It supports monitoring of voltage, fans, sensors, and power supplies; virtual media path resetting; and KVM functionality. The AST2500 chip integrates an 800MHz ARM11 processor and also includes controllers for PCIe 1xGen 2, eSPI, DDR4 / 3LV, and VGA, meeting the management and monitoring requirements shown in the diagram below.

[0092] The BMC monitoring and management unit is designed based on the AST2500 chip and consists of a power supply, sensors, a control processing center, and output interfaces. The LM73 is a temperature sensor that converts temperature information into I2C bus data signals. Voltage status at various levels is collected by the AST2500's internal ADC sensor. The AST2500 chip processes and analyzes the status monitoring signals collected by the I2C from various sensors and sent by CPU0 and CPU1. It determines the motherboard's operational status by monitoring temperature, voltage, current, fan speed, and CPU status. The BMC monitoring unit performs a cyclic self-test throughout operation and reports the motherboard's BIT information via the IPMI bus. The AST2500 chip can also connect to the PCH controller via LPC, USB 1.1, and USB 2.0 interfaces. The AST2500 chip integrates MCU, A / D, Gigabit Ethernet, GPU, and I / O controllers, enabling system management, iKVM, and graphics card functionality.

[0093] The technical specifications of the BMC monitoring unit are as follows:

[0094] The BMC monitors the following voltages: +12V, +5V, +3.3V, +2.5V, +1.8V, +1.5V, +1.2V, +1.0V;

[0095] BMC monitors the following current: +12V;

[0096] The BMC monitors the temperatures of the following chips: CPU, BMC, and PCH.

[0097] It has one BMC Gigabit Ethernet interface;

[0098] It has 4 fan control interfaces;

[0099] It features a dual-channel VGA interface that can be switched between front and rear, with a maximum output resolution of 1920x1200@60Hz.

[0100] Next, it can be combined with the appendix Figure 4 As shown, the IO unit is used for external USB and RS232 interfaces. The USB interfaces output from the PCH controller are 6 USB 2.0 interfaces and 3 USB 3.0 interfaces. After passing through the USB ESD and power protection circuit, they are output to the front panel 2 USB 2.0 interfaces and 2 USB 3.0 interfaces, and to the VPX connector 4 USB 2.0 interfaces and 1 USB 3.0 interface. The RS232 interface uses the SIO chip F81804. It is output through the LPC bus of the PCH and through the RS232 driver chip UM3243EEAS to output 1 RS232 interface to the VPX connector.

[0101] For further details, please refer to the appendix. Figure 5 and Figure 6 As shown, the CPLD unit is used to control the power-on timing using the EPL2210 CPLD. It communicates with the PCH via the LPC bus, RS232, I2C bus, etc., and inputs system status signals to realize control functions such as system reset timing, power control, and system indicator lights.

[0102] Please refer to the attached document. Figure 7 As shown, the power supply unit mainly performs the function of converting the +12V power input from the power board to the power of various chips on the motherboard, and provides power to the server RAID disk group and fan assembly. The clock unit serves as the chip clock source for the motherboard.

[0103] Please refer to the attached document. Figure 8 As shown, the hot-swap unit uses the domestically produced BT9352 chip, with a soft-start time of approximately 2ms, which can suppress the inrush current when the blade is powered on. The BT9352 chip uses an external N-channel MOSFET to generate a near-ideal diode. This replaces a high-power Schottky diode and its associated heatsink, saving power and board space. The ideal diode function enables low-loss power holding applications. The hot-swap unit's rapid turn-on reduces load voltage drop during power switching. A fast turn-off function minimizes reverse current if the input power supply fails or is short-circuited. The BT9352 chip operates from a 2.9V to 18V power supply. An external power supply is required at low voltages. The power path is disabled under undervoltage or overvoltage conditions. The BT9352 chip also features an open-circuit MOSFET detection circuit that issues an indication signal if the voltage drop across the MOSFET is excessive during the on-state.

[0104] Finally, it should be noted that the above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A high-performance server based on a multi-processor Xeon processor platform, characterized in that: The motherboard includes a CPU unit, a CPU connector unit, a system hard disk unit, a RAID control unit, a gigabit network unit, a BMC monitoring unit, a display unit, an I / O unit, a CPLD unit, a clock unit, a power supply unit, and a hot-swappable unit. The CPU unit is electrically connected to the CPU plug-in unit, the system hard disk unit, the RAID control unit, the gigabit network unit, the BMC monitoring unit, the display unit, the I / O unit, the CPLD unit, the clock unit, the power supply unit, and the hot-swappable unit. The CPU connector uses an FCLGA3647 socket. The CPU unit is electrically connected to the CPU connector. The CPU unit includes dual Xeon processors, which are electrically connected to each other.

2. The high-performance server based on a multi-processor Xeon processor platform according to claim 1, characterized in that: The CPU unit includes a dual-socket Xeon processor, a memory chip, and a PCH controller. The dual-socket Xeon processor is electrically connected via two UPI interfaces and is connected to the motherboard via a socket slot. The memory chip type is DDR4 2133MHz, and the memory chip uses MT40A2G8VA-062E IT:E; The PCH controller is an EY82C621, FCBGA1310 package; The dual Xeon processors are electrically connected to the PCH controller. Each of the dual Xeon processors uses a 4-channel interconnect board to mount 64GB DDR4 memory chips with ECC. The memory chips are mounted in both directions and are MT40A2G8VA-062E IT:E.

3. The high-performance server based on a multi-processor Xeon processor platform according to claim 2, characterized in that: The system hard disk unit uses a SATA3.0 protocol SSD with an mSATA port and is electrically connected to the PCH controller.

4. The high-performance server based on a multi-processor Xeon processor platform according to claim 1, characterized in that: The RAID control unit uses the 88RC9580 chip, which integrates an embedded ARM processor, PCIe controller, DDR3 controller, and SATA controller. The 88RC9580 chip is electrically connected to the dual-channel Xeon processor via a PCIe 2.0 x8 bus, and the 88RC9580 chip is electrically connected to the BMC monitoring unit.

5. The high-performance server based on a multi-processor Xeon processor platform according to claim 1, characterized in that: The gigabit network unit includes a WX1860AL2 chip and a WX1860AL4 chip.

6. The high-performance server based on a multi-processor Xeon processor platform according to claim 1, characterized in that: The BMC monitoring unit uses the AST2500 chip.

7. The high-performance server based on a multi-processor Xeon processor platform according to claim 1, characterized in that: The I / O unit includes a USB interface and an RS232 interface, and the RS232 interface uses an F81804 chip.

8. The high-performance server based on a multi-processor Xeon processor platform according to claim 1, characterized in that: The hot-swap unit includes a BT9352 hot-swap circuit.

9. The high-performance server based on a multi-processor Xeon processor platform according to any one of claims 1-8, characterized in that: Including the chassis, the blades are fixed in the chassis guide slots by air-cooled plates.

10. The high-performance server based on a multi-processor Xeon processor platform according to claim 9, characterized in that: The blade is quickly inserted and removed via a front panel ejector inside the chassis.

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