Display device

Abstract

A display device is disclosed. The display device includes: an insulating layer in which a first groove and a second groove surrounding the first groove are defined; a pixel defining layer disposed on the insulating layer, and in which a light emitting opening, a first separation opening overlapping the first groove, and a second separation opening overlapping the second groove and surrounding the first separation opening are defined; a light-emitting element including a first electrode, a second electrode, and a light-emitting layer, at least a portion of the first electrode being exposed through the light-emitting opening, the light-emitting layer overlapping the light-emitting opening; at least one part of the spacer is arranged in the first groove and the first separation opening; an inorganic encapsulation film disposed on the second electrode and the spacer; and a color filter layer disposed on the inorganic encapsulation film. Therefore, embodiments of the present disclosure provide a display device having improved display quality.

Description

[0001] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0050991, filed on April 16, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The embodiments of this disclosure described herein relate to a display device with improved display quality. Background Technology

[0003] Display devices provide information to users by displaying various images on a display screen. Typically, display devices display information within a defined screen area. A display device may include a display panel, an anti-reflective layer, and a window. Utility Model Content

[0004] Embodiments of this disclosure provide a display device with improved display quality.

[0005] According to an embodiment, the display device includes: an insulating layer, in which a first groove and a second groove surrounding the first groove are defined; a pixel defining layer disposed on the insulating layer, and in which a light-emitting opening, a first partition opening superimposed on the first groove, and a second partition opening superimposed on the second groove and surrounding the first partition opening are defined; a light-emitting element disposed on the insulating layer and including a first electrode, a second electrode, and a light-emitting layer, wherein at least a portion of the first electrode is exposed through the light-emitting opening, the second electrode is disposed on the first electrode, and the light-emitting layer is disposed between the first electrode and the second electrode and superimposed on the light-emitting opening; a spacer, at least a portion of which is disposed inside the first groove and the first partition opening; an inorganic encapsulation film disposed on the second electrode and the spacer; and a color filter layer disposed directly on the inorganic encapsulation film.

[0006] The first tip of the pixel defining layer may protrude from the first inner surface of the insulating layer defining the first groove in a direction toward the center of the first groove.

[0007] The spacer can contact the first tip.

[0008] The spacer may include a first portion disposed inside the first groove and the first dividing opening, and a second portion extending from the first portion and protruding in a direction away from the first dividing opening.

[0009] The second tip of the pixel defining layer can protrude from the second inner surface of the insulating layer defining the second groove in a direction away from the center of the first groove, and the third tip of the pixel defining layer can protrude from the third inner surface of the insulating layer in a direction toward the center of the first groove, the third inner surface facing and surrounding the second inner surface and defining the second groove.

[0010] The inorganic encapsulation film can contact the inner surface of the defined second separation opening of the pixel defining layer.

[0011] The display device may also include a dummy pattern disposed in a second groove, separated from the second electrode, and made of the same material as the second electrode.

[0012] The light-emitting element can be configured as multiple light-emitting elements, and the multiple light-emitting elements can include a first light-emitting element, a second light-emitting element, and a third light-emitting element. A first light-emitting region emitting light of a first color is defined in the first light-emitting element, a second light-emitting region emitting light of a second color different from the first color is defined in the second light-emitting element, and a third light-emitting region emitting light of a third color different from the first color and the second color is defined in the third light-emitting element. The light-emitting opening can be configured as multiple light-emitting openings, and the multiple light-emitting openings can include a first light-emitting opening superimposed on the first light-emitting region, a second light-emitting opening superimposed on the second light-emitting region, and a third light-emitting opening superimposed on the third light-emitting region. The color filter layer can include a first color filter, a second color filter, and a third color filter. At least a portion of the first color filter is superimposed on the first light-emitting region, at least a portion of the second color filter is superimposed on the second light-emitting region, and at least a portion of the third color filter is superimposed on the third light-emitting region.

[0013] At least a portion of the first to third color filters may be superimposed on each other in an area that does not overlap with any of the first to third light-emitting regions.

[0014] The portions of the first to third color filters can be arranged inside the second groove and the second dividing opening.

[0015] The display device may also include an outer coating that covers the color filter layer.

[0016] The display device may also include an input sensor layer disposed on the color filter layer.

[0017] The input sensor layer may include: a first sensing insulating layer disposed on the color filter layer; a second sensing insulating layer disposed on the first sensing insulating layer; a third sensing insulating layer disposed on the second sensing insulating layer; a first conductive layer disposed between the first sensing insulating layer and the second sensing insulating layer; a second conductive layer disposed between the second sensing insulating layer and the third sensing insulating layer; and a light-shielding layer disposed between the second sensing insulating layer and the third sensing insulating layer and covering the second conductive layer.

[0018] The display device may further include a sacrificial pattern disposed between the first electrode and the pixel defining layer, and a sacrificial opening superimposed on the light-emitting opening is defined in the sacrificial pattern.

[0019] Inorganic encapsulation films can include multiple layers.

[0020] The third groove surrounding the second groove may be further defined in an insulating layer, and the third partition opening, which overlaps with the third groove and surrounds the second partition opening, may be further defined in a pixel defining layer.

[0021] The fourth tip of the pixel defining layer can protrude from the fourth inner surface of the insulating layer defining the third groove in a direction away from the center of the first groove, and the fifth tip of the pixel defining layer can protrude from the fifth inner surface of the insulating layer in a direction toward the center of the first groove, the fifth inner surface facing and surrounding the fourth inner surface and defining the third groove.

[0022] The display device may further include: a first intermediate insulating layer disposed between the insulating layer and the pixel defining layer, wherein a first-1 lower opening superimposed with the first groove and a first-2 lower opening superimposed with the second groove are defined in the first intermediate insulating layer; and a second intermediate insulating layer disposed between the first intermediate insulating layer and the pixel defining layer, wherein a second-1 lower opening superimposed with the first-1 lower opening and a second-2 lower opening superimposed with the first-2 lower opening are defined in the second intermediate insulating layer, wherein the inner surface of the second intermediate insulating layer defining the second-1 lower opening may be recessed compared to the first intermediate insulating layer and the pixel defining layer, and the inner surface of the second intermediate insulating layer defining the second-2 lower opening may be recessed compared to the first intermediate insulating layer and the pixel defining layer.

[0023] According to an embodiment, the display device includes: an insulating layer, a first groove and a second groove surrounding the first groove defined in the insulating layer; a pixel defining layer disposed on the insulating layer and including a first tip protruding from the inner edge of the insulating layer defining the first groove and a second tip and a third tip protruding from the inner edge of the insulating layer defining the second groove; a light-emitting element disposed on the insulating layer; a spacer, at least a portion of which is disposed inside the first groove; an inorganic encapsulation film disposed on the second electrode and the spacer; and a color filter layer disposed directly on the inorganic encapsulation film.

[0024] The inorganic encapsulation film can contact the second and third tips. Attached Figure Description

[0025] The above and other aspects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0026] Figure 1 This is a perspective view of a display device according to an embodiment of the present disclosure.

[0027] Figure 2 This is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure.

[0028] Figure 3 This is an enlarged plan view showing a portion of the display layer according to an embodiment of the present disclosure.

[0029] Figure 4 This is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0030] Figure 5 This is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0031] Figure 6A This is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0032] Figure 6B This is an enlarged plan view showing some components of a display panel according to an embodiment of the present disclosure.

[0033] Figure 6C It shows Figure 6A An enlarged sectional view of region AA'.

[0034] Figure 6D It shows Figure 6A An enlarged sectional view of region BB'.

[0035] Figure 7 This is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0036] Figure 8A This is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0037] Figure 8B This is an enlarged plan view showing a portion of the construction of a display panel according to an embodiment of the present disclosure.

[0038] Figure 9 This is an enlarged cross-sectional view showing a portion of a display panel according to an embodiment of the present disclosure.

[0039] Figures 10A to 10G This is a cross-sectional view illustrating some of the operations of a method for manufacturing a display panel according to an embodiment of the present disclosure. Detailed Implementation

[0040] In the specification, the description that the first component (or area, layer, part, section, etc.) is "set on" the second component, "connected to" the second component, or "attached to" the second component means that the first component is directly set on the second component / directly connected to the second component / directly attached to the second component, or means that the third component is placed between the first component and the second component.

[0041] The same reference numerals refer to the same components. Furthermore, in the accompanying drawings, the thickness, scale, and dimensions of the components are exaggerated for the sake of effective description of the technical content. The term "and / or" includes all combinations of one or more components that can be defined by the relevant components.

[0042] While terms such as "first," "second," etc., can be used to describe various components, components should not be limited by the terms. Terms are used only to distinguish one component from another. For example, without departing from the appropriate scope of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless explicitly stated in the context, singular expressions include plural expressions.

[0043] Furthermore, the terms "below," "under," "on," and "above" are used to describe the relevance of the components shown in the accompanying drawings. Conceptually relative terms are described based on the orientation shown in the accompanying drawings.

[0044] It will be understood that the terms “comprising,” “including,” “having,” etc., indicate the presence of the features, quantities, steps, operations, elements or components or combinations thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements or components or combinations thereof.

[0045] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an overly idealized or formalized sense unless expressly defined herein.

[0046] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0047] Figure 1 This is a perspective view of a display device DD according to an embodiment of the present disclosure.

[0048] In this embodiment, the display device DD can be a large electronic device such as a television, monitor, or billboard. Alternatively, the display device DD can be a small to medium-sized electronic device such as a personal computer (“PC”), laptop computer, personal digital terminal, vehicle navigation unit, game console, smartphone, tablet PC, and camera. However, this is exemplary, and the display device DD can be used with other electronic devices, provided that the display device does not depart from the concept of this disclosure.

[0049] Reference Figure 1The display device DD can display an image on a third direction DR3 on a display surface DP-IS parallel to the first direction DR1 and the second direction DR2. The image can include still images and moving images. The display surface DP-IS on which the image is displayed can correspond to the front surface of the display device DD.

[0050] In the embodiments, a front (or upper) surface and a rear (or lower) surface of each component are defined relative to the direction along which the displayed image is viewed. The front and rear surfaces may face each other on a third direction DR3, and the normal direction of each of the front and rear surfaces may be parallel to the third direction DR3. Meanwhile, the directions indicated from the first direction to the third directions DR1, DR2, and DR3 are relative concepts and may be changed to other directions. In the specification, the phrase "in a plane" (in other words, "in a plan view") may refer to the state when viewed in the third direction DR3 (i.e., the thickness direction of the display device DD).

[0051] The display device DD may include a display area DA and a non-display area NDA. Pixels PX are arranged in the display area DA, and pixels PX are not arranged in the non-display area NDA. The non-display area NDA is defined along the edge of the display surface DP-IS. The non-display area NDA may surround the display area DA in a plan view. However, this is exemplary, and the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the non-display area NDA may be omitted or may only be provided on one side of the display area DA. Furthermore, Figure 1 An example of a flat display device DD is shown, but the display device DD may have a curved shape.

[0052] Figure 2 This is a schematic cross-sectional view of a display device DD according to an embodiment of the present disclosure.

[0053] Reference Figure 2 The display device DD may include a display panel DP and a window WM. The display panel DP may include a display layer DPL, an anti-reflective layer ARL, and an input sensor layer ISL.

[0054] The display layer (DPL) can be a light-emitting display layer. For example, the display layer (DPL) can be an organic light-emitting display layer, an inorganic light-emitting display layer, an organic-inorganic light-emitting display layer, a micro light-emitting diode (“LED”) display layer, or a nano LED display layer.

[0055] An anti-reflective layer (ARL) can be applied to the display layer (DPL). The ARL reduces the reflectivity of external light.

[0056] The anti-reflective layer ARL can be applied to the display layer DPL via a continuous process. In this case, the anti-reflective layer ARL can be directly applied to the display layer DPL. The phrase "component 'B' is directly applied to component 'A'" in the specification can mean that no third component is placed between component 'A' and component 'B'. For example, no adhesive layer may be required between the anti-reflective layer ARL and the display layer DPL.

[0057] The anti-reflective layer ARL may include a color filter layer CF, which will be described below (see Figure 5 The color filter layer CF can include multiple color filters CF1, CF2, and CF3 (see...). Figure 5 A detailed description of the anti-reflective layer (ARL) will follow.

[0058] The input sensor layer (ISL) can be disposed on the anti-reflective layer (ARL). The input sensor layer (ISL) can sense external input applied from external units. External input can be user input. User input can include various types of external input such as a part of the user's body, light, heat, pen, and pressure.

[0059] The input sensor layer (ISL) can be formed on the anti-reflective layer (ARL) using a continuous process. In this case, the input sensor layer (ISL) can be directly disposed on the anti-reflective layer (ARL).

[0060] The window WM can be disposed on the input sensor layer ISL. The window WM and the input sensor layer ISL can be bonded to each other by an adhesive layer. The adhesive layer can be a pressure-sensitive adhesive (“PSA”) film or an optically transparent adhesive (“OCA”) component.

[0061] Window WM includes at least one substrate layer 110 (see Figure 4 The substrate layer 110 can be a glass substrate or a synthetic resin film. The window WM can have a multilayer structure. The window WM can include a thin-film glass substrate and a synthetic resin film disposed on the thin-film glass substrate. The thin-film glass substrate and the synthetic resin film can be bonded to each other by an adhesive layer, and the adhesive layer and the synthetic resin film can be separated from the thin-film glass substrate for the purpose of replacing the thin-film glass substrate.

[0062] In embodiments of this disclosure, the adhesive layer may be omitted, and the window WM may be directly disposed on the input sensor layer ISL. Organic, inorganic, or ceramic materials may be coated onto the input sensor layer ISL.

[0063] Figure 3 This is an enlarged plan view showing a portion of the display layer DPL according to an embodiment of the present disclosure.

[0064] Reference Figure 3The display layer (DPL) may include multiple pixels PXr, PXg, and PXb. Pixels PXr, PXg, and PXb may include a first pixel PXr, a second pixel PXg, and a third pixel PXb.

[0065] The first light-emitting region LA1 can be confined in the first pixel PXr, the second light-emitting region LA2 can be confined in the second pixel PXg, and the third light-emitting region LA3 can be confined in the third pixel PXb. Figure 3 The circular shapes shown can correspond to the shapes of the first to third light-emitting areas LA1, LA2, and LA3, respectively. However, the shapes of the first to third light-emitting areas LA1, LA2, and LA3 are not limited to this. For example, the first to third light-emitting areas LA1, LA2, and LA3 can have various shapes on a plane, such as quadrilaterals, polygons, ellipses, triangles, or irregular shapes.

[0066] In embodiments of this disclosure, the first pixel PXr and the third pixel PXb can be arranged alternately and repeatedly in the first direction DR1 and the second direction DR2. The second pixel PXg can be disposed in the space between two first pixels PXr adjacent to each other along the diagonal direction and two third pixels PXb adjacent to each other along the diagonal direction. However, as Figure 3 The arrangement of the first to third pixels PXr, PXg, and PXb shown is an example, and the arrangement is not particularly limited to this. The direction of the diagonal line can be between the first direction DR1 and the second direction DR2, or between the direction opposite to the first direction DR1 and the second direction DR2.

[0067] In embodiments of this disclosure, the area of ​​the third light-emitting region LA3 may be the largest, and the area of ​​the second light-emitting region LA2 may be the smallest. However, this disclosure is not particularly limited thereto. For example, the areas of the first to third light-emitting regions LA1, LA2, and LA3 may be the same or may differ from the example shown.

[0068] Figure 4 This is a cross-sectional view of a display panel DP according to an embodiment of the present disclosure.

[0069] Figure 4 A cross-section corresponding to a light-emitting region LA and a non-light-emitting region NLA surrounding the light-emitting region LA in a plan view is shown, and a pixel disposed in a light-emitting region LA is shown by way of example. Figure 4 The pixel shown can be compared with the one referenced above. Figure 3The first to third pixels PXr, PXg, and PXb described herein correspond to any one of them. A pixel may include a light-emitting element ED and a driving circuit for the pixel electrically connected to the light-emitting element ED. Figure 4 A light-emitting element (ED) and a transistor TFT connected to the ED are shown. The transistor TFT may be one of a plurality of transistor TFTs included in the driving circuitry of a pixel. In an embodiment, the transistor TFT may be described as a silicon transistor, but may be a metal-oxide-semiconductor transistor.

[0070] Reference Figure 4 The display panel DP may include a display layer DPL, an anti-reflective layer ARL, and an input sensor layer ISL. The display layer DPL may include a substrate layer 110, a circuit layer 120, a light-emitting element layer 130, and an inorganic encapsulation film 141.

[0071] The substrate layer 110 can provide a substrate surface on which the circuit layer 120 is disposed. The substrate layer 110 can be a rigid substrate or a flexible substrate that can be bent, folded, and rolled. The substrate layer 110 can be a glass substrate, a metal substrate, a polymer substrate, etc. However, the embodiments of this disclosure are not limited thereto. In another embodiment, the substrate layer 110 may include an inorganic layer, an organic layer, or a composite material layer.

[0072] The substrate layer 110 may have a multilayer structure. For example, the substrate layer 110 may include a first synthetic resin layer, multiple or single inorganic layers, and a second synthetic resin layer disposed on the multiple or single inorganic layers. Each of the first and second synthetic resin layers may include a polyimide resin, but this disclosure is not particularly limited thereto.

[0073] The circuit layer 120 may be disposed on the substrate layer 110. The circuit layer 120 may include an insulating layer, a semiconductor pattern, a conductive pattern, signal lines, and driving circuitry for pixels. For example, the circuit layer 120 may include a buffer layer 10br, first to sixth insulating layers 10, 20, 30, 40, 50, and 60, a signal transmission region SCL, and multiple connection electrodes CNE1 and CNE2.

[0074] A buffer layer 10br may be disposed on the substrate layer 110. The buffer layer 10br prevents metal atoms or impurities from diffusing from the substrate layer 110 to the semiconductor pattern thereon. The semiconductor pattern includes the active region AC1 of the transistor TFT. A back metal layer may be additionally disposed between the substrate layer 110 and the buffer layer 10br. The back metal layer may be disposed below the transistor TFT and prevents external light from reaching the transistor TFT.

[0075] Semiconductor patterns can be disposed on the buffer layer 10br. The semiconductor patterns may include silicon semiconductors. For example, the silicon semiconductor may include amorphous silicon and / or polycrystalline silicon, etc. For example, the semiconductor patterns may include low-temperature polycrystalline silicon.

[0076] The semiconductor pattern may include a first region with higher conductivity and a second region with lower conductivity. The first region may be doped with either N-type or P-type dopant. A P-type transistor TFT may include a doped region doped with P-type dopant, and an N-type transistor TFT may include a doped region doped with N-type dopant. The second region may be an undoped region, or it may be a region doped at a lower concentration than the first region.

[0077] The conductivity of the first region is greater than that of the second region, and the first region can be essentially used as an electrode or signal line. The second region can essentially correspond to the active region AC1 (or channel) of the transistor TFT. In other words, a portion of the semiconductor pattern can be the active region AC1 of the transistor TFT, another portion of the semiconductor pattern can be the source or drain of the transistor TFT, and yet another portion of the semiconductor pattern can be a connecting electrode or a connecting signal line.

[0078] A transistor TFT may include a source region SE1 (or source electrode), an active region AC1 (or channel), a drain region DE1 (or drain electrode), and a gate GT1. The source region SE1, active region AC1, and drain region DE1 of the transistor TFT may be formed by a semiconductor pattern. The source region SE1 and drain region DE1 may extend from the active region AC1 in opposite directions in a cross-sectional view. Figure 4 A portion of the signal transmission region SCL, formed by a semiconductor pattern, is shown. Although not shown separately, the signal transmission region SCL can be connected in a plane (i.e., in a planar view) to the drain region DE1 of the transistor TFT.

[0079] The first insulating layer 10 can be disposed on the buffer layer 10br. The first insulating layer 10 can cover the source region SE1, active region AC1, and drain region DE1 of the transistor TFT disposed on the buffer layer 10br, as well as the signal transmission region SCL disposed on the buffer layer 10br.

[0080] The first insulating layer 10 may include an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. The insulating layers of the first insulating layer 10 and the circuit layer 120, as described below, may be inorganic and / or organic layers, and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the materials described above, but this disclosure is not limited thereto.

[0081] The gate GT1 of the transistor TFT can be disposed on the first insulating layer 10. The gate GT1 can be part of a metal pattern. The gate GT1 can be stacked with the active region AC1. The gate GT1 can be used as a mask in a process of doping the semiconductor pattern. The gate GT1 can include titanium (Ti), silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (“AlN”), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (“ITO”), indium zinc oxide (“IZO”), etc., but this disclosure is not particularly limited thereto.

[0082] The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate GT1. The third insulating layer 30 may be disposed on the second insulating layer 20.

[0083] The first connecting electrode CNE1 can be disposed on the third insulating layer 30. The first connecting electrode CNE1 can be connected to the signal transmission area SCL through a contact hole CNT-1 passing through the first insulating layer to the third insulating layers 10, 20 and 30. A fourth insulating layer 40 can be disposed on the third insulating layer 30 to cover the first connecting electrode CNE1. The fourth insulating layer 40 can be an organic layer.

[0084] The fifth insulating layer 50 can be disposed on the fourth insulating layer 40. The second connecting electrode CNE2 can be disposed on the fifth insulating layer 50. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through the contact hole CNT-2 passing through the fourth insulating layer 40 and the fifth insulating layer 50. The fifth insulating layer 50 can be an organic layer.

[0085] A sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover the second connecting electrode CNE2. The sixth insulating layer 60 may be an organic layer. The stacked structure of the first to sixth insulating layers 10, 20, 30, 40, 50 and 60 is merely an example. In addition to the first to sixth insulating layers 10, 20, 30, 40, 50 and 60, additional conductive layers and additional insulating layers may also be disposed.

[0086] The light-emitting element layer 130 may be disposed on the circuit layer 120. The light-emitting element layer 130 may include a light-emitting element ED and a pixel defining layer PDL.

[0087] The light-emitting element (ED) can include organic light-emitting elements, inorganic light-emitting elements, organic-inorganic light-emitting elements, quantum dot light-emitting elements, micro LED light-emitting elements, or nano LED light-emitting elements. However, the embodiments are not limited to these, and the light-emitting element (ED) can include various embodiments, as long as it can generate light according to an electrical signal or control the amount of light.

[0088] The light-emitting element (ED) may include a first electrode AE ​​(or anode), a light-emitting layer EML, and a second electrode CE (or cathode). The second electrode CE may be disposed on the first electrode AE, and the light-emitting layer EML may be disposed between the first electrode AE ​​and the second electrode CE. The first electrode AE ​​may be disposed on a sixth insulating layer 60. The first electrode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The first electrode AE ​​may include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or compounds thereof, and a transparent or semi-transparent electrode layer disposed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (“IGZO”), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (“AZO”). For example, the first electrode AE ​​may include an ITO / Ag / ITO stacked structure.

[0089] According to embodiments of this disclosure, the display panel DP may further include a sacrificial pattern SP. The sacrificial pattern SP may be disposed between the first electrode AE ​​and the pixel defining layer PDL. A sacrificial opening S-OP may be defined in the sacrificial pattern SP, through which a portion of the upper surface of the first electrode AE ​​is exposed. The sacrificial pattern SP may include an amorphous transparent conductive oxide.

[0090] A pixel defining layer (PDL) may be disposed on a sixth insulating layer 60. The PDL may cover a portion of the first electrode AE. For example, a light-emitting opening (PDL-OP) may be defined within the PDL, through which a portion of the first electrode AE ​​is exposed. The PDL-OP may define a light-emitting region LA. That is, the light-emitting region LA may be defined to correspond to the portion of the first electrode AE ​​exposed from the PDL through the PDL-OP.

[0091] The light-emitting aperture PDL-OP can be superimposed on the sacrificial aperture S-OP of the sacrificial pattern SP in a planar view. According to an embodiment, the upper surface of the first electrode AE ​​can be separated from the pixel defining layer PDL in a cross-sectional view and the sacrificial pattern SP is placed between the upper surface of the first electrode AE ​​and the pixel defining layer PDL. Therefore, damage to the first electrode AE ​​can be prevented during the process of forming the light-emitting aperture PDL-OP.

[0092] Figure 4The illustration schematically shows that the areas of the sacrificial opening S-OP and the light-emitting opening PDL-OP are substantially the same. However, the embodiment is not limited to this; the area of ​​the light-emitting opening PDL-OP may be smaller than the area of ​​the sacrificial opening S-OP, and the inner surface of the pixel defining layer PDL defining the light-emitting opening PDL-OP may be closer to the center of the first electrode AE ​​than the inner surface of the sacrificial pattern SP defining the sacrificial opening S-OP. In another embodiment of this disclosure, the sacrificial pattern SP may be omitted.

[0093] The pixel-defining layer (PDL) may include an inorganic insulating material. For example, the pixel-defining layer (PDL) may include silicon nitride (SiN). x ).

[0094] According to an embodiment, the pixel-defining layer (PDL) may have light-absorbing properties; for example, the PDL may be black. The PDL may include a black colorant. The black colorant may include black dyes and black pigments. The black colorant may include carbon black, metals such as chromium, or oxides thereof. The PDL may correspond to a light-shielding pattern with light-shielding properties.

[0095] A hole control layer may be further disposed between the first electrode AE ​​and the light-emitting layer EML. The hole control layer may further include a hole transport layer and / or a hole injection layer. An electron control layer may be further disposed between the light-emitting layer EML and the second electrode CE. The electron control layer may further include an electron transport layer and / or an electron injection layer.

[0096] Although not shown, in embodiments of this disclosure, the light-emitting element layer 130 may further include a capping layer. The capping layer may be disposed on the light-emitting element ED and cover the second electrode CE of the light-emitting element ED. The capping layer may comprise an organic material. The capping layer may be formed as a single layer or multiple layers. The capping layer can adequately protect the underlying negative electrode and organic light-emitting layer from moisture penetration or external contamination, thus providing a light-emitting element ED with improved lifetime.

[0097] An inorganic encapsulation film 141 can be disposed on the light-emitting element layer 130. The inorganic encapsulation film 141 protects the light-emitting element layer 130 from foreign matter such as moisture, oxygen, and dust particles. The inorganic encapsulation film 141 can have a single-layer structure or a multilayer structure in which multiple layers are stacked on a third-direction DR3. In other words, the inorganic encapsulation film 141 can be formed as a single-layer inorganic film or can have a structure in which multiple layers of inorganic films are stacked. The inorganic encapsulation film 141 protects the light-emitting element layer 130 from moisture and oxygen. The inorganic encapsulation film 141 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc.

[0098] An anti-reflective layer (ARL) can be disposed on the display layer (DPL). In an embodiment, an organic film can be disposed therein to protect the light-emitting element layer 130 from foreign matter penetrating the ARL and to provide a flat surface to the input sensor layer (ISL). This will be described in detail below.

[0099] The input sensor layer (ISL) can be disposed on the anti-reflective layer (ARL). The input sensor layer (ISL) can be referred to as a sensor layer, input sensing layer, or input sensing panel. The input sensor layer (ISL) may include a first sensing insulating layer 200-IL1, a first conductive layer 200-CL1, a second sensing insulating layer 200-IL2, a second conductive layer 200-CL2, and a third sensing insulating layer 200-IL3.

[0100] The first sensing insulating layer 200-IL1 can be directly disposed on the display layer DPL. The first sensing insulating layer 200-IL1 can be an inorganic layer comprising at least one of silicon nitride, silicon oxynitride, and silicon oxide. Optionally, the first sensing insulating layer 200-IL1 can be an organic layer comprising an epoxy resin, an acrylic resin, or an imide resin. The first sensing insulating layer 200-IL1 can have a single-layer structure or a multilayer structure in which multiple layers are stacked on a third-direction DR3.

[0101] Each of the first conductive layer 200-CL1 and the second conductive layer 200-CL2 may have a single-layer structure or a multilayer structure in which multiple layers are stacked on a third-direction DR3. Each of the first conductive layer 200-CL1 and the second conductive layer 200-CL2 may include a mesh sensing pattern or a bridging pattern.

[0102] The conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium zinc tin oxide (IZTO). Alternatively, the transparent conductive layer may include conductive polymers such as poly(3,4-ethylenedioxythiophene) (“PEDOT”), metal nanowires, graphene, etc.

[0103] A conductive layer with a multilayer structure may include a metal layer. The metal layer may have a three-layer structure, such as titanium / aluminum / titanium. A conductive layer with a multilayer structure may include at least one metal layer and at least one transparent conductive layer.

[0104] The second sensing insulating layer 200-IL2 can be disposed between the first conductive layer 200-CL1 and the second conductive layer 200-CL2. The third sensing insulating layer 200-IL3 can be disposed on the second sensing insulating layer 200-IL2 and cover the second conductive layer 200-CL2. The third sensing insulating layer 200-IL3 can reduce or eliminate the probability that the second conductive layer 200-CL2 will be damaged in subsequent processes. In embodiments of this disclosure, the input sensor layer ISL may not include the third sensing insulating layer 200-IL3.

[0105] The second sensing insulating layer 200-IL2 and the third sensing insulating layer 200-IL3 may include inorganic layers. The inorganic layers may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0106] Optionally, the second sensing insulating layer 200-IL2 and the third sensing insulating layer 200-IL3 may include at least one of epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin and perylene resin.

[0107] The input sensor layer ISL according to embodiments of the present disclosure may further include a light-shielding layer 200-SDL. The light-shielding layer 200-SDL may be disposed between the second sensing insulating layer 200-IL2 and the third sensing insulating layer 200-IL3 and cover the second conductive layer 200-CL2. For example, the light-shielding layer 200-SDL may cover all upper and side surfaces of the sensing pattern and / or bridging pattern included in the second conductive layer 200-CL2.

[0108] The light-shielding layer 200-SDL may have a black color pattern. In this embodiment, the light-shielding layer 200-SDL may include a black colorant. The black colorant may include black dyes and black pigments. The black colorant may include carbon black, metals such as chromium, or oxides thereof. However, this is exemplary, and there are no particular limitations on the materials constituting the light-shielding layer 200-SDL, as long as the material absorbs light.

[0109] Figure 5 This is a cross-sectional view of a display panel DP according to an embodiment of the present disclosure.

[0110] exist Figure 5 The description will refer to Figure 4 The description will be provided, and descriptions for the same figure references will be omitted. Figure 5 The description of each of the first to third light-emitting elements ED1, ED2, and ED3 can be compared with... Figure 4 The descriptions of light-emitting elements (EDs) are basically the same.

[0111] Reference Figure 5 The display panel DP may include a sixth insulating layer 60, a light-emitting element layer 130, an inorganic encapsulation film 141, and an input sensor layer ISL. Figure 5 For ease of description, circuit layers 120, except for the sixth insulating layer 60, are omitted (see...). Figure 4 ) and matrix layer 110 (see Figure 4 In other words, Figure 5 Only the circuit layer 120 is shown (see Figure 4 The uppermost insulating layer (i.e., the sixth insulating layer 60).

[0112] A light-emitting element ED can be configured as multiple light-emitting elements ED. These multiple light-emitting elements ED may include a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3. A first light-emitting region LA1 emitting light of a first color can be defined within the first light-emitting element ED1. A second light-emitting region LA2 emitting light of a second color different from the first color can be defined within the second light-emitting element ED2. A third light-emitting region LA3 emitting light of a third color different from both the first and second colors can be defined within the third light-emitting element ED3. The first light-emitting element ED1 can be associated with the elements included above. Figure 3 The first pixel PXr corresponds to the light-emitting element ED, and the second light-emitting element ED2 can be included with the reference above. Figure 3 The second pixel PXg described corresponds to the light-emitting element ED, and the third light-emitting element ED3 can be included with the reference above. Figure 3 The description corresponds to the light-emitting element ED in the third pixel PXb.

[0113] The first light-emitting element ED1 may include a first electrode AE, a first light-emitting layer EML1, and a second electrode CE. The second light-emitting element ED2 may include a first electrode AE, a second light-emitting layer EML2, and a second electrode CE. The third light-emitting element ED3 may include a first electrode AE, a third light-emitting layer EML3, and a second electrode CE.

[0114] In an embodiment, the first electrode AE ​​of the first light-emitting element to the third light-emitting elements ED1, ED2 and ED3 can be configured with multiple patterns.

[0115] The light-emitting aperture PDL-OP can be defined within the pixel definition layer PDL. Multiple light-emitting aperture PDL-OPs can be configured. These multiple light-emitting aperture PDL-OPs may include a first light-emitting aperture PDL-OP1 superimposed on (or defining) a first light-emitting region LA1, a second light-emitting aperture PDL-OP2 superimposed on (or defining) a second light-emitting region LA2, and a third light-emitting aperture PDL-OP3 superimposed on (or defining) a third light-emitting region LA3. The first light-emitting aperture PDL-OP1 can expose at least a portion of the first electrode AE ​​of the first light-emitting element ED1. The second light-emitting aperture PDL-OP2 can expose at least a portion of the first electrode AE ​​of the second light-emitting element ED2. The third light-emitting aperture PDL-OP3 can expose at least a portion of the first electrode AE ​​of the third light-emitting element ED3.

[0116] The first to third light-emitting layers EML1, EML2, and EML3 can be disposed on the first electrode AE ​​and the pixel defining layer PDL. The first to third light-emitting layers EML1, EML2, and EML3 can be disposed within the first to third light-emitting openings PDL-OP1, PDL-OP2, and PDL-OP3, respectively. The first light-emitting layer EML1 can be superimposed on the first light-emitting opening PDL-OP1 in a planar view and can be disposed on the first electrode AE ​​of the first light-emitting element ED1. The second light-emitting layer EML2 can be superimposed on the second light-emitting opening PDL-OP2 in a planar view and can be disposed on the first electrode AE ​​of the second light-emitting element ED2. The third light-emitting layer EML3 can be superimposed on the third light-emitting opening PDL-OP3 in a planar view and can be disposed on the first electrode AE ​​of the third light-emitting element ED3.

[0117] The second electrode CE can be disposed on the first to third light-emitting layers EML1, EML2, and EML3 and the pixel limiting layer PDL. The second electrode CE can be stacked with the first to third light-emitting openings PDL-OP1, PDL-OP2, and PDL-OP3 in a planar view. The second electrode CE of the first light-emitting element ED1 can be stacked with the first light-emitting opening PDL-OP1 in a planar view and can be disposed on the first light-emitting layer EML1. The second electrode CE of the second light-emitting element ED2 can be stacked with the second light-emitting opening PDL-OP2 in a planar view and can be disposed on the second light-emitting layer EML2. The second electrode CE of the third light-emitting element ED3 can be stacked with the third light-emitting opening PDL-OP3 in a planar view and can be disposed on the third light-emitting layer EML3. In an embodiment, the second electrodes CE of the first to third light-emitting elements ED1, ED2, and ED3 can be formed as a common layer and configured as a single electrode.

[0118] Figure 5 Exemplary illustration shows first to third light-emitting layers EML1, EML2, and EML3 arranged on the first electrode AE ​​of the first to third light-emitting elements ED1, ED2, and ED3 and the pixel defining layer PDL, but this disclosure is not limited thereto. In another example, the first to third light-emitting layers EML1, EML2, and EML3 may be arranged only on the first electrode AE ​​of the first to third light-emitting elements ED1, ED2, and ED3.

[0119] The first to the third light-emitting layers, EML1, EML2, and EML3, can provide light of different colors. For example, the first light-emitting layer EML1 can provide red light, the second light-emitting layer EML2 can provide green light, and the third light-emitting layer EML3 can provide blue light.

[0120] The sacrificial pattern SP may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. Each of the first to third sacrificial patterns SP1, SP2, and SP3 may be disposed on the upper surface of the corresponding first electrode AE. In the planar view, the first to third sacrificial openings S-OP1, S-OP2, and S-OP3 superimposed with the first to third light-emitting openings PDL-OP1, PDL-OP2, and PDL-OP3 may be defined in the first to third sacrificial patterns SP1, SP2, and SP3, respectively.

[0121] The anti-reflective layer ARL may include a color filter layer CF and an outer coating layer OC. The color filter layer CF can be directly disposed on the inorganic encapsulation film 141, and the outer coating layer OC can be directly disposed on the color filter layer CF.

[0122] The color filter layer CF may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. At least a portion of the first color filter CF1 may be superimposed on a first light-emitting region LA1. At least a portion of the second color filter CF2 may be superimposed on a second light-emitting region LA2. At least a portion of the third color filter CF3 may be superimposed on a third light-emitting region LA3.

[0123] The first to third color filters CF1, CF2, and CF3 correspond to the first to third light-emitting elements ED1, ED2, and ED3, respectively. They can transmit light generated by the first to third light-emitting elements ED1, ED2, and ED3, and can block light of certain wavelengths from the external light source. The first color filter CF1 can transmit light of a first color, the second color filter CF2 can transmit light of a second color, and the third color filter CF3 can transmit light of a third color. The second color can be different from the first color, and the third color can be different from both the first and second colors. For example, the first color can be red, the second color can be green, and the third color can be blue.

[0124] Each of the first to third color filters CF1, CF2, and CF3 may include a polymeric photosensitive resin and a colorant. In the specification, the colorant includes pigments and dyes. A red colorant may include red pigments and red dyes, a green colorant may include green pigments and green dyes, and a blue colorant may include blue pigments and blue dyes.

[0125] For example, the first color filter CF1 may include red pigment or red dye, the second color filter CF2 may include green pigment or green dye, and the third color filter CF3 may include blue pigment or blue dye. Of the light provided from the light-emitting element layer 130, light passing through the first color filter CF1 can provide red light to the outside of the display panel DP, light passing through the second color filter CF2 can provide green light to the outside of the display panel DP, and light passing through the third color filter CF3 can provide blue light to the outside of the display panel DP.

[0126] According to the embodiment, color filters CF1, CF2, and CF3 are directly arranged on the display layer DPL. Therefore, the color filter layer CF can cover the second electrode CE of the first light-emitting element ED1, the second electrode CE of the second light-emitting element ED2, and the second electrode CE of the third light-emitting element ED3. Thus, the reflection of external light caused by the electrodes inside the display layer DPL (e.g., the first electrode AE ​​and the second electrode CE of the first to third light-emitting elements ED1, ED2, and ED3) can be effectively reduced or prevented.

[0127] In embodiments of this disclosure, at least portions of the first to third color filters CF1, CF2, and CF3 may be stacked on top of each other in an area not overlapping any of the first to third luminous regions LA1, LA2, and LA3. That is, at least portions of the first to third color filters CF1, CF2, and CF3 may be arranged in a stacked manner on the third-direction DR3 in an area overlapping the non-luminous region NLA. The first to third color filters CF1, CF2, and CF3 stacked on top of each other in the thickness direction (i.e., the third-direction DR3) may block light passing through the non-luminous region NLA to prevent color mixing between the first to third luminous regions LA1, LA2, and LA3. For example, the first color filter CF1 may include openings corresponding to the second luminous region LA2 and the third luminous region LA3, and may be configured to overlap with the first luminous region LA1 and the non-luminous region NLA. The second color filter CF2 may include openings corresponding to the first luminous region LA1 and the third luminous region LA3, and may be configured to overlap with the second luminous region LA2 and the non-luminous region NLA. The third color filter CF3 may include openings corresponding to the first luminescent region LA1 and the second luminescent region LA2, and may be configured to overlap with the third luminescent region LA3 and the non-luminescent region NLA.

[0128] However, the embodiments are not limited to this. In another embodiment, the first to third color filters CF1, CF2, and CF3 may not overlap each other in the thickness direction (i.e., the third direction DR3). For example, the first to third color filters CF1, CF2, and CF3 may be arranged in a pattern corresponding to the first to third light-emitting elements ED1, ED2, and ED3, respectively. Optionally, only two of the first to third color filters CF1, CF2, and CF3 may overlap each other in the thickness direction. For example, the first color filter CF1 and the second color filter CF2 may be arranged in a pattern corresponding to the first light-emitting region LA1 and the second light-emitting region LA2, and the third color filter CF3 may include an opening corresponding to the first light-emitting region LA1 and the second light-emitting region LA2 and may be arranged to overlap with the third light-emitting region LA3 and the non-light-emitting region NLA.

[0129] The outer coating OC can cover the color filter layer CF. The outer coating OC can cover the first color filter CF1, the second color filter CF2, and the third color filter CF3. The outer coating OC can contain an organic material and provide a flat upper surface. The organic material can be transparent and can include, for example, acrylic resins. According to an embodiment, the outer coating OC can protect the light-emitting element layer 130 from foreign matter such as dust particles.

[0130] In this embodiment, the outer coating OC can be formed by coating or deposition processes. More specifically, the outer coating OC can be formed by forming an organic layer via methods such as coating and deposition, followed by selectively patterning the organic layer by photolithography and etching. In this case, a higher level of flatness can be maintained at its edges, and a smaller thickness can be provided compared to cases where the organic layer is formed by inkjet processes. Therefore, the distance between the light-emitting element ED and the light-shielding layer 200-SDL can be effectively reduced, and the viewing angle can be effectively widened.

[0131] The input sensor layer ISL can be disposed on the anti-reflective layer ARL. In an embodiment, the input sensor layer ISL may include a first sensing insulating layer 200-IL1, a first conductive layer 200-CL1, a second sensing insulating layer 200-IL2, a second conductive layer 200-CL2, a light-shielding layer 200-SDL, and a third sensing insulating layer 200-IL3.

[0132] Multiple apertures, OPR, OPG, and OPB, can be defined within the light-shielding layer 200-SDL. The apertures OPR, OPG, and OPB can be stacked with the first to third light-emitting layers EML1, EML2, and EML3, respectively, and can be referred to as the first to third aperture OPR, OPG, and OPB. The first to third color filters CF1, CF2, and CF3 can be arranged to correspond to the first to third apertures OPR, OPG, and OPB, respectively. Of the light passing through the color filter layer CF, the light passing through the first to third apertures OPR, OPG, and OPB of the light-shielding layer 200-SDL can be exhausted to the outside of the display panel DP.

[0133] Figure 6A This is a cross-sectional view of a display panel DP according to an embodiment of the present disclosure. Figure 6B This illustrates a display panel DP according to an embodiment of the present disclosure (see...). Figure 6A A floor plan of some components of ). Figure 6C It shows Figure 6A An enlarged sectional view of region AA'. Figure 6D It shows Figure 6A An enlarged sectional view of region BB'. Figure 6A It shows Figure 5 A magnified view of a portion thereof, showing a first luminescent region LA1, a second luminescent region LA2, and a non-luminescent region NLA surrounding the first luminescent region LA1 and the second luminescent region LA2 in a planar view. Figure 6B This shows the display panel DP (see) Figure 6A A magnified planar view of a portion of the pixel-defined layer (PDL) within the component, and similar to... Figure 6AThe diagram shows a first luminescent region LA1, a second luminescent region LA2, and an enlarged view of a non-luminescent region NLA surrounding the first luminescent region LA1 and the second luminescent region LA2 in a planar view. In the following text, with reference to... Figures 6A to 6D In the description, the same / similar reference numerals are used for Figures 3 to 5 The same / similar components described in the previous section will be omitted, and repeated descriptions will be omitted.

[0134] Reference Figures 6A to 6D The display panel DP according to an embodiment may include a first trench TRC1 and a second trench TRC2. Each of the first trench TRC1 and the second trench TRC2 may be defined within a sixth insulating layer 60 and a pixel defining layer PDL. The first trench TRC1 and the second trench TRC2 may be separated from the first light-emitting opening PDL-OP1 and the second light-emitting opening PDL-OP2. A spacer SPC may be disposed in the first trench TRC1. The second trench TRC2 may surround the first trench TRC1 in a plan view. The first trench TRC1 and the second trench TRC2 will be described in detail below.

[0135] A first groove GRV1 can be defined in the sixth insulating layer 60 by removing a portion of it in the thickness direction (i.e., the third direction DR3). A second groove GRV2 can be defined in the sixth insulating layer 60 by removing a portion of it in the thickness direction (i.e., the third direction DR3). The second groove GRV2 may surround the first groove GRV1 in a plan view. In the planar plane, the second groove GRV2 may have a ring shape surrounding the first groove GRV1.

[0136] The sixth insulating layer 60 may include an upper surface US, a first inner surface IS1, and a first bottom surface BS1 defining a first groove GRV1, and a second inner surface IS2, a third inner surface IS3, and a second bottom surface BS2 defining a second groove GRV2. The first inner surface IS1 can connect the upper surface US and the first bottom surface BS1. The second inner surface IS2 and the third inner surface IS3 can connect the upper surface US and the second bottom surface BS2. The second inner surface IS2 and the third inner surface IS3 may face each other, and the second inner surface IS2 may be arranged closer to the first groove GRV1 than the third inner surface IS3.

[0137] The first separating opening SP-OP1 and the second separating opening SP-OP2 can be defined in the pixel definition layer PDL. The first separating opening SP-OP1 and the second separating opening SP-OP2 can be arranged to be separated from the light-emitting opening PDL-OP.

[0138] like Figure 6A and Figure 6CAs shown, the first partition opening SP-OP1 can be superimposed on the first groove GRV1 in the plan view. The first partition opening SP-OP1 and the first groove GRV1 can form an integral space. The first groove TRC1 can be provided by the first partition opening SP-OP1 and the first groove GRV1 formed in the integral space.

[0139] A portion of the pixel defining layer PDL can protrude from the first inner surface IS1 of the sixth insulating layer 60 defining the first groove GRV1 in a direction toward the center of the first groove GRV1. That is, a portion of the pixel defining layer PDL can be superimposed on the first groove GRV1 in a planar view. The portion of the pixel defining layer PDL protruding from the first inner surface IS1 can define a first tip TIP1.

[0140] The sixth insulating layer 60, which defines the first trench TRC1, and the pixel defining layer PDL can have an undercut shape or a hanging structure. In a cross-sectional view, the width of the first separating opening SP-OP1 in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2 can be less than the maximum width of the first groove GRV1 in that direction.

[0141] like Figure 6A and Figure 6D As shown, the second partition opening SP-OP2 can be superimposed on the second groove GRV2 in the plan view. The second partition opening SP-OP2 and the second groove GRV2 can form an integral space. The second groove TRC2 can be provided by the second partition opening SP-OP2 and the second groove GRV2 formed in the integral space.

[0142] A portion of the pixel defining layer PDL may protrude from the second inner surface IS2 of the sixth insulating layer 60 defining the second groove GRV2 in a direction away from the first groove GRV1. A portion of the pixel defining layer PDL may protrude from one inner edge of the sixth insulating layer 60 defining the second groove GRV2. That is, a portion of the pixel defining layer PDL may be superimposed on the second groove GRV2 in a planar view. The portion of the pixel defining layer PDL protruding from the second inner surface IS2 may define a second tip TIP2. Another portion of the pixel defining layer PDL may protrude from the third inner surface IS3 of the sixth insulating layer 60 defining the second groove GRV2 in a direction toward the first groove GRV1. Another portion of the pixel defining layer PDL may protrude from another inner edge of the sixth insulating layer 60 defining the second groove GRV2. That is, another portion of the pixel defining layer PDL may be superimposed on the second groove GRV2 in a planar view. Another portion of the pixel defining layer PDL protruding from the third inner surface IS3 may define a third tip TIP3. The sixth insulating layer 60, which defines the first trench TRC1 and the second trench TRC2, and the pixel defining layer PDL can have an undercut shape or a hanging structure. In a cross-sectional view, the width of the second separating opening SP-OP2 in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2 can be less than the maximum width of the second groove GRV2 in that direction.

[0143] Figure 6B An exemplary illustration shows a first dividing opening SP-OP1 having a circular shape in a plane (i.e., in a plan view) and a second dividing opening SP-OP2 having a loop shape (or hook shape or closed curve shape) in a plane (i.e., in a plan view), but the shapes of the first dividing opening SP-OP1 and the second dividing opening SP-OP2 are not limited thereto. For another example, the first dividing opening SP-OP1 may have an elliptical or polygonal shape, and the second dividing opening SP-OP2 may have various shapes, as long as the second dividing opening SP-OP2 is configured to surround the first dividing opening SP-OP1 in a plan view.

[0144] like Figure 6A and Figure 6C As shown, at least a portion of the spacer SPC can be disposed in the first groove TRC1. That is, at least a portion of the spacer SPC can be disposed in the first dividing opening SP-OP1 and the first groove GRV1. The spacer SPC may include a first portion P1 disposed in the first groove TRC1 and a second portion P2 extending from the first portion P1 and protruding in a direction away from the first dividing opening SP-OP1 (i.e., the third direction DR3).

[0145] The first portion P1 of the spacer SPC can contact the first inner surface IS1 and the first bottom surface BS1 of the sixth insulating layer 60 defining the first groove GRV1. Furthermore, the first portion P1 of the spacer SPC can contact the inner surface PDL-IS1 of the pixel defining layer PDL defining the first separating opening SP-OP1 and the lower surface PDL-BS1 of the pixel defining layer PDL exposed from the sixth insulating layer 60. That is, the first portion P1 of the spacer SPC can contact the first tip TIP1. Since a portion of the spacer SPC is disposed within the first trench TRC1, the area in which the spacer SPC contacts the sixth insulating layer 60 and the pixel defining layer PDL can be increased, and the adhesion of the spacer SPC can be improved. Therefore, the spacer SPC can be disposed with a relatively reduced width.

[0146] The second portion P2 of the spacer SPC may have a shape that protrudes from the pixel defining layer PDL, and thus can support a fine metal mask (“FMM”) in the process of forming the first light-emitting layer EML1 and the second light-emitting layer EML2.

[0147] The spacer SPC can be disposed within the island structure of the pixel defining layer PDL. Specifically, a first separating opening SP-OP1 and a second separating opening SP-OP2 that completely surrounds the first separating opening SP-OP1 in a plan view are defined within the pixel defining layer PDL, thus portions of the pixel defining layer PDL can be arranged in a spaced pattern. After the process of forming the first light-emitting layer EML1 and the second light-emitting layer EML2, even if foreign matter remains in the spacer SPC or the spacer SPC is damaged due to scratches from the FMM, since the spacer SPC is disposed within the island structure of the pixel defining layer PDL separated by the second separating opening SP-OP2, defects in the first light-emitting element ED1 and the second light-emitting element ED2 caused by residual foreign matter or damage to the spacer SPC can be effectively reduced or prevented.

[0148] The display panel DP according to an embodiment may further include a dummy pattern DPA. The dummy pattern DPA may include a first dummy pattern DPA1 and a second dummy pattern DPA2. The first dummy pattern DPA1 may be disposed inside the second groove GRV2. The second dummy pattern DPA2 may be disposed on the pixel defining layer PDL and may cover the spacer SPC. The second dummy pattern DPA2 may be superimposed on the first groove TRC1 in a plan view.

[0149] The first dummy pattern DPA1 and the second dummy pattern DPA2 can be separated from the second electrode CE. The first dummy pattern DPA1 and the second dummy pattern DPA2 can comprise the same material as the second electrode CE and can be formed using the same process as the second electrode CE. That is, the first dummy pattern DPA1 and the second dummy pattern DPA2 can be formed simultaneously when portions of them are separated from the second electrode CE by the second tip TIP2 and the third tip TIP3 during the process of forming the second electrode CE. The dummy pattern DPA can be referred to as a dummy electrode. In another embodiment, according to the embodiment, the dummy pattern DPA can be removed or may not be formed.

[0150] An inorganic encapsulation film 141 may be disposed on the second electrode CE and the spacer SPC. The inorganic encapsulation film 141 may cover the second electrode CE and the dummy pattern DPA. A portion of the inorganic encapsulation film 141 may be disposed inside the second trench TRC2. The inorganic encapsulation film 141 may contact the inner surface PDL-IS2 of the pixel defining layer PDL defining the second separating opening SP-OP2 and the lower surface PDL-BS2 of the pixel defining layer PDL exposed from the upper surface US of the sixth insulating layer 60. Furthermore, the inorganic encapsulation film 141 may contact the second inner surface IS2 and the third inner surface IS3 of the sixth insulating layer 60 defining the second groove GRV2, and may contact the first dummy pattern DPA1 inside the second groove GRV2. The inorganic encapsulation film 141 may cover the second dummy pattern DPA2.

[0151] The inorganic encapsulation film 141 can contact the second tip TIP2 and the third tip TIP3. Since the second tip TIP2 and the third tip TIP3 can protrude from the second inner surface IS2 and the third inner surface IS3, and the inorganic encapsulation film 141 can surround these protrusions, the penetration path of moisture, oxygen, and dust particles from the outside to the light-emitting element ED can be lengthened (i.e., thickened). Therefore, penetration into the light-emitting element ED can be delayed or prevented. Furthermore, moisture penetration into the light-emitting element ED can be prevented, thereby preventing defects in the light-emitting element ED. For example, growth spots (“GDS”) defects caused by the penetration of moisture, oxygen, and dust particles can be reduced. Therefore, a display device DD with improved display quality (see...) can be provided. Figure 1 ).

[0152] The portions of the first to third color filters CF1, CF2, and CF3 can be arranged inside the second trench TRC2. That is, the portions of the first to third color filters CF1, CF2, and CF3 can be arranged inside the second separating opening SP-OP2 and the second groove GRV2. The portions of the first to third color filters CF1, CF2, and CF3 can be arranged inside the second trench TRC2 and contact the inorganic encapsulation film 141. Figure 6A An exemplary illustration shows a first color filter CF1 disposed in a portion of the second trench TRC2 adjacent to the first light-emitting element ED1, and a second color filter CF2 disposed in a portion of the second trench TRC2 adjacent to the second light-emitting element ED2. However, the types of color filters CF1, CF2, and CF3 disposed within the second trench TRC2 can vary depending on the position of the second trench TRC2.

[0153] Figure 7 This is a cross-sectional view of the display panel DP-1 according to an embodiment of the present disclosure. Figure 7 It shows Figure 5 This is a magnified view of a portion of the image, showing a first luminescent region LA1, a second luminescent region LA2, and a non-luminescent region NLA surrounding the first luminescent region LA1 and the second luminescent region LA2 in a planar view. In the following text, with reference to... Figure 7 In the description, the same / similar reference numerals are used for Figures 3 to 6D The same / similar components described in the previous section will be omitted, and repeated descriptions will be omitted.

[0154] Reference Figure 7 According to embodiments of the present disclosure, the display panel DP-1 may include an inorganic encapsulation film 141a having a multilayer structure in which multiple layers are stacked on a third-direction DR3. The inorganic encapsulation film 141a may include a first inorganic encapsulation film 141-1 and a second inorganic encapsulation film 141-2.

[0155] The second inorganic encapsulation film 141-2 can be directly disposed on the first inorganic encapsulation film 141-1. The second inorganic encapsulation film 141-2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc. When depositing the first inorganic encapsulation film 141-1 and the second inorganic encapsulation film 141-2, atomic layer deposition (“ALD”) and chemical vapor deposition (“CVD”) processes can be used. Both the first inorganic encapsulation film 141-1 and the second inorganic encapsulation film 141-2 can be formed by the ALD process, or both can be formed by the CVD process. Optionally, the first inorganic encapsulation film 141-1 and the second inorganic encapsulation film 141-2 can be formed by both ALD and CVD processes, or both can be formed by both CVD and ALD processes. When the first inorganic encapsulation film 141-1 and the second inorganic encapsulation film 141-2 are formed by the ALD process, a uniform and thin encapsulation film can be formed compared with the case where the first inorganic encapsulation film 141-1 and the second inorganic encapsulation film 141-2 are formed by the CVD process.

[0156] Figure 8A This is a cross-sectional view of the display panel DP-2 according to an embodiment of the present disclosure. Figure 8B This illustrates a display panel DP-2 according to an embodiment of the present disclosure (see...). Figure 8A An enlarged plan view of part of the structure. Figure 8A It shows Figure 5 A magnified view of a portion thereof, showing a first luminescent region LA1, a second luminescent region LA2, and a non-luminescent region NLA surrounding the first luminescent region LA1 and the second luminescent region LA2 in a planar view. Figure 8B This shows the display panel DP-2 (see...) Figure 8A A magnified planar view of a portion of the pixel-limited layer PDLa in the component, and similar to Figure 8A The diagram shows a first luminescent region LA1, a second luminescent region LA2, and an enlarged view of a non-luminescent region NLA surrounding the first luminescent region LA1 and the second luminescent region LA2 in a planar view. In the following text, with reference to... Figure 8A and Figure 8B In the description, the same / similar reference numerals are used for Figures 3 to 6D The same / similar components described in the previous section will be omitted, and repeated descriptions will be omitted.

[0157] Reference Figure 8A and Figure 8BThe display panel DP-2 according to embodiments of the present disclosure may further include a third trench TRC3. The third trench TRC3 may be defined within the sixth insulating layer 60a and the pixel defining layer PDLa. The third trench TRC3 may be separated from the first light-emitting opening PDL-OP1 and the second light-emitting opening PDL-OP2. The third trench TRC3 may surround the second trench TRC2 in a plan view. The third trench TRC3 will be described in detail below.

[0158] A third groove GRV3 can be additionally defined in the sixth insulating layer 60a by removing a portion of the sixth insulating layer 60a in the thickness direction (i.e., the third third direction DR3). The third groove GRV3 may surround the second groove GRV2 in a plan view. In the planar view, the third groove GRV3 may have a ring shape surrounding the second groove GRV2.

[0159] The sixth insulating layer 60a may further include a fourth inner surface IS4, a fifth inner surface IS5, and a third bottom surface BS3 defining the third groove GRV3. The fourth inner surface IS4 and the fifth inner surface IS5 can connect the upper surface of the sixth insulating layer 60a and the third bottom surface BS3. The fourth inner surface IS4 and the fifth inner surface IS5 can face each other, and the fourth inner surface IS4 can be arranged closer to the first groove GRV1 and the second groove GRV2 than the fifth inner surface IS5.

[0160] A third separating opening SP-OP3 can be additionally defined in the pixel-defining layer PDLa. The third separating opening SP-OP3 can be separated from the light-emitting openings PDL-OP1 and PDL-OP2.

[0161] The third partition opening SP-OP3 can be superimposed on the third groove GRV3 in the plan view. The third partition opening SP-OP3 and the third groove GRV3 can form an integral space. The third groove TRC3 can be set by the third partition opening SP-OP3 and the third groove GRV3 formed in the integral space.

[0162] A portion of the pixel-defining layer PDLa may protrude from the fourth inner surface IS4 of the sixth insulating layer 60a defining the third groove GRV3 in a direction away from the second groove GRV2. That is, a portion of the pixel-defining layer PDLa may overlap with the third groove GRV3 in a plan view. The portion of the pixel-defining layer PDLa protruding from the fourth inner surface IS4 may define a fourth tip TIP4. Another portion of the pixel-defining layer PDLa may protrude from the fifth inner surface IS5 of the sixth insulating layer 60a defining the third groove GRV3 in a direction toward the second groove GRV2. That is, another portion of the pixel-defining layer PDLa may overlap with the third groove GRV3 in a plan view. The other portion of the pixel-defining layer PDLa protruding from the fifth inner surface IS5 may define a fifth tip TIP5. The sixth insulating layer 60a defining the third groove TRC3 and the pixel-defining layer PDLa may have an undercut shape or a cantilever structure. In a cross-sectional view, the width of the third separating opening SP-OP3 in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2 may be less than the maximum width of the third groove GRV3 in said direction.

[0163] Figure 8B An exemplary illustration shows that the first dividing opening SP-OP1 has a circular shape in the plane (i.e., in a plan view) and the second dividing opening SP-OP2 and the third dividing opening SP-OP3 have annular shapes in the plane (i.e., in a plan view), but the shapes of the first dividing opening SP-OP1 and the second dividing opening SP-OP2 and the third dividing opening SP-OP3 are not limited thereto. For another example, the first dividing opening SP-OP1 may have an elliptical or polygonal shape, and the second dividing opening SP-OP2 and the third dividing opening SP-OP3 may have various shapes, as long as the second dividing opening SP-OP2 and the third dividing opening SP-OP3 are arranged to surround the first dividing opening SP-OP1 in the plan view.

[0164] The display panel DP-2 according to an embodiment of the present disclosure may further include a dummy pattern DPAa, and the dummy pattern DPAa may include a first dummy pattern DPA1, a second dummy pattern DPA2, and a third dummy pattern DPA3. That is, in the display panel DP-2 according to an embodiment of the present disclosure, the dummy pattern DPAa may further include a third dummy pattern DPA3. The third dummy pattern DPA3 may be disposed inside the third groove GRV3. The third dummy pattern DPA3 may be superimposed on the third groove TRC3 in a plan view.

[0165] The third dummy pattern DPA3 can be separated from the second electrode CE. The third dummy pattern DPA3 can comprise the same material as the second electrode CE and can be formed in the same process as the second electrode CE. That is, the third dummy pattern DPA3 can be formed when a portion of it is separated from the second electrode CE by the fourth tip TIP4 and the fifth tip TIP5 during the process of forming the second electrode CE. The third dummy pattern DPA3 can be separated from the first dummy pattern DPA1 and the second dummy pattern DPA2, and can be formed simultaneously.

[0166] An inorganic encapsulation film 141 can be disposed on the second electrode CE and the spacer SPC. The inorganic encapsulation film 141 can cover the second electrode CE and the dummy pattern DPAa. A portion of the inorganic encapsulation film 141 can be disposed inside the third trench TRC3. The inorganic encapsulation film 141 can contact the inner surface PDL-IS3 of the pixel defining layer PDLa, which defines the third separating opening SP-OP3, and the lower surface PDL-BS3 of the pixel defining layer PDLa, which is exposed from the upper surface of the sixth insulating layer 60a. Furthermore, the inorganic encapsulation film 141 can contact the fourth inner surface IS4 and the fifth inner surface IS5 of the sixth insulating layer 60a, which defines the third groove GRV3, and can contact the third dummy pattern DPA3 inside the third groove GRV3. The inorganic encapsulation film 141 can cover the third dummy pattern DPA3.

[0167] The inorganic encapsulation film 141 can contact the fourth tip TIP4 and the fifth tip TIP5. The fourth tip TIP4 and the fifth tip TIP5 can protrude from the fourth inner surface IS4 and the fifth inner surface IS5, respectively, and the inorganic encapsulation film 141 can surround these protrusions, thus extending (i.e., thickening) the penetration path of moisture, oxygen, and dust particles from the outside to the light-emitting element ED. Therefore, penetration into the light-emitting element ED can be delayed or prevented. Furthermore, moisture penetration into the light-emitting element ED can be prevented, thereby preventing defects in the light-emitting element ED. For example, GDS defects caused by the penetration of moisture, oxygen, and dust particles can be reduced. Therefore, a display device DD with improved display quality (see...) can be provided. Figure 1 ).

[0168] The portions of the first to third color filters CF1, CF2, and CF3 can be arranged inside the third trench TRC3. That is, the portions of the first to third color filters CF1, CF2, and CF3 can be arranged inside the third separating opening SP-OP3 and the third recess GRV3. The portions of the first to third color filters CF1, CF2, and CF3 can be arranged inside the third trench TRC3 and contact the inorganic encapsulation film 141. Figure 8AAn exemplary illustration shows a first color filter CF1 disposed in a portion of the third trench TRC3 adjacent to the first light-emitting element ED1, and a second color filter CF2 disposed in a portion of the third trench TRC3 adjacent to the second light-emitting element ED2. However, the types of color filters CF1, CF2, and CF3 disposed within the third trench TRC3 can vary depending on the position of the third trench TRC3.

[0169] Figure 9 This is a cross-sectional view of the display panel DP-3 according to an embodiment of the present disclosure. In the following, with reference to... Figure 9 In the description, the same / similar reference numerals are used for Figures 3 to 6D The same / similar components described in the previous section will be omitted, and repeated descriptions will be omitted.

[0170] Reference Figure 9 The display panel DP-3 according to embodiments of the present disclosure may further include a seventh insulating layer 70 and an eighth insulating layer 80.

[0171] The seventh insulating layer 70 can be disposed between the sixth insulating layer 60b and the pixel defining layer PDLb. The first-1 lower opening L-OP11 and the first-2 lower opening L-OP12 can be defined within the seventh insulating layer 70. The first-1 lower opening L-OP11 and the first-2 lower opening L-OP12 can be connected to the light-emitting opening PDL-OP (see...). Figure 6A Separated by ), the first lower opening L-OP11 can be superimposed on the first groove GRV1 in the plan view. The second lower opening L-OP12 can be superimposed on the second groove GRV2 in the plan view. The seventh insulating layer 70 can be referred to as the "first intermediate insulating layer".

[0172] In the cross-sectional view, the width of the lower opening L-OP11 of the 1-1 in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2 may be less than the maximum width of the first groove GRV1 in that direction. A portion of the seventh insulating layer 70 may protrude from the first inner surface IS1 of the sixth insulating layer 60b defining the first groove GRV1 in a direction toward the center of the first groove GRV1. That is, a portion of the seventh insulating layer 70 may overlap with the first groove GRV1 in the plan view. The portion of the seventh insulating layer 70 protruding from the first inner surface IS1 may define a first lower tip TIP1-L. The sixth insulating layer 60b, the seventh insulating layer 70, the eighth insulating layer 80, and the pixel defining layer PDLb, which define the first trench TRC1b, may have an undercut shape or a hanging structure.

[0173] In the cross-sectional view, the width of the first-second lower opening L-OP12 in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2 may be less than the maximum width of the second groove GRV2 in that direction. A portion of the seventh insulating layer 70 may protrude from the second inner surface IS2 of the sixth insulating layer 60b defining the second groove GRV2 in a direction away from the first groove GRV1. That is, a portion of the seventh insulating layer 70 may overlap with the second groove GRV2 in the plan view. The portion of the seventh insulating layer 70 protruding from the second inner surface IS2 may define a second lower tip TIP2-L. Another portion of the seventh insulating layer 70 may protrude from the third inner surface IS3 of the sixth insulating layer 60b defining the second groove GRV2 in a direction toward the first groove GRV1. That is, another portion of the seventh insulating layer 70 may overlap with the second groove GRV2 in the plan view. Another portion of the seventh insulating layer 70 protruding from the third inner surface IS3 may define a third lower tip TIP3-L.

[0174] The seventh insulating layer 70 may include an inorganic insulating material. For example, the seventh insulating layer 70 may include silicon nitride (SiN). x In one embodiment, the seventh insulating layer 70 may comprise the same material as the pixel defining layer PDLb. However, the embodiments are not limited thereto.

[0175] The eighth insulating layer 80 can be disposed between the seventh insulating layer 70 and the pixel defining layer PDLb. The second-first lower opening L-OP21 and the second-second lower opening L-OP22 can be defined within the eighth insulating layer 80. The second-first lower opening L-OP21 and the second-second lower opening L-OP22 can be connected to the light-emitting opening PDL-OP (see...). Figure 6A Separated by ), the lower opening L-OP21 of the 2-1 type can be superimposed on the first groove GRV1 in the plan view. The lower opening L-OP22 of the 2-2 type can be superimposed on the second groove GRV2 in the plan view. The eighth insulating layer 80 can be referred to as the "second intermediate insulating layer".

[0176] In the cross-sectional view, the width of the 2-1 lower opening L-OP21 in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2 may be greater than the width of the 1-1 lower opening L-OP11 in that direction. The portion of the seventh insulating layer 70 defining the first lower tip TIP1-L may protrude from the inner surface ISa of the eighth insulating layer 80 defining the 2-1 lower opening L-OP21. In the cross-sectional view, the width of the 2-2 lower opening L-OP22 in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2 may be greater than the width of the 1-2 lower opening L-OP12 in that direction. That is, a portion of the seventh insulating layer 70 may protrude from the inner surfaces ISb and ISc of the eighth insulating layer 80 defining the 2-2 lower opening L-OP22.

[0177] The eighth insulating layer 80 may be an organic layer. In an embodiment, the eighth insulating layer 80 may comprise the same material as the sixth insulating layer 60b. However, the embodiments are not limited thereto.

[0178] A pixel-defining layer PDLb can be disposed on an eighth insulating layer 80. A first separating opening SP-OP1 and a second separating opening SP-OP2 can be defined within the pixel-defining layer PDLb. The first separating opening SP-OP1 can be superimposed on a first groove GRV1, a first-1 lower opening L-OP11, and a second-1 lower opening L-OP21 in a planar view. The second separating opening SP-OP2 can be superimposed on a second groove GRV2, a first-2 lower opening L-OP12, and a second-2 lower opening L-OP22 in a planar view.

[0179] In a cross-sectional view, the width of the first separating opening SP-OP1 in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2 may be less than the maximum width of the second-1st lower opening L-OP21 in said direction. In an embodiment, a portion of the pixel defining layer PDLb may protrude from the inner surface ISa of the eighth insulating layer 80 defining the second-1st lower opening L-OP21 in a direction toward the center of the first recess GRV1. That is, a portion of the pixel defining layer PDLb may overlap with the second-1st lower opening L-OP21 in a plan view. The portion of the pixel defining layer PDLb protruding from the inner surface ISa of the eighth insulating layer 80 defining the second-1st lower opening L-OP21 may define a first upper tip TIP1-U. Compared to the seventh insulating layer 70 and the pixel defining layer PDLb, the inner surface ISa of the eighth insulating layer 80 defining the second-1st lower opening L-OP21 may be recessed.

[0180] In a cross-sectional view, the width of the second separating opening SP-OP2 in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2 may be less than the maximum width of the second-second lower opening L-OP22 in that direction. In an embodiment, a portion of the pixel defining layer PDLb may protrude from the inner surfaces ISb and ISc of the eighth insulating layer 80 defining the second-second lower opening L-OP22 in a direction away from or towards the first recess GRV1. That is, a portion of the pixel defining layer PDLb may overlap with the second-second lower opening L-OP22 in a plan view. The portion of the pixel defining layer PDLb protruding from the inner surfaces ISb and ISc of the eighth insulating layer 80 defining the second-second lower opening L-OP22 may define a second upper tip TIP2-U and a third upper tip TIP3-U. The second upper tip TIP2-U may protrude in a direction away from the first recess GRV1, and the third upper tip TIP3-U may protrude in a direction towards the first recess GRV1. Compared to the seventh insulating layer 70 and the pixel defining layer PDLb, the inner surfaces ISb and ISc of the eighth insulating layer 80 defining the second-second lower opening L-OP22 can be recessed.

[0181] The first groove GRV1, the first lower opening L-OP11, the second lower opening L-OP21, and the first partition opening SP-OP1 can form an integral space. The first trench TRC1b can be provided by the first groove GRV1, the first lower opening L-OP11, the second lower opening L-OP21, and the first partition opening SP-OP1 formed in an integral space. The sixth insulating layer 60b, the seventh insulating layer 70, the eighth insulating layer 80, and the pixel defining layer PDLb defining the first trench TRC1b can have an undercut shape or a hanging structure.

[0182] The second groove GRV2, the second-second lower opening L-OP22, the first-second lower opening L-OP12, and the second partition opening SP-OP2 can form an integral space. The second trench TRC2b can be formed by the second groove GRV2, the second-second lower opening L-OP22, the first-second lower opening L-OP12, and the second partition opening SP-OP2 within the integral space. The sixth insulating layer 60b, the seventh insulating layer 70, the eighth insulating layer 80, and the pixel defining layer PDLb, which define the second trench TRC2b, can have an undercut shape or a hanging structure. Although... Figure 9 An exemplary structure is shown in which two tips are stacked on top of each other in the thickness direction (i.e., the third direction DR3), but there is no limitation on the number of tips formed in the thickness direction.

[0183] At least a portion of the spacer SPC may be disposed within the first groove TRC1b. That is, at least a portion of the spacer SPC may be disposed within the first recess GRV1, the first-1 lower opening L-OP11, the second-1 lower opening L-OP21, and the first dividing opening SP-OP1. The spacer SPC may include a first portion P1 disposed in the first groove TRC1b and a second portion P2 extending from the first portion P1 and protruding in a direction away from the first dividing opening SP-OP1.

[0184] An inorganic encapsulation film 141 can be disposed on the second electrode CE and the spacer SPC. The inorganic encapsulation film 141 can cover the second electrode CE and the dummy pattern DPA. A portion of the inorganic encapsulation film 141 can be disposed inside the second trench TRC2b. The inorganic encapsulation film 141 can contact the second lower tip TIP2-L, the third lower tip TIP3-L, the second upper tip TIP2-U, and the third upper tip TIP3-U. Furthermore, the inorganic encapsulation film 141 can contact the inner surfaces ISb and ISc of the seventh insulating layer 70 defining the first-second lower opening L-OP12 and the eighth insulating layer 80 defining the second-second lower opening L-OP22. The inorganic encapsulation film 141 can contact the first dummy pattern DPA1 inside the second groove GRV2. The inorganic encapsulation film 141 can cover the second dummy pattern DPA2.

[0185] The inorganic encapsulation film 141 surrounds multiple tips (e.g., a second lower tip TIP2-L, a third lower tip TIP3-L, a second upper tip TIP2-U, and a third upper tip TIP3-U), thus extending (i.e., thickening) the penetration path of moisture, oxygen, and dust particles from the outside to the light-emitting element ED. Therefore, penetration into the light-emitting element ED can be delayed or prevented. Furthermore, moisture penetration into the light-emitting element ED can be prevented, thereby preventing defects in the light-emitting element ED. For example, GDS defects caused by the penetration of moisture, oxygen, and dust particles can be reduced. Therefore, a display device DD with improved display quality can be provided (see...). Figure 1 ).

[0186] Figures 10A to 10G This is a cross-sectional view illustrating some of the operations of a method for manufacturing a display panel (DP) according to an embodiment of this disclosure. The same / similar reference numerals are used for... Figures 1 to 9 The same / similar components described in the previous section will be omitted, and repeated descriptions will be omitted.

[0187] Reference Figures 10A to 10GThe method for manufacturing a display panel DP according to an embodiment may include setting an initial display panel DP-I, etching an initial sixth insulating layer 60-I, forming a spacer SPC, etching an initial sacrificial pattern SP-I, performing a heat treatment, forming a light-emitting layer EML and an inorganic encapsulation film 141, forming an anti-reflective layer ARL, and forming an input sensor layer ISL.

[0188] like Figure 10A As shown, the manufacturing of the display panel DP according to an embodiment (see Figure 10G The method may include setting up a preliminary display panel DP-I. In an embodiment, the preliminary display panel DP-I includes an initial sixth insulating layer 60-I, a first electrode AE, an initial sacrificial pattern SP-I, and a pixel defining layer PDL. Although in Figure 10A Not shown, but the initial display panel DP-I may also include the above. Figure 4 The substrate layer 110 and the circuit layer 120 disposed on the substrate layer 110 are described herein, and the circuit layer 120 may include the components described herein. Figure 4 The buffer layer 10br, the first to fifth insulating layers 10, 20, 30, 40 and 50, the signal transmission region SCL, and the multiple connecting electrodes CNE1 and CNE2 described herein, as well as in Figure 10A The initial sixth insulating layer 60-I is shown in the figure.

[0189] Circuit layer 120 can be formed using general methods for manufacturing circuit elements (see...). Figure 4 This general method forms an insulating layer, a semiconductor layer, and a conductive layer through coating or deposition. The insulating layer, semiconductor layer, and conductive layer are selectively patterned through photolithography and etching processes to form semiconductor patterns, conductive patterns, signal lines, etc.

[0190] The light-emitting opening PDL-OP, the first dividing opening SP-OP1, and the second dividing opening SP-OP2 can be defined in the pixel-limiting layer PDL.

[0191] The light-emitting opening PDL-OP can expose a portion of the initial sacrificial pattern SP-I. The upper surface of the first electrode AE ​​can be covered by the initial sacrificial pattern SP-I, and the first electrode AE ​​can be left unexposed by the light-emitting opening PDL-OP.

[0192] The light-emitting aperture PDL-OP can be configured to have multiple light-emitting apertures. Figure 10A An example is shown of multiple light-emitting openings PDL-OP, including a first light-emitting opening PDL-OP1 and a second light-emitting opening PDL-OP2.

[0193] The initial sacrifice pattern SP-I can be set to multiple initial sacrifice patterns SP-I. Figure 10A An exemplary illustration shows multiple initial sacrificial patterns SP-I, including a first initial sacrificial pattern SP-I1 and a second initial sacrificial pattern SP-I2, a portion of the first initial sacrificial pattern SP-I1 being exposed by a first light-emitting opening PDL-OP1, and a portion of the second initial sacrificial pattern SP-I2 being exposed by a second light-emitting opening PDL-OP2.

[0194] The first dividing opening SP-OP1 and the second dividing opening SP-OP2 can be separated from the light-emitting opening PDL-OP. The second dividing opening SP-OP2 can surround the first dividing opening SP-OP1 in a plan view. The first dividing opening SP-OP1 can have a circular, elliptical, or polygonal shape in the plan (i.e., in a plan view), but this disclosure is not limited thereto. Similarly, the second dividing opening SP-OP2 can have various shapes, as long as the second dividing opening SP-OP2 is configured to surround the first dividing opening SP-OP1 in a plan view.

[0195] like Figure 10A and Figure 10B The manufacturing process of the display panel DP according to an embodiment is shown in the figure. Figure 10G The method may include etching an initial sixth insulating layer 60-I to form a sixth insulating layer 60. In an embodiment, during the etching of the initial sixth insulating layer 60-I, a first groove GRV1 and a second groove GRV2 may be formed on the initial sixth insulating layer 60-I using a pixel defining layer PDL and an initial sacrificial pattern SP-I as masks. That is, the sixth insulating layer 60, in which the first groove GRV1 and the second groove GRV2 are defined, can be formed by etching the initial sixth insulating layer 60-I. The first groove GRV1 may be formed to overlap with a first separating opening SP-OP1 of the pixel defining layer PDL in a planar view, and the second groove GRV2 may be formed to overlap with a second separating opening SP-OP2 of the pixel defining layer PDL in a planar view. In an embodiment, the etching process of the initial sixth insulating layer 60-I may be performed using a dry etching method.

[0196] According to an embodiment, without forming a separate mask, the pixel-defining layer (PDL) and the initial sacrificial pattern (SP-I) can be used as masks to form the first groove GRV1 and the second groove GRV2. More specifically, the portion of the initial sixth insulating layer 60-I exposed from the pixel-defining layer (PDL) through the first separating opening (SP-OP1) can be removed by etching gas, thus forming the first groove GRV1 corresponding to the first separating opening (SP-OP1) in the initial sixth insulating layer 60-I. The first separating opening (SP-OP1) and the first groove GRV1 can form a first trench TRC1. The portion of the initial sixth insulating layer 60-I exposed from the pixel-defining layer (PDL) through the second separating opening (SP-OP2) can be removed by etching gas, thus forming the second groove GRV2 corresponding to the second separating opening (SP-OP2) in the initial sixth insulating layer 60-I. The second separating opening (SP-OP2) and the second groove GRV2 can form a second trench TRC2.

[0197] In the cross-sectional view, the first groove GRV1 can be formed such that its maximum width w2 is greater than the width w1 of the first separating opening SP-OP1. Therefore, a portion of the pixel defining layer PDL can protrude in a direction toward the center of the first groove GRV1. That is, a portion of the pixel defining layer PDL can overlap with the first groove GRV1 in the plan view. In this case, the protruding portion of the pixel defining layer PDL can define the first tip TIP1.

[0198] In the cross-sectional view, the second groove GRV2 can be formed such that its maximum width w4 is greater than the width w3 of the second separating opening SP-OP2. Therefore, a portion of the pixel defining layer PDL can protrude in a direction away from the first groove GRV1. That is, a portion of the pixel defining layer PDL can overlap with the second groove GRV2 in the plan view. In this case, the protruding portion of the pixel defining layer PDL can define the second tip TIP2. Another portion of the pixel defining layer PDL can protrude in a direction toward the center of the first groove GRV1. That is, another portion of the pixel defining layer PDL can overlap with the second groove GRV2 in the plan view. In this case, the other protruding portion of the pixel defining layer PDL can define the third tip TIP3.

[0199] like Figure 10C As shown, the manufacturing of the display panel DP according to an embodiment (see Figure 10G The method may include the operation of forming spacer SPC.

[0200] At least a portion of the spacer SPC can be arranged and formed inside the first partition opening SP-OP1 and the first groove GRV1. The spacer SPC may include a first portion P1 disposed in the first groove TRC1 and a second portion P2 extending from the first portion P1 and protruding in a direction away from the first partition opening SP-OP1.

[0201] The first portion P1 of the spacer SPC can contact the first tip TIP1. Since a portion of the spacer SPC is disposed inside the first trench TRC1, the area in which the spacer SPC contacts the sixth insulating layer 60 and the pixel defining layer PDL can be increased, and the adhesion of the spacer SPC can be improved. Therefore, the spacer SPC can be disposed with a reduced width.

[0202] like Figure 10C and Figure 10D As shown, the manufacturing of the display panel DP according to an embodiment (see Figure 10G The method may include etching an initial sacrificial pattern SP-I to form a sacrificial pattern SP. In an embodiment, during the etching of the initial sacrificial pattern SP-I, a sacrificial opening S-OP may be formed in the initial sacrificial pattern SP-I using a pixel defining layer PDL as a mask. That is, the sacrificial pattern SP, in which the sacrificial opening S-OP is defined, can be formed by etching the initial sacrificial pattern SP-I. At least a portion of the first electrode AE ​​can be exposed from the sacrificial pattern SP and the pixel defining layer PDL through the sacrificial opening S-OP and the light-emitting opening PDL-OP.

[0203] In this embodiment, the process of etching the sacrificial pattern SP can be performed using a wet etching method.

[0204] The sacrificial pattern SP can be set to multiple sacrificial patterns SP. Figure 10D An example is shown where the setup consists of a first initial sacrificial pattern SP-I1 (see...). Figure 10C The first sacrificial pattern SP1 formed by the second initial sacrificial pattern SP-I2 (see...) Figure 10C The second sacrificial pattern SP2 is formed.

[0205] More specifically, the portion of the first initial sacrificial pattern SP-I1 exposed from the pixel-defining layer PDL through the first light-emitting opening PDL-OP1 can be removed, thus forming a first sacrificial opening S-OP1 corresponding to the first light-emitting opening PDL-OP1 in the first initial sacrificial pattern SP-I1. Therefore, a first sacrificial pattern SP1 in which the first sacrificial opening S-OP1 is defined can be formed from the first initial sacrificial pattern SP-I1.

[0206] The portion of the second initial sacrificial pattern SP-I2 exposed from the pixel-defining layer PDL through the second light-emitting opening PDL-OP2 can be removed, thus forming a second sacrificial opening S-OP2 corresponding to the second light-emitting opening PDL-OP2 in the second initial sacrificial pattern SP-I2. Therefore, a second sacrificial pattern SP2 in which the second sacrificial opening S-OP2 is defined can be formed from the second initial sacrificial pattern SP-I2.

[0207] The process of etching the sacrificial pattern SP can be performed in an environment with high etch selectivity between the sacrificial pattern SP and the first electrode AE, thus preventing the first electrode AE ​​from being etched together. In other words, by setting a sacrificial pattern SP with an etch rate greater than that of the first electrode AE ​​between the pixel defining layer PDL and the first electrode AE, the first electrode AE ​​can be prevented from being etched and damaged together during the etching process.

[0208] The method for manufacturing a display panel DP may also include performing a heat treatment operation after the etching of the sacrificial pattern SP. Performing the heat treatment operation after the etching of the sacrificial pattern SP allows for easy removal of gases generated from the organic layer (e.g., the sixth insulating layer 60) disposed beneath the first electrode AE. Therefore, in manufacturing a display panel DP (see...),... Figure 10G In the process of manufacturing ED (Electronic Light Emitting Device), sufficient discharge can be achieved. Figure 10E The gas in the organic layer below can be reduced after manufacturing, thus lowering the emission level of the light-emitting element (ED). Figure 10E The rate of degradation. In this case, the gas in the organic layer can be more easily discharged through the first separation opening SP-OP1 and the second separation opening SP-OP2 formed in the pixel-defined layer PDL.

[0209] like Figure 10E The manufacturing process of the display panel DP according to an embodiment is shown in the figure. Figure 10G The method may include operations such as forming a light-emitting layer (EML) and a second electrode (CE), as well as operations such as forming an inorganic encapsulation film 141. Therefore, a display layer (DPL) can be completed.

[0210] First, in the operation of forming the light-emitting layer EML and the second electrode CE, the light-emitting layer EML and the second electrode CE can be sequentially arranged on the first electrode AE ​​to form the light-emitting element ED.

[0211] Each of the operations of forming the light-emitting layer (EML) and forming the second electrode (CE) can be performed by a deposition process. In an embodiment, the operation of forming the EML can be performed by a thermal evaporation process, and the operation of forming the second electrode (CE) can be performed by a CVD process. However, this disclosure is not limited thereto.

[0212] The light-emitting element (ED) can be set to multiple light-emitting elements (ED). Figure 10E An exemplary illustration shows a first light-emitting element ED1 comprising a first electrode AE, a first light-emitting layer EML1, and a second electrode CE, and a second light-emitting element ED2 comprising a first electrode AE, a second light-emitting layer EML2, and a second electrode CE.

[0213] During the formation of the second electrode CE, a dummy pattern DPA, separated from the second electrode CE, can be formed simultaneously. The dummy pattern DPA may include a first dummy pattern DPA1 and a second dummy pattern DPA2. The first dummy pattern DPA1 and the second dummy pattern DPA2 can be partially separated during the formation of the second electrode CE by a second tip TIP2 and a third tip TIP3 formed on the pixel defining layer PDL, and therefore can be formed simultaneously. The first dummy pattern DPA1 can be formed inside the second recess GRV2. The second dummy pattern DPA2 can be disposed on the pixel defining layer PDL and can cover the spacer SPC.

[0214] Subsequently, in the process of forming the inorganic encapsulation film 141, the inorganic encapsulation film 141 can be formed by a deposition process. In embodiments, the inorganic encapsulation film 141 may include inorganic materials, and may include, for example, silicon nitride (SiN). x For example, inorganic encapsulation films 141 can be formed by CVD and / or ALD processes.

[0215] like Figure 10F As shown, the manufacturing of the display panel DP according to an embodiment (see Figure 10G The method may include the operation of forming an anti-reflective layer (ARL).

[0216] The anti-reflective layer ARL may include a color filter layer CF and an outer coating OC. The color filter layer CF can be directly disposed and formed on the display layer DPL. That is, the color filter layer CF can be directly disposed on the inorganic encapsulation film 141. Therefore, the color filter layer CF can cover the second electrode CE of the light-emitting element ED. Thus, the reflection of external light caused by the electrodes in the display layer DPL can be effectively reduced or prevented.

[0217] In embodiments of this disclosure, at least a portion of the first color filter CF1 to the third color filters CF2 and CF3 may be independent of the first light-emitting region to the third light-emitting region LA1, LA2 and LA3 (see...). Figure 5In other words, at least portions of the first to third color filters CF1, CF2, and CF3 can be arranged in a stacked manner on the third-direction DR3 in the region superimposed with the non-emitting region NLA. The first to third color filters CF1, CF2, and CF3, stacked on each other in the thickness direction (i.e., the third-direction DR3), can block light passing through the non-emitting region NLA to prevent light from passing through the first to third emitting regions LA1, LA2, and LA3 (see Figure 5 The color mixing between the filters. However, the embodiments are not limited to this. In another embodiment, the first to third color filters CF1, CF2 and CF3 may not be arranged to overlap each other in the thickness direction in the plan view.

[0218] In an embodiment, an outer coating OC may be provided, which can protect the light-emitting element layer 130 from foreign objects penetrating the anti-reflective layer ARL and supply power to the input sensor layer ISL (see...). Figure 10G It provides a flat surface.

[0219] The outer coating OC can be formed by coating or deposition processes. More specifically, the outer coating OC can be formed by forming an organic layer via methods such as coating and deposition, and then selectively patterning the organic layer by photolithography and etching. In this case, a higher level of flatness can be maintained at its edges, and a smaller thickness can be provided compared to the case where the organic layer is formed by inkjet processes. Therefore, the difference between the light-emitting element ED and the input sensor layer ISL (see...) can be effectively reduced. Figure 10G The light-shielding layer 200-SDL in ) (see Figure 10G The distance between them can effectively widen the field of view.

[0220] like Figure 10G As shown, the method for manufacturing a display panel DP according to an embodiment may include forming an input sensor layer ISL. The input sensor layer ISL can be formed directly on the anti-reflective layer ARL. That is, the input sensor layer ISL can be formed directly on the outer coating OC.

[0221] The input sensor layer ISL may include a first sensing insulating layer 200-IL1, a first conductive layer 200-CL1, a second sensing insulating layer 200-IL2, a second conductive layer 200-CL2, and a third sensing insulating layer 200-IL3. The first sensing insulating layer 200-IL1 can be directly disposed on the outer coating OC. In an embodiment, the input sensor layer ISL may further include a light-shielding layer 200-SDL disposed between the second sensing insulating layer 200-IL2 and the third sensing insulating layer 200-IL3 and covering the second conductive layer 200-CL2.

[0222] The input sensor layer (ISL) can be formed by manufacturing processes such as coating and deposition to form insulating and conductive layers, selectively patterning the insulating and conductive layers and forming conductive patterns (e.g., sensing patterns or bridging patterns with a mesh structure) through photolithography and etching processes.

[0223] Therefore, a display panel DP can be formed, which includes a display layer DPL, an anti-reflective layer ARL, and an input sensor layer ISL.

[0224] According to this disclosure, since grooves (or overhang structures) are provided near the spacers, the occurrence of defects in the light-emitting elements can be effectively reduced or prevented even when foreign matter remains in the spacers or the spacers are damaged by scratches on the metal mask. Therefore, a display device with improved display quality can be provided.

[0225] According to this disclosure, an anti-reflective layer (e.g., a color filter layer) can be directly disposed on the display layer, thereby reducing or preventing the reflection of external light caused by electrodes in the display layer. Furthermore, the distance between the display layer and the light-shielding layer can be effectively reduced, and the viewing angle can be effectively widened. Therefore, a display device with improved display quality can be provided.

[0226] While embodiments of this disclosure have been described above with reference to them, it is understood that various modifications and alterations can be made to this disclosure by those skilled in the art or those with ordinary knowledge in the art without departing from the spirit and scope of this disclosure as set forth in the appended claims. Therefore, the scope of this disclosure is not limited to the detailed description in the specification, but should be defined by the appended claims.

Claims

1. A display device, characterized in that, The display device includes: An insulating layer, a first groove, and a second groove surrounding the first groove are defined in the insulating layer; A pixel defining layer is disposed on the insulating layer, and a light-emitting opening, a first dividing opening superimposed on the first groove, and a second dividing opening superimposed on the second groove and surrounding the first dividing opening are defined in the pixel defining layer; A light-emitting element is disposed on the insulating layer and includes a first electrode, a second electrode, and a light-emitting layer. At least a portion of the first electrode is exposed through the light-emitting opening. The second electrode is disposed on the first electrode. The light-emitting layer is disposed between the first electrode and the second electrode and is superimposed on the light-emitting opening. A spacer, at least a portion of which is disposed inside the first groove and the first dividing opening; An inorganic encapsulation film is disposed on the second electrode and the spacer; and The color filter layer is directly disposed on the inorganic encapsulation film.

2. The display device according to claim 1, characterized in that, The first tip of the pixel defining layer protrudes from the first inner surface of the insulating layer defining the first groove in a direction toward the center of the first groove.

3. The display device according to claim 2, characterized in that, The spacer contacts the first tip.

4. The display device according to claim 1, characterized in that, The spacer includes: The first part is disposed inside the first groove and the first dividing opening; and The second part extends from the first part and protrudes in a direction away from the first dividing opening.

5. The display device according to claim 1, characterized in that, The second tip of the pixel defining layer protrudes from the second inner surface of the insulating layer defining the second groove in a direction away from the center of the first groove, and The third tip of the pixel defining layer protrudes from the third inner surface of the insulating layer in a direction toward the center of the first groove, the third inner surface facing and surrounding the second inner surface and defining the second groove.

6. The display device according to claim 1, characterized in that, The inorganic encapsulation film contacts the inner surface of the pixel defining layer that defines the second separation opening.

7. The display device according to claim 1, characterized in that, The display device further includes: A dummy pattern is disposed in the second groove, separated from the second electrode, and made of the same material as the second electrode.

8. The display device according to claim 1, characterized in that, The light-emitting element is configured as a plurality of light-emitting elements, including a first light-emitting element, a second light-emitting element, and a third light-emitting element. A first light-emitting region configured to emit light of a first color is defined in the first light-emitting element; a second light-emitting region configured to emit light of a second color different from the first color is defined in the second light-emitting element; and a third light-emitting region configured to emit light of a third color different from both the first and second colors is defined in the third light-emitting element. The light-emitting opening is configured as a plurality of light-emitting openings, including a first light-emitting opening superimposed on the first light-emitting region, a second light-emitting opening superimposed on the second light-emitting region, and a third light-emitting opening superimposed on the third light-emitting region. The color filter layer includes a first color filter, a second color filter, and a third color filter. At least a portion of the first color filter is superimposed on the first light-emitting area, at least a portion of the second color filter is superimposed on the second light-emitting area, and at least a portion of the third color filter is superimposed on the third light-emitting area.

9. The display device according to claim 8, characterized in that, At least a portion of the first to the third color filters are superimposed on each other in areas that do not overlap with any of the first to the third light-emitting regions.

10. The display device according to claim 8, characterized in that, The portions of the first to the third color filters are arranged inside the second groove and the second partition opening.

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