Display device and head-mounted display device

Abstract

A display device and a head-mounted display device including the same are provided. The display device includes: a first single crystal semiconductor substrate in which a plurality of first transistors are formed; a second single crystal semiconductor substrate on the first single crystal semiconductor substrate, and a display element layer including a plurality of light emitting elements on the second single crystal semiconductor substrate; a connection wiring layer between the first single crystal semiconductor substrate and the second single crystal semiconductor substrate; a plurality of through holes in the second single crystal semiconductor substrate and in which vias connected to connection lines connecting the wiring layer are located; a plurality of bonding pads on the first single crystal semiconductor substrate, the plurality of bonding pads being connected to the connecting lines and spaced apart from each other; and a heating wire around the plurality of bonding pads, each of both ends of the heating wire being connected to the heating contact portion. In the display device, damage to a light emitting element due to heat treatment is reduced.

Description

Technical Field

[0001] One or more aspects of this disclosure relate to a display device, a method of manufacturing the display device, and a head-mounted display device. Background Technology

[0002] A head-mounted display (HMD) is an image display device worn on a user's head in the form of glasses or a helmet, designed to focus on an image at close range in front of the user's eyes. HMDs can enable virtual reality (VR) and / or augmented reality (AR).

[0003] Head-mounted display devices magnify images displayed on a small display using multiple lenses and then display the magnified images. Therefore, display devices used in head-mounted displays need to provide high-resolution images, for example, images with a resolution of 3000 PPI (pixels per inch) or higher. For this purpose, organic light-emitting diodes on silicon (OLEDoS), as high-resolution small organic light-emitting display devices, are used in head-mounted displays. OLEDoS is an image display device in which organic light-emitting diodes (OLEDs) are disposed on a semiconductor wafer substrate on which complementary metal-oxide-semiconductor (CMOS) is disposed.

[0004] The information disclosed in this background section is intended to enhance the understanding of the background of this disclosure, and therefore may contain information that does not constitute prior art. Utility Model Content

[0005] The purpose of this invention is to provide a microdisplay device comprising multiple different single-crystal semiconductor substrates and a head-mounted display device including the microdisplay device.

[0006] Embodiments of this disclosure relate to a microdisplay device and a method of manufacturing the microdisplay device, the microdisplay device including a heating wire capable of transferring heat in a bonding process in which two different semiconductor substrates are connected to each other.

[0007] However, the aspects and features of embodiments of this disclosure are not limited to those set forth herein. These and other aspects and features of this disclosure will become more apparent to those skilled in the art from the following detailed description of the disclosure given with reference to the accompanying drawings.

[0008] According to one or more embodiments of the present disclosure, a display device includes: a first single-crystal semiconductor substrate in which a plurality of first transistors are formed; a second single-crystal semiconductor substrate on which a display element layer including a plurality of light-emitting elements is located; a connection wiring layer between the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate; a plurality of vias in which vias connected to connection lines of the connection wiring layer are located; a plurality of bonding pads on which the plurality of bonding pads are connected to connection lines of the connection wiring layer and spaced apart from each other; and heating wires around the plurality of bonding pads, each of the two ends of the heating wires being connected to a heating contact portion.

[0009] The heating wire is not stacked with multiple bonding pads.

[0010] The heating wires bypass the bonding pads and surround at least a portion of the plurality of bonding pads.

[0011] The heating wires consist of multiple heating wires, and the multiple heating wires are separated from multiple bonding pads.

[0012] The heating wire is stacked with multiple bonding pads.

[0013] The heating wire has a plate shape and a width greater than the width of the multiple bonding pads.

[0014] The heating wire has a shape that extends in one direction and is positioned across multiple bonding pads.

[0015] The display device further includes at least one semiconductor insulating layer on a first single-crystal semiconductor substrate, wherein a plurality of bonding pads are on at least one semiconductor insulating layer.

[0016] At least one semiconductor insulating layer comprises a plurality of semiconductor insulating layers, wherein the heating wire is located between the plurality of semiconductor insulating layers.

[0017] The heating wire is in the first single-crystal semiconductor substrate.

[0018] The heating wire is on at least one semiconductor insulating layer and is on the same layer as multiple bonding pads.

[0019] The heating contact portion is connected to the heating wire without being covered by at least one semiconductor insulating layer.

[0020] The number of bonding pads is equal to the number of vias in the second single-crystal semiconductor substrate.

[0021] Multiple through holes are not stacked with multiple light-emitting elements.

[0022] A plurality of second transistors electrically connected to a plurality of light-emitting elements are formed in a first single-crystal semiconductor substrate, wherein some of the plurality of vias are stacked with the plurality of light-emitting elements, and wherein the number of the plurality of bonding pads is greater than the number of the plurality of vias stacked with the plurality of light-emitting elements.

[0023] The display device further includes a passivation layer surrounding the first single-crystal semiconductor substrate and stacked with the second single-crystal semiconductor substrate.

[0024] In the planar diagram, the area of ​​the first single-crystal semiconductor substrate is smaller than the area of ​​the second single-crystal semiconductor substrate.

[0025] The display device further includes: a plurality of second transistors formed in a second single-crystal semiconductor substrate; and a plurality of signal lines on the second single-crystal semiconductor substrate, which are electrically connected to the first transistors through vias in a plurality of through holes.

[0026] The minimum linewidth of the first transistor is less than 100 nm, and the minimum linewidth of the second transistor among the plurality of second transistors is greater than or equal to 100 nm.

[0027] According to one or more embodiments, a head-mounted display device includes: a frame mounted on a user's body and corresponding to a left eye and a right eye; a plurality of display devices in the frame; and lenses on each of the plurality of display devices, wherein each of the plurality of display devices includes: a first single-crystal semiconductor substrate in which a plurality of first transistors are formed; a second single-crystal semiconductor substrate on which a display element layer including a plurality of light-emitting elements is located; a connection wiring layer between the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate; a plurality of vias in which vias connected to connection lines of the connection wiring layer are located; a plurality of bonding pads on which the plurality of bonding pads are connected to connection lines of the connection wiring layer and spaced apart from each other; and heating wires around the plurality of bonding pads, each of the two ends of the heating wires being connected to a heating contact portion.

[0028] A display device according to one or more embodiments may include: two different single-crystal semiconductor substrates; and a heating wire used in a bonding process in which the two different single-crystal semiconductor substrates are joined together. In the display device, when two different single-crystal semiconductor substrates are joined together, the bonding process can be performed by locally transferring heat to the bonding pads, and damage to the light-emitting elements due to heat treatment can be reduced.

[0029] However, the aspects and features of this disclosure are not limited to those described above, and various other aspects and features are incorporated herein. Attached Figure Description

[0030] The above and other aspects and features of this disclosure will become clearer from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings, in which:

[0031] Figure 1 It is an exploded perspective view of a display device according to one or more embodiments;

[0032] Figure 2 It is shown Figure 1 A plan view of an example of the drive unit shown;

[0033] Figure 3 It is shown Figure 1 A floor plan view of an example of the display unit shown;

[0034] Figure 4 It shows the setting Figure 3 A plan view showing the arrangement of multiple wirings in the display unit;

[0035] Figure 5 This is a block diagram illustrating a display device according to one or more embodiments;

[0036] Figure 6 It is an equivalent circuit diagram of a pixel according to one or more embodiments;

[0037] Figure 7 This is a schematic cross-sectional view of a display device according to one or more embodiments;

[0038] Figure 8 This is a schematic diagram showing the rear surface of a display device according to one or more embodiments;

[0039] Figure 9 This is a schematic cross-sectional view of a drive unit according to one or more embodiments;

[0040] Figure 10 This is a plan view showing a pixel-defining film, a first electrode, and a light-emitting area disposed in a display area of ​​a display unit according to one or more embodiments;

[0041] Figure 11 This is a plan view showing a pixel-defining film, a first electrode, and a light-emitting area disposed in a display area of ​​a display unit according to one or more embodiments;

[0042] Figures 12 to 14 It is a cross-sectional view showing a portion of the display area and a portion of the non-display area in a display unit according to one or more embodiments;

[0043] Figure 15This is a plan view showing the arrangement of signal terminals and heating wires disposed on a first single-crystal semiconductor substrate according to one or more embodiments;

[0044] Figure 16 It is along Figure 15 A sectional view taken by line A1-A1' in the diagram;

[0045] Figure 17 This is a schematic diagram illustrating the bonding process of the driving unit and the display unit during the manufacturing process of the display device according to one or more embodiments;

[0046] Figure 18A and Figure 18B This is a cross-sectional view showing the arrangement of heating wires of a display device according to one or more embodiments;

[0047] Figures 19 to 23 This is a plan view showing the arrangement of heating wires of a display device according to one or more embodiments;

[0048] Figure 24 This is a plan view illustrating an example of a driving unit of a display device according to one or more embodiments;

[0049] Figure 25 It is shown Figure 24 A plan view of an example display unit of a display device;

[0050] Figure 26 yes Figure 24 and Figure 25 A schematic cross-sectional view of the display device;

[0051] Figure 27 It is shown Figure 24 and Figure 25 A schematic diagram of the rear surface of the display device;

[0052] Figure 28 and Figure 29 This is a schematic cross-sectional view of a display device according to one or more embodiments;

[0053] Figure 30 This is a perspective view showing a head-mounted display device according to one or more embodiments;

[0054] Figure 31 It is shown Figure 30 An exploded perspective view of an example of a head-mounted display device; and

[0055] Figure 32 This is a perspective view showing a head-mounted display device according to one or more embodiments. Detailed Implementation

[0056] The aspects and features of embodiments of this disclosure, as well as methods of implementing them, can be more readily understood by referring to the detailed description of the embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of this disclosure to those skilled in the art. Therefore, processes, elements, and techniques unnecessary for those skilled in the art to fully understand the aspects and features of this disclosure are not described.

[0057] Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description, and therefore their description will not be repeated. Furthermore, components unrelated to the description of one or more embodiments may be omitted for clarity.

[0058] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity. Furthermore, crosshairs and / or shading are typically used in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not express or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the elements shown, or any other characteristics, properties, or attributes.

[0059] Various embodiments are described herein with reference to sectional views that serve as schematic illustrations of examples and / or intermediate structures. Thus, variations in the shapes illustrated will be expected due to factors such as manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes specifically shown in the region, but will include shape deviations due to factors such as manufacturing.

[0060] For example, an injection region shown as rectangular may have rounded or curved features at its edges and / or a gradient of injection concentration, rather than a binary change from an injection region to a non-injection region. Similarly, an embedded region formed by injection may result in some injection in the region between the embedded region and the surface through which the injection occurs. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device, nor are they intended to be limiting. Furthermore, as those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing entirely from the scope of this disclosure.

[0061] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various embodiments. However, it will be apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other examples, well-known structures and arrangements are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0062] For ease of explanation, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” may be used herein to describe the relationship of one element or feature to another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below” or “below” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when a first component is described as being arranged “above” a second component, this means that the first component is arranged above or below the second component, not limited to its upper side based on the direction of gravity.

[0063] Furthermore, in this specification, the phrase "in a plane" or "in a plan view" refers to the target portion viewed from above, and the phrase "in a cross section" refers to the cross section formed by vertically cutting the target portion viewed from the side.

[0064] It will be understood that when an element, layer, region, or component is referred to as "formed on," "on," "connected to," or "joined to" another element, layer, region, or component, the element, layer, region, or component may be directly formed on, directly on, directly connected to, or directly joined to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly joined to the other element, layer, region, or component, such that one or more intermediary elements, layers, regions, or components may exist. For example, when a layer, region, or component is referred to as "electrically connected" or "electrically joined" to another layer, region, or component, the layer, region, or component may be directly electrically connected or directly electrically joined to the other layer, region, and / or component, or an intermediary layer, region, or component may exist. However, "direct connection / direct bonding" refers to a component being directly connected to or bonded to another component without any intermediate components. Similarly, expressions describing relationships between components, such as "between," "immediately between," or "adjacent to" and "directly adjacent to," can be interpreted in a similar way. Furthermore, it will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may be one or more intermediary elements or layers.

[0065] For the purposes of this disclosure, when expressions such as “at least one of…”, “one of…”, and “selected from…” precede (or follow) a list of elements, they modify the entire list of elements without modifying individual elements within that list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as XYZ, XYY, XZ, YZ, and ZZ) or any variation thereof. Similarly, expressions such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, expressions such as “A and / or B” can include A, B, or A and B. Furthermore, the use of “may” in describing embodiments of this disclosure refers to “one or more embodiments of this disclosure”.

[0066] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the scope of this disclosure, the first element, first component, first region, first layer, or first portion described below may be referred to as a second element, second component, second region, second layer, or second portion.

[0067] In the example, the x, y, and / or z directions are not limited to directions corresponding to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x, y, and z directions can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first, second, and / or third directions.

[0068] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms as well. It will also be understood that when the terms “comprising” and variations thereof, “having” and variations thereof, “including” and variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0069] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. As used herein, “about” or “approximately” includes the stated value and means: within an acceptable deviation of the specific value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, in describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.”

[0070] When one or more embodiments can be implemented differently, a particular process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0071] Furthermore, any numerical ranges disclosed and / or enumerated herein are intended to include all subranges containing the same numerical precision within the enumerated ranges. For example, the range “1.0 to 10.0” is intended to include all subranges between (and including) the enumerated minimum value of 1.0 and the enumerated maximum value of 10.0, such as having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, as exemplified by 2.4 to 7.6. Any maximum numerical limit enumerated herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit enumerated in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly enumerate any subranges contained within the ranges expressly enumerated herein.

[0072] Electronic devices or electrical devices and / or any other related devices or components according to one or more embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on an integrated circuit (IC) chip or a separate IC chip. Furthermore, various components of these devices can be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0073] Furthermore, the various components of these devices can be processes or threads running on one or more processors, executing computer program instructions and interacting with other system components for performing the various functions described herein, within one or more computing devices. The computer program instructions are stored in memory, which can be implemented in the computing device using standard memory devices, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Moreover, those skilled in the art will recognize that, without departing from the scope of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0074] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant field and / or in this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0075] Those skilled in the art will understand that, in view of the overall content of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with one another, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of one another or in any suitable combination with one another.

[0076] Figure 1 It is an exploded perspective view of a display device according to one or more embodiments.

[0077] Reference Figure 1 The display device 10 according to one or more embodiments is a means for displaying moving images and / or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices (such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, ultra-mobile PCs (UMPCs), etc.). For example, the display device 10 can be applied as a display unit in televisions, laptop computers, monitors, billboards, and / or Internet of Things (IoT) devices. Optionally, the display device 10 can be applied to smartwatches, smartwatch phones, head-mounted displays (HMDs) for realizing virtual and augmented reality, etc.

[0078] The display device 10 according to one or more embodiments may include a driving unit 100, a display unit 200, and a circuit board 300. The display device 10 may also include a passivation layer 900 disposed around the driving unit 100.

[0079] The drive unit 100 may have a planar shape similar to a quadrilateral. For example, the drive unit 100 may have a planar shape similar to a rectangle, having one side in a first direction DR1 and another side in a second direction DR2 intersecting the first direction DR1. The drive unit 100 may have different lengths on one side in the first direction DR1 and the other side in the second direction DR2. In the drive unit 100, the corner where the one side in the first direction DR1 and the other side in the second direction DR2 intersect may be a right angle or a rounded corner with a suitable curvature (e.g., a predetermined curvature). The planar shape of the drive unit 100 is not limited to a quadrilateral shape, but may be a shape similar to another polygonal shape, a circular shape, and / or an elliptical shape.

[0080] The display unit 200 may be disposed on the driving unit 100. In the display device 10, the driving unit 100 and the display unit 200 may be coupled to each other. Unlike the driving unit 100, the display unit 200 may have a shape similar to a square. For example, the display unit 200 may have a planar shape similar to a square having the same length on one side in the first direction DR1 and on the other side in the second direction DR2 intersecting the first direction DR1. The planar shape of the display unit 200 is not limited to a square, and may be a shape similar to another polygonal shape, a circular shape, and / or an elliptical shape. The planar shape of the display device 10 may conform to the planar shape of the display unit 200, but is not limited thereto.

[0081] According to one or more embodiments, in the display device 10, the area of ​​the display unit 200 in a plan view may be larger than the area of ​​the driving unit 100 in a plan view. The display device 10 may include the driving unit 100 and the display unit 200 with different substrates, and the driving unit 100 and the display unit 200 may have different areas. The elements formed in the driving unit 100 and the elements formed in the display unit 200 may be different, and these elements may be formed individually on different substrates. The display device 10 can be manufactured by forming multiple elements with different sizes, linewidths and manufacturing processes on different substrates and then joining them together, which may have the advantages of improved product performance and manufacturing yield.

[0082] Circuit board 300 can be electrically connected to multiple pads in the pad (also known as "solder pad" or "soldering pad") area of ​​display unit 200 using conductive adhesive members such as anisotropic conductive film. Circuit board 300 can be a flexible printed circuit board (FPCB) and / or flexible film made of flexible material. Although circuit board 300 is in Figure 1 The circuit board 300 is shown unfolded, but it can be bent. In this case, one end of the circuit board 300 can be disposed on the bottom surface of the drive unit 100. The other end of the circuit board 300 can be connected to a plurality of pads in the pad area of ​​the display unit 200 using conductive adhesive members. In another embodiment, the circuit board 300 can be attached to the bottom surface of the drive unit 100.

[0083] The passivation layer 900 may be disposed on the bottom surface of the display unit 200 and around the driving unit 100 (e.g., surrounding the driving unit 100). The passivation layer 900 may reduce the horizontal difference caused by the area difference between the driving unit 100 and the display unit 200, and may also protect the driving unit 100 and the display unit 200.

[0084] Figure 2 It is shown Figure 1A plan view of an example of a drive unit shown. Figure 3 It is shown Figure 1 A floor plan of an example of a display unit shown. Figure 4 It shows the setting Figure 3 A plan view showing the arrangement of multiple wirings in the display unit.

[0085] Reference Figures 2 to 4 The driving unit 100 of the display device 10 may include driving circuit elements of the display device 10. The driving unit 100 may include a first single-crystal semiconductor substrate 110 and a timing control circuit (i.e., timing controller) 400, a gate driver 600, and a data driver 700 formed on the first single-crystal semiconductor substrate 110. The gate driver 600 may include a scan driver 610 and an emitter driver 620.

[0086] The first single-crystal semiconductor substrate 110 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. A plurality of first transistors may be formed in the first single-crystal semiconductor substrate 110. The plurality of first transistors may be electrically connected to each other and constitute a timing control circuit 400, gate drivers 610 and 620, and a data driver 700. The first transistors may be formed using semiconductor processes. For example, the plurality of transistors may be formed as complementary metal-oxide-semiconductor (CMOS) transistors.

[0087] In the accompanying drawings, a data driver 700 is shown positioned above the driving unit 100, a signal terminal area TDA is positioned below it, a timing control circuit 400 is positioned between the data driver 700 and the signal terminal area TDA, and a gate driver 600 is positioned on both sides of the timing control circuit 400 in the first direction DR1. A scan driver 610 may be positioned to the left of the timing control circuit 400, and a transmit driver 620 may be positioned to the right of the timing control circuit 400. However, this disclosure is not limited thereto. The positions of the timing control circuit 400, the gate driver 600, and the data driver 700 in the driving unit 100 can vary depending on the design structure of the plurality of circuit elements formed on the first single-crystal semiconductor substrate 110.

[0088] Multiple signal terminals TPDs arranged along the first direction DR1 can be disposed in the signal terminal area TDA. The multiple signal terminals TPDs can be electrically connected to the display unit 200 and can be electrically connected to the circuit board 300 via them. The signal terminals TPDs can transmit electrical signals applied from the circuit board 300 to the timing control circuit 400, the gate driver 600, the data driver 700, and the pixel circuit layer 220 (see...). Figure 7 ).

[0089] The display unit 200 may include a second single-crystal semiconductor substrate 210 and a pixel circuit layer 220 and a display layer 230 formed on the second single-crystal semiconductor substrate 210 (see...). Figure 7 The display unit 200 may include a display area DAA with multiple pixels PX and a non-display area NA surrounding the display area DAA (e.g., around the display area DAA) along its edge or periphery. Through-hole areas TSA1, TSA2, TSA3, and TSA4, and a pad area PDA may be disposed in the non-display area NA.

[0090] The second single-crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. Multiple second transistors may be formed in the second single-crystal semiconductor substrate 210, and these second transistors may be electrically connected to each other to form a pixel circuit PXC for light emission from multiple pixels PX. The second transistors may be formed using semiconductor processes. For example, the multiple transistors may be formed as complementary metal-oxide-semiconductor (CMOS) transistors.

[0091] Multiple pixels PX, including light-emitting elements, can be disposed in a display area DAA. Each of the multiple pixels PX may include three sub-pixels, for example, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The three sub-pixels SP1, SP2, and SP3 can constitute a pixel PX to display color. However, this disclosure is not limited thereto, and a pixel PX may include three or more sub-pixels. The multiple sub-pixels SP1, SP2, and SP3 may be arranged in a matrix along a first direction DR1 and a second direction DR2. For example, the multiple sub-pixels SP1, SP2, and SP3 may be arranged along the rows and columns of a matrix along the first direction DR1 and the second direction DR2. Each of the multiple sub-pixels SP1, SP2, and SP3 may be electrically connected to a pixel circuit PXC composed of multiple second transistors formed in a second single-crystal semiconductor substrate 210 (e.g., see...). Figure 6 Each of the sub-pixels SP1, SP2, and SP3 may include a light-emitting element, and the light-emitting element may emit light in accordance with an electrical signal applied from the pixel circuit PXC disposed in the display area DAA.

[0092] Some of the sub-pixels SP1, SP2, and SP3 disposed in the display area DAA of the display unit 200 may be superimposed on the driving unit 100 in the thickness direction (e.g., third-party direction DR3), while other sub-pixels may not be superimposed on the driving unit 100. The driving unit 100 has an area smaller than that of the display unit 200 and may be configured to be adjacent to one side of the display unit 200. Therefore, only some of the sub-pixels SP1, SP2, and SP3 may be superimposed on the driving unit 100 in the thickness direction (e.g., third-party direction DR3).

[0093] The pixel circuit layer 220 includes a plurality of pixel transistors formed in the second single-crystal semiconductor substrate 210. The plurality of pixel transistors can be formed by semiconductor processes. For example, the plurality of pixel transistors can be formed as CMOS transistors.

[0094] Pixel circuit layer 220 may include a pixel circuit PXC (e.g., see below) consisting of a plurality of pixel transistors and electrically connected to each of the sub-pixels SP1, SP2 and SP3. Figure 6 This includes multiple scan lines GL1 and GL2, and a data line DL. Multiple pixel circuits (PXCs) can be arranged in the second single-crystal semiconductor substrate 210 along a first direction DR1 and a second direction DR2. The arrangement of the pixel circuits (PXCs) can be similar to the arrangement of sub-pixels SP1, SP2, and SP3.

[0095] Multiple scan lines GL1 and GL2 may extend along a first direction DR1 and may be spaced apart from each other along a second direction DR2 (e.g., spaced apart). Multiple data lines DL may extend along the second direction DR2 and may be spaced apart from each other along the first direction DR1 (e.g., spaced apart). Multiple data lines DL may extend from a first via region TSA1 located above the display area DAA. Multiple scan lines GL1 and GL2 may extend from second via regions TSA2 and third via regions TSA3 located to the left and right sides of the display area DAA, respectively. Multiple scan lines GL1 and GL2 may include different types of scan lines, such as first scan lines to third scan lines GWL, GCL, and GBL (see...). Figure 5 ) and transmit control lines EL1 and EL2 (see Figure 5 For example, the first scan line GL1 extending from the second via region TSA2 may include the first scan line to the third scan line GWL, GCL and GBL (see...). Figure 5 The second scan line GL2 extending from the third via region TSA3 may include multiple emission control lines EL1 and EL2 (see...). Figure 5 Multiple scan lines GL1 and GL2, and data lines DL, can be connected to multiple sub-pixels SP1, SP2, and SP3 in the display area DAA. Multiple scan lines GL1 and GL2 can be electrically connected to the gate drivers 610 and 620 of the driving unit 100, and multiple data lines DL can be electrically connected to the data driver 700 of the driving unit 100. The data line DL can be electrically connected to the data driver 700 of the driving unit 100 through a first via TSV1, the first scan line GL1 can be electrically connected to the scan driver 610 through a second via TSV2, and the second scan line GL2 can be electrically connected to the emitter driver 620 through a third via TSV3.

[0096] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be electrically connected to scan lines GL1 and GL2 and data line DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive data voltage from data line DL in response to scan signals from scan lines GL1 and GL2, and emit light from light-emitting element according to data voltage.

[0097] The non-display area NA can be set around the display area DAA (e.g., surrounding the display area DAA). The non-display area NA can be an area without any pixels PX and therefore no light emission. The pad area PDA and multiple vias TSV1, TSV2, TSV3, and TSV4 can be set in the non-display area NA.

[0098] The display device 10 may include a plurality of through-holes TSV1, TSV2, TSV3, and TSV4 forming a path through which components disposed in the driving unit 100 and the display unit 200 are electrically connected to each other. The plurality of through-holes TSV1, TSV2, TSV3, and TSV4 may be formed to penetrate the second single-crystal semiconductor substrate 210 of the display unit 200. The timing control circuit 400, gate drivers 610 and 620, and data driver 700 disposed in the driving unit 100 may be electrically connected to the display unit 200 and the circuit board 300 via connecting lines disposed in the through-holes TSV1, TSV2, TSV3, and TSV4.

[0099] Multiple through holes TSV1, TSV2, TSV3 and TSV4 may include a first through hole TSV1, a second through hole TSV2, a third through hole TSV3 and a fourth through hole TSV4 disposed in the non-display area NA.

[0100] The first through-hole TSV1 can be disposed in the non-display area NA on one side of the display area DAA in the second direction DR2. For example, the first through-hole TSV1 can be disposed in the first through-hole area TSA1 located on the upper side of the display area DAA. The first through-hole TSV1 can be configured to correspond to multiple data lines DL disposed in the display area DAA. The number of first through-hole TSV1s can be equal to the number of data lines DL and the number of pixel columns of multiple sub-pixels SP1, SP2, and SP3 disposed in the display area DAA. Each of the multiple data lines DL can correspond to the first through-hole TSV1 and can be electrically connected to the connecting line disposed in the first through-hole TSV1. Each of the sub-pixels SP1, SP2, and SP3 can receive a data signal from the data line DL of the data driver 700 connected to the drive unit 100 through the first through-hole TSV1.

[0101] The second via TSV2 and the third via TSV3 can be respectively disposed on both sides of the display area DAA in the non-display area NA along the first direction DR1. For example, the second via TSV2 can be disposed in the second via area TSA2 located on the left side of the display area DAA, and the third via TSV3 can be disposed in the third via area TSA3 located on the right side of the display area DAA. The second via TSV2 can be configured to correspond to multiple first scan lines GL1 disposed in the display area DAA, and the third via TSV3 can be configured to correspond to multiple second scan lines GL2 disposed in the display area DAA. The number of second via TSV2s can be the same as the number of first scan lines GL1, and the number of third via TSV3s can be the same as the number of second scan lines GL2. Figure 4 The diagram shows a first scan line GL1 and a second scan line GL2 connected to each of sub-pixels SP1, SP2, and SP3. However, as will be described later, sub-pixels SP1, SP2, and SP3 can each be connected to three first scan lines (e.g., ...). Figure 5 The first to third scan lines (GWL, GCL, and GBL) and two second scan lines (e.g., Figure 5 The first emission control line EL1 and the second emission control line EL2 in the display area DAA). Therefore, the number of second vias TSV2 can be equal to three times the number of pixel rows of multiple sub-pixels SP1, SP2 and SP3 set in the display area DAA, and the number of third vias TSV3 can be equal to twice the number of pixel rows of multiple sub-pixels SP1, SP2 and SP3 set in the display area DAA.

[0102] Each of the plurality of first scan lines GL1 can correspond to a second via TSV2 and can be electrically connected to a connecting line disposed in the second via TSV2. Each of the sub-pixels SP1, SP2, and SP3 can receive a scan signal from the first scan line GL1 of the scan driver 610 connected to the drive unit 100 through the second via TSV2. Each of the plurality of second scan lines GL2 can correspond to a third via TSV3 and can be electrically connected to a connecting line disposed in the third via TSV3. Each of the sub-pixels SP1, SP2, and SP3 can receive a transmission control signal from the second scan line GL2 of the transmission driver 620 connected to the drive unit 100 through the third via TSV3.

[0103] A fourth via TSV4 can be disposed in a fourth via region TSA4 in the non-display area NA. The fourth via region TSA4 can be disposed between the pad region PDA and the display area DAA. The fourth via TSV4 can be a connection path for electrically connecting the signal terminals TPD of the drive unit 100 to the signal connection lines of the circuit board 300. Multiple fourth via TSV4s can be formed to correspond to the signal terminals TPD of the drive unit 100 respectively. In some embodiments, the number of fourth via TSV4s can be equal to the number of signal terminals TPDs, and the fourth via TSV4s can be formed to be stacked with the signal terminals TPDs respectively. However, this disclosure is not limited thereto. The circuit board 300 can be electrically connected to the signal terminals TPD of the drive unit 100 via multiple pads PD and signal connection lines disposed in the fourth via TSV4s.

[0104] The pad area PDA can be disposed on the lower side of the display area DAA, which is located in the second direction DR2. Multiple pad PDs arranged along the first direction DR1 can be disposed within the pad area PDA. The circuit board 300 can be attached to the multiple pad PDs. The pad PDs can be electrically connected to the circuit board 300 and can be used to transmit electrical signals applied from the circuit board 300 to the drive unit 100.

[0105] Figure 5 This is a block diagram illustrating a display device according to one or more embodiments.

[0106] Reference Figure 5 The timing control circuit 400 may include a timing controller. Additionally, the timing control circuit 400 may also include various circuits related to driving the display device 10, such as gamma circuits and logic circuits. The timing control circuit 400 may include driving circuit transistors formed in the first single-crystal semiconductor substrate 110.

[0107] The timing control circuit 400 can receive digital video data DATA and timing signals from an external source. Based on the timing signals, the timing control circuit 400 generates a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display unit 200. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 of the gate driver 600, and can output the transmit timing control signal ECS to the transmit driver 620 of the gate driver 600. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0108] The power supply unit 150 can generate multiple panel driving voltages using an external power supply voltage. For example, the power supply unit 150 can generate a first driving voltage VSS, a second driving voltage VDD, and an initialization voltage VINT, and supply them to multiple pixels PX.

[0109] The scanning timing control signal SCS, the transmission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 can be supplied to multiple pixels PX. The first driving voltage VSS, the second driving voltage VDD, and the initialization voltage VINT of the power supply unit 150 can also be supplied to multiple pixels PX.

[0110] Gate drivers 610 and 620 may include a scan driver 610 and an emitter driver 620. The scan driver 610 may include a plurality of scan transistors formed in the first single-crystal semiconductor substrate 110, and the emitter driver 620 may include a plurality of emitter transistors formed in the first single-crystal semiconductor substrate 110. The plurality of scan transistors and the plurality of emitter transistors may be formed using semiconductor processes. For example, the plurality of scan transistors and the plurality of emitter transistors may be formed as CMOS transistors.

[0111] The scan driver 610 may include a first scan signal output unit 611, a second scan signal output unit 612, and a third scan signal output unit 613. Each of the first scan signal output unit 611, the second scan signal output unit 612, and the third scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The first scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing control circuit 400, and output them sequentially to the first scan line GWL. The second scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS, and output them sequentially to the second scan line GCL. The third scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS, and output them sequentially to the third scan line GBL.

[0112] The transmit driver 620 may include a first transmit signal output unit 621 and a second transmit signal output unit 622. Each of the first transmit signal output unit 621 and the second transmit signal output unit 622 may receive a transmit timing control signal ECS from the timing control circuit 400. The transmit driver 620 may generate transmit control signals according to the transmit timing control signal ECS and output them sequentially to the first transmit control line EL1 and the second transmit control line EL2.

[0113] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0114] Figure 6 It is an equivalent circuit diagram of a pixel according to one or more embodiments.

[0115] Reference Figure 6 The pixel circuits (PXC) of sub-pixels SP1, SP2, and SP3 can be connected to the first scan line GWL, the second scan line GCL, the third scan line GBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Additionally, the pixel circuits (PXC) can be connected to the first driving voltage line VSL to which the first driving voltage VSS (corresponding to a low potential voltage) is applied, the second driving voltage line VDL to which the second driving voltage VDD (corresponding to a high potential voltage) is applied, and the third driving voltage line VIL to which the initialization voltage VINT (corresponding to the initialization voltage) is applied. That is, the first driving voltage line VSL can be a low potential voltage line, the second driving voltage line VDL can be a high potential voltage line, and the third driving voltage line VIL can be an initialization voltage line. In this case, the first driving voltage VSS can be lower than the initialization voltage VINT, and the second driving voltage VDD can be higher than the initialization voltage VINT.

[0116] The pixel circuit PXC of sub-pixels SP1, SP2 and SP3 includes multiple transistors T1 to T6, a light-emitting element LE, a first capacitor C1 and a second capacitor C2.

[0117] The light-emitting element LE emits light in response to a drive current flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE can be proportional to the drive current. The light-emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and its second electrode can be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode (OLED) including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but is not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in this case, the light-emitting element LE can be a micro light-emitting diode.

[0118] The first transistor T1 may be a drive transistor that controls the source-drain current (hereinafter referred to as the "drive current") flowing between its source and drain electrodes according to the voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to the drain electrode of a sixth transistor T6, and a drain electrode connected to a second node N2.

[0119] A second transistor T2 can be disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the first scan line GWL to connect the one electrode of the first capacitor C1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to the one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the first scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the one electrode of the first capacitor C1.

[0120] A third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal from the second scan line GCL to connect the first node N1 to the second node N2. For this purpose, because the gate and drain electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode (e.g., the first transistor T1 can be diode-connected). The third transistor T3 includes a gate electrode connected to the second scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0121] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emitter control signal on the first emitter control line EL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0122] A fifth transistor T5 can be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the third scan line GBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the initialization voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the third scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0123] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by a second emitter control signal on the second emitter control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, a second drive voltage VDD on the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0124] A first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0125] A second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0126] The first node N1 is the junction between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is the junction between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is the junction between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0127] Each of the first transistors T1 to the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 can be a P-type MOSFET, but is not limited thereto. Each of the first transistors T1 to the sixth transistor T6 can be an N-type MOSFET. Optionally, some of the first transistors T1 to the sixth transistor T6 can be P-type MOSFETs, and each of the remaining transistors can be an N-type MOSFET.

[0128] although Figure 6 The pixel circuit PXC shown for sub-pixels SP1, SP2, and SP3 includes six transistors T1 to T6 and two capacitors C1 and C2. However, it should be noted that the equivalent circuit diagram of sub-pixel SP is not limited to... Figure 6 The equivalent circuit diagram is shown. For example, the number of transistors and capacitors in a pixel circuit PXC is not limited to... Figure 6 The example shown.

[0129] Figure 7 It is a schematic cross-sectional view of a display device according to one or more embodiments. Figure 8 This is a schematic diagram showing the rear surface of a display device according to one or more embodiments. Figure 7 The schematic connection relationship of the routing lines RM1, RM2, RM3, and RM4 electrically connecting the display unit 200 to the drive unit 100 is shown. Figure 8 The arrangement of through holes TSV1, TSV2, TSV3 and TSV4, and routing lines RDL, GSL1, GSL2 and SCL, as viewed from the rear of the display device 10, is shown.

[0130] Combination Figure 4 Reference Figure 7 and Figure 8 The display device 10 according to one or more embodiments may include: a driving unit 100, including a first single-crystal semiconductor substrate 110 and a driving circuit layer 120 disposed on the first single-crystal semiconductor substrate 110; and a display unit 200, including a second single-crystal semiconductor substrate 210 and a pixel circuit layer 220 and a display layer 230 disposed on the second single-crystal semiconductor substrate 210. The display device 10 may include two different single-crystal semiconductor substrates 110 and 210 stacked on a third third-direction DR3, which is the thickness direction of the display device 10.

[0131] The driving unit 100 may include circuit elements necessary for light emission of the light-emitting element included in the display layer 230 of the display unit 200. As described above, the driving circuit layer 120 of the driving unit 100 may include a timing control circuit 400, a gate driver 600, and a data driver 700, and the circuit elements constituting them (such as transistors and capacitors) may be formed from CMOS in the first single-crystal semiconductor substrate 110.

[0132] The display unit 200 may include a plurality of light-emitting elements that emit light to display an image of the display device 10. The light-emitting elements may be electrically connected to circuit elements formed in the driving unit 100 to emit light. Additionally, the display unit 200 may include a pixel circuit layer 220, in which circuit elements constituting pixel circuits PXC electrically connected to each of the sub-pixels SP1, SP2, and SP3 are disposed. The pixel circuit layer 220 may include circuit elements constituting the pixel circuits PXC (e.g., ...). Figure 6 The first transistor T1 to the sixth transistor T6 in the display unit 200, multiple scan lines GL1 and GL2, and data lines DL. The pixel circuit layer 220 may also include multiple terminals DTD, GTD1, GTD2, and STD (e.g., see [link to display unit 200]) connected to vias TSV1, TSV2, TSV3, and TSV4 disposed in the non-display area NA of the display unit 200. Figures 12 to 14 ).

[0133] According to one or more embodiments, in the display device 10, in a plan view, the area of ​​the driving unit 100 or the first single-crystal semiconductor substrate 110 may be smaller than the area of ​​the display unit 200 or the second single-crystal semiconductor substrate 210. Multiple transistors formed in the driving unit 100 can be formed using semiconductor microprocessors and therefore can have very small dimensions or linewidths. The driving unit 100 has the advantages of allowing a large number of circuit elements to be arranged with high integration density and reducing power consumption due to the miniaturization of the elements.

[0134] Furthermore, since the driving unit 100 only includes circuit elements formed by CMOS on the first single-crystal semiconductor substrate 110 and does not include light-emitting elements, the driving unit 100 only needs to ensure space within it to accommodate elements formed by microprocessing. Even though the first single-crystal semiconductor substrate 110 has a smaller area than the second single-crystal semiconductor substrate 210, it still functions, and a large number of driving units 100 can be manufactured on a single wafer substrate on which the process for forming the driving circuit layer 120 is performed, thereby improving manufacturing yield. In particular, because the driving unit 100 is manufactured using high-cost semiconductor processes, this improvement in manufacturing yield can lead to cost reduction. Furthermore, in the display unit 200, since a large number of light-emitting elements can be formed on the second single-crystal semiconductor substrate 210, which has a relatively large area, a high-resolution display device can be realized.

[0135] The display device 10 may include a connection wiring layer 500 disposed between the second single-crystal semiconductor substrate 210 of the display unit 200 and the driving circuit layer 120 of the driving unit 100. The connection wiring layer 500 may be disposed on the bottom surface of the second single-crystal semiconductor substrate 210. A portion of a plurality of routing lines RM1, RM2, RM3 and RM4 may be disposed in the connection wiring layer 500, and the routing lines RM1, RM2, RM3 and RM4 may connect the pixel circuit layer 220 of the display unit 200 and the circuit board 300 to the driving unit 100. The driving circuit layer 120 of the driving unit 100 may be electrically connected to the display unit 200 and the circuit board 300 through the routing lines RM1, RM2, RM3 and RM4 of the connection wiring layer 500 to transmit electrical signals for light emission.

[0136] The first routing line RM1 can be connected to the data line DL disposed in the display unit 200 and the data driver 700 disposed in the driving unit 100. The first routing line RM1 can be disposed in the first via TSV1 formed in the second single crystal semiconductor substrate 210, and can include the data routing line RDL connecting the wiring layer 500. A plurality of first via TSV1s can be disposed in the first via region TSA1 of the non-display area NA of the display unit 200, and can not overlap with the driving unit 100 in the thickness direction (e.g., third direction DR3). The first routing line RM1 can be partially disposed in the first via TSV1, the data routing line RDL can be disposed in the connecting wiring layer 500, and the first via TSV1s that do not overlap with the driving unit 100 can be connected to the data driver 700.

[0137] The second routing line RM2 can be connected to the first scan line GL1 or the first scan line to the third scan line GWL, GCL and GBL disposed in the display unit 200 and the scan driver 610 disposed in the driving unit 100. The second routing line RM2 can be disposed in the second via TSV2 formed in the second single crystal semiconductor substrate 210, and can include the first scan routing line GSL1 connecting the wiring layer 500. A plurality of second via TSV2 can be disposed in the second via region TSA2 of the non-display area NA of the display unit 200, and can be not superimposed on the driving unit 100 in the thickness direction. The second routing line RM2 can be partially disposed in the second via TSV2, the first scan routing line GSL1 can be disposed in the connecting wiring layer 500, and the second via TSV2 not superimposed on the driving unit 100 can be connected to the scan driver 610.

[0138] The third routing line RM3 can be connected to the second scan line GL2 or the first emission control line EL1 and the second emission control line EL2 disposed in the display unit 200 and the emission driver 620 disposed in the driving unit 100. The third routing line RM3 can be disposed in the third via TSV3 formed in the second single crystal semiconductor substrate 210 and can include the second scan routing line GSL2 connecting the wiring layer 500. A plurality of third via TSV3s can be disposed in the third via region TSA3 of the non-display area NA of the display unit 200 and can not overlap with the driving unit 100 in the thickness direction (e.g., third direction DR3). The third routing line RM3 can be partially disposed in the third via TSV3, the second scan routing line GSL2 can be disposed in the connecting wiring layer 500, and the third via TSV3s that do not overlap with the driving unit 100 can be connected to the emission driver 620.

[0139] According to one or more embodiments, the number of first vias TSV1 can be equal to the number of pixel columns of multiple sub-pixels SP1, SP2, and SP3 disposed in the display area DAA. For example, multiple sub-pixels SP1, SP2, and SP3 can be arranged in the display area DAA along a first direction DR1 and a second direction DR2. When the number of pixel columns arranged along the first direction DR1 is 4000, the number of first vias TSV1 can also be equal to 4000. The first vias TSV1 can correspond one-to-one with the pixel columns of sub-pixels SP1, SP2, and SP3 arranged along the first direction DR1, and can also correspond one-to-one with multiple data lines DL and first routing lines RM1 arranged along the first direction DR1. A data line DL arranged parallel to a pixel column can be connected to the data driver 700 through a first routing line RM1 disposed in a first via TSV1. The first routing line RM1 and the first vias TSV1 can each be provided in the same number as the number of multiple pixel columns and the number of data lines DL.

[0140] On the other hand, the number of second vias TSV2 and third vias TSV3 can be greater than the number of pixel rows of multiple sub-pixels SP1, SP2, and SP3 disposed in the display area DAA. As described above, since two or more scan lines GL1 and GL2 are disposed in a sub-pixel SP1, SP2, SP3, three second vias TSV2 and two third vias TSV3 can be configured to correspond to one sub-pixel row. However, multiple second vias TSV2 can correspond one-to-one with a second routing line RM2 arranged along the second direction DR2 and multiple first scan lines GL1, and multiple third vias TSV3 can correspond one-to-one with a third routing line RM3 arranged along the second direction DR2 and multiple second scan lines GL2.

[0141] Multiple data lines DL can extend along the second direction DR2 and can be connected to the first via TSV1 in parallel without bending, even in the non-display area NA. Multiple scan lines GL1 and GL2 can extend along the first direction DR1 and can be connected to the second via TSV2 and the third via TSV3 in parallel without bending, even in the non-display area NA. The display device 10 can maintain a constant gap between the signal lines in the display area DAA and the non-display area NA of the display unit 200, and the fan-out structure in which the signal lines bend and narrow in the non-display area NA can be omitted. Similar to the gap between the signal lines, the gap between the first via TSV1, the second via TSV2, and the third via TSV3 can also be constant. However, routing lines (e.g., data routing lines RDL and scan routing lines GSL1 and GSL2) disposed on the rear surface of the display unit 200 can connect the display unit 200 to the drive unit 100 with a small area from the edge of the display unit 200, such that their gap can become smaller when they approach the drive unit 100.

[0142] The fourth routing line RM4 can be connected to the circuit board 300 via a pad PD disposed in the display unit 200, and can also be connected to the signal terminal TPD of the drive unit 100. The fourth routing line RM4 can be disposed in a fourth via TSV4 formed in the second single-crystal semiconductor substrate 210, and can include a signal routing line SCL connecting the wiring layer 500. Multiple fourth via TSV4s can be disposed in the fourth via region TSA4 of the non-display area NA of the display unit 200, and can be non-overlapping with the drive unit 100 in the thickness direction (e.g., third direction DR3). The fourth routing line RM4 can be partially disposed in the fourth via TSV4, the signal routing line SCL can be disposed in the connecting wiring layer 500, and the fourth via TSV4s not overlapping with the drive unit 100 can be connected to the signal terminal TPD. The fourth routing line RM4 can be wiring that transmits signals applied from the circuit board 300 to the drive unit 100.

[0143] Router cables RM1, RM2, RM3, and RM4 may include: connector cables RML1, RML2, RML3, and RML4 (see...) Figures 12 to 14 ), and is provided in the connection wiring layer 500; and conductive vias RVA1, RVA2, RVA3 and RVA4 (see Figures 12 to 14The vias RM1, RM2, RM3, and RM4 are disposed in the second single-crystal semiconductor substrate 210. The routing lines RM1, RM2, RM3, and RM4 are wirings that electrically connect the layers disposed on and below the second single-crystal semiconductor substrate 210, and the arrangement and design of the vias formed in the second single-crystal semiconductor substrate 210 can vary depending on the arrangement of the layers electrically connected to the routing lines RM1, RM2, RM3, and RM4.

[0144] In the following description, the structure of the driving circuit layer 120 of the driving unit 100 and the pixel circuit layer 220 and display layer 230 of the display unit 200 will be described in detail with reference to other accompanying drawings.

[0145] Figure 9 It is a schematic cross-sectional view of a drive unit according to one or more embodiments.

[0146] Reference Figure 9 The driving unit 100 may include a first single-crystal semiconductor substrate 110 and a driving circuit layer 120 disposed thereon. Figure 9 A cross-sectional structure of the data driver 700 disposed in the circuit portion of the drive unit 100 is schematically shown.

[0147] The first single-crystal semiconductor substrate 110 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The first single-crystal semiconductor substrate 110 may be a substrate doped with a first type of impurity. Multiple well regions WA may be disposed on the top surface of the first single-crystal semiconductor substrate 110. The multiple well regions WA may be regions doped with a second type of impurity. The second type of impurity may be different from the aforementioned first type of impurity. For example, when the first type of impurity is a P-type impurity, the second type of impurity may be an N-type impurity. Optionally, when the first type of impurity is an N-type impurity, the second type of impurity may be a P-type impurity.

[0148] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the first transistor PTR1, a drain region DA corresponding to its drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0149] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can also be disposed on the lower insulating film (BINS).

[0150] Each of the source region SA and the drain region DA can be a region doped with a type I impurity. The gate electrode GE of the first transistor PTR1 can be stacked with the well region WA on the third-direction DR3. The channel region CH can be stacked with the gate electrode GE on the third-direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0151] Each of the multiple well regions WA also includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region with a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region with a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The distance between the source region SA and the drain region DA can be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH in each of the first transistor PTR1 can be increased, thereby reducing or preventing punch-through and hot carrier phenomena that may be caused by short channels.

[0152] The first single-crystal semiconductor substrate 110 may include a plurality of first transistors PTR1 constituting a plurality of circuit elements of the driving unit 100. The first transistors PTR1 formed in the first single-crystal semiconductor substrate 110 may constitute a timing control circuit 400 or a data driver 700.

[0153] When the driving circuit layer 120 is formed on a silicon wafer substrate, a process can be performed to reduce the thickness of the first single-crystal semiconductor substrate 110. The first single-crystal semiconductor substrate 110 can have a small thickness compared to the thickness of the wafer substrate to which the semiconductor processes for forming the driving circuit layer 120 are performed. In one or more embodiments, the thickness of the first single-crystal semiconductor substrate 110 can be 100 μm or less, for example, in the range of 80 μm to 100 μm.

[0154] The driving circuit layer 120 may include a first semiconductor insulating layer SINS1, a second semiconductor insulating layer SINS2, a plurality of contact electrodes CTE, a first interlayer insulating layer INS1, a second interlayer insulating layer INS2, a plurality of conductive layers ML1 to ML8, and a plurality of vias VA1 to VA8. The driving circuit layer 120 may include wiring electrically connected to a plurality of first transistors PTR1 included in the first single-crystal semiconductor substrate 110.

[0155] A first semiconductor insulating layer SINS1 and a second semiconductor insulating layer SINS2 can be disposed on a first single-crystal semiconductor substrate 110. The first semiconductor insulating layer SINS1 can be an insulating layer disposed on the first single-crystal semiconductor substrate 110 and the gate electrode GE of the first transistor PTR1, and the second semiconductor insulating layer SINS2 can be an insulating layer disposed on the gate electrode GE of the first transistor PTR1 and the first semiconductor insulating layer SINS1. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 can be made of silicon carbonitride (SiCN) and / or silicon oxide (SiO2).x The formation of an inorganic film is possible, but not limited to, that described above. In the accompanying drawings, the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 are each illustrated as a single layer having a suitable thickness (e.g., a predetermined thickness), but are not limited thereto. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may have a structure in which one or more layers are stacked on top of each other.

[0156] Multiple contact electrodes (CTEs) can be disposed on the first single-crystal semiconductor substrate 110. Each of the multiple contact electrodes (CTEs) can be connected to one of the gate electrode GE, source region SA, and drain region DA of each first transistor PTR1 formed on the first single-crystal semiconductor substrate 110 through a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The multiple contact electrodes (CTEs) can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or alloys including one or more of them. The top surfaces of the multiple contact electrodes (CTEs) can be exposed and not covered by the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2.

[0157] A first interlayer insulating layer INS1 can be disposed on multiple contact electrodes CTEs and a first semiconductor insulating layer SINS1 and a second semiconductor insulating layer SINS2. A second interlayer insulating layer INS2 can be disposed on the first interlayer insulating layer INS1. Each of the first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 can be made of silicon carbonitride (SiCN) and / or silicon oxide (SiO2). x The formation of inorganic films is not limited to this. Although each of the first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 is shown in the figures as a single layer, this disclosure is not limited thereto. Each of the first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 may have a structure in which one or more layers are stacked on top of each other, and may be disposed between a plurality of first conductive layers ML1 to eighth conductive layers ML8, which will be described later.

[0158] The first conductive layers ML1 to the eighth conductive layers ML8 and the first vias VA1 to the eighth vias VA8 can be electrically connected to multiple contact electrodes CTE to form the timing control circuit 400 and / or the data driver 700 of the drive unit 100. Multiple first transistors PTR1 formed in the first single-crystal semiconductor substrate 110 can be electrically connected to each other through the first conductive layers ML1 to the eighth conductive layers ML8 and the first vias VA1 to the eighth vias VA8, and can form the timing control circuit 400 and the data driver 700 of the drive unit 100.

[0159] A first conductive layer ML1 can be connected to the contact electrode CTE via a first via VA1. The first conductive layer ML1 can be disposed above the contact electrode CTE, and the first via VA1 can be disposed between the first conductive layer ML1 and the contact electrode CTE to contact both of them. A second conductive layer ML2 can be connected to the first conductive layer ML1 via a second via VA2. The second conductive layer ML2 can be disposed above the first conductive layer ML1, and the second via VA2 can be disposed between the first conductive layer ML1 and the second conductive layer ML2 to contact both of them.

[0160] The third conductive layer ML3 can be connected to the second conductive layer ML2 through the third via VA3. The fourth conductive layer ML4 can be connected to the third conductive layer ML3 through the fourth via VA4, the fifth conductive layer ML5 can be connected to the fourth conductive layer ML4 through the fifth via VA5, and the sixth conductive layer ML6 can be connected to the fifth conductive layer ML5 through the sixth via VA6. The third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be sequentially disposed above the second conductive layer ML2, and the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be disposed between them. The third via VA3 to the sixth via VA6 can contact different metal layers disposed above and below them, respectively. The seventh via VA7 can be disposed on the sixth conductive layer ML6. The seventh via VA7 can contact the seventh conductive layer ML7 and the sixth conductive layer ML6 disposed thereon.

[0161] The first conductive layers ML1 to the sixth conductive layers ML6 and the first vias VA1 to the seventh vias VA7 can be disposed in the first interlayer insulating layer INS1. The first conductive layers ML1 to the sixth conductive layers ML6 and the first vias VA1 to the seventh vias VA7 can constitute a first driving circuit layer disposed in the first interlayer insulating layer INS1 of the driving circuit layer 120.

[0162] The seventh conductive layer ML7 can be connected to the sixth conductive layer ML6 via the seventh via VA7. The seventh conductive layer ML7 can be disposed above the sixth conductive layer ML6 and the first interlayer insulating layer INS1, and the seventh via VA7 can be disposed between the sixth conductive layer ML6 and the seventh conductive layer ML7 to contact both of them. The eighth conductive layer ML8 can be connected to the seventh conductive layer ML7 via the eighth via VA8. The eighth conductive layer ML8 is disposed above the seventh conductive layer ML7, and the eighth via VA8 can be disposed between the seventh conductive layer ML7 and the eighth conductive layer ML8 to contact both of them. The eighth conductive layer ML8 can have a top surface exposed not covered by the second interlayer insulating layer INS2, and can be electrically connected to the routing line RM disposed in the display unit 200.

[0163] The seventh conductive layer ML7, the eighth via VA8, and the eighth conductive layer ML8 can be disposed in the second interlayer insulating layer INS2. The seventh conductive layer ML7, the eighth via VA8, and the eighth conductive layer ML8 can constitute a second driving circuit layer disposed in the second interlayer insulating layer INS2 of the driving circuit layer 120.

[0164] In the accompanying drawings, although the first conductive layers ML1 to the eighth conductive layers ML8 and the first vias VA1 to the eighth vias VA8 are shown as being stacked sequentially on top of each other, their arrangement and connection can be modified in various ways depending on the timing control circuit 400 of the drive unit 100 and the circuitry of the data driver 700. The connection structure shown in the drawings is merely an example, and the connection of the drive circuit layer 120 provided in the drive unit 100 of the display device 10 is not limited thereto. Furthermore, the drive circuit layer 120 may not necessarily include the first conductive layers ML1 to the eighth conductive layers ML8 and the first vias VA1 to the eighth vias VA8, and some of these layers may be omitted or more layers may be provided.

[0165] The first conductive layers ML1 to the eighth conductive layers ML8 and the first vias VA1 to the eighth vias VA8 can be formed of substantially the same material. For example, the first conductive layers ML1 to the eighth conductive layers ML8 and the first vias VA1 to the eighth vias VA8 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) or alloys including any of them.

[0166] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be approximately 1360 Å. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately 1440 Å. The thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be approximately 1150 Å.

[0167] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately 9000 Å. The thickness of each of the seventh via VA7 and the eighth via VA8 can be approximately 6000 Å.

[0168] Figure 10 This is a plan view illustrating a pixel-defining film of a plurality of sub-pixels disposed in a display area of ​​a display unit, a first electrode, and a light-emitting area, according to one or more embodiments.

[0169] Reference Figure 10 Each of the multiple pixels PX may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first to third sub-pixels SP1, SP2, and SP3 may each include a light-emitting region EA1, EA2, and EA3, respectively. For example, the first sub-pixel SP1 may include a first light-emitting region EA1, the second sub-pixel SP2 may include a second light-emitting region EA2, and the third sub-pixel SP3 may include a third light-emitting region EA3.

[0170] In the planar view, each of the first luminous region EA1, the second luminous region EA2, and the third luminous region EA3 can have a quadrilateral shape such as a rectangle, a square, and / or a rhombus. For example, in the planar view, the third luminous region EA3 can have a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2. Additionally, in the planar view, each of the second luminous region EA2 and the first luminous region EA1 can have a rectangular shape having a long side in the first direction DR1 and a short side in the second direction DR2.

[0171] Each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be a region defined by a pixel-defining film PDL. For example, each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be a region defined by a first pixel-defining film PDL1.

[0172] The length of the third luminous region EA3 in the first direction DR1 can be less than the length of the first luminous region EA1 in the first direction DR1, and can also be less than the length of the second luminous region EA2 in the first direction DR1. The lengths of the first luminous region EA1 and the second luminous region EA2 in the first direction DR1 can be substantially the same.

[0173] In each of the plurality of pixels PX, the first light-emitting region EA1 and the second light-emitting region EA2 may be adjacent to each other in the second direction DR2. Further, the first light-emitting region EA1 and the third light-emitting region EA3 may be adjacent to each other in the first direction DR1. Further, the second light-emitting region EA2 and the third light-emitting region EA3 may be adjacent to each other in the first direction DR1. The areas of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be different.

[0174] Although each of the first luminous region EA1, the second luminous region EA2, and the third luminous region EA3 is shown in the accompanying drawings to have a rectangular shape in a plan view, this disclosure is not limited thereto. For example, in a plan view, each of the first luminous region EA1, the second luminous region EA2, and the third luminous region EA3 may have a polygonal shape other than a quadrilateral shape, a circular shape, or an elliptical shape.

[0175] The first emitting region EA1 can emit light of a first color, the second emitting region EA2 can emit light of a second color, and the third emitting region EA3 can emit light of a third color. Here, the first color of light can be light in the red band, the second color of light can be light in the green band, and the third color of light can be light in the blue band. For example, the blue band can be a band of light whose main peak wavelength is in the range of approximately 370 nm to approximately 460 nm, the green band can be a band of light whose main peak wavelength is in the range of approximately 480 nm to approximately 560 nm, and the red band can be a band of light whose main peak wavelength is in the range of approximately 600 nm to approximately 750 nm.

[0176] The first electrode of the light-emitting element AND (for example, see...) Figure 12The first electrode AND of the light-emitting element can have a rectangular shape in the planar diagram. In the first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3, the planar shape of the first electrode AND can be different. For example, the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the second sub-pixel SP2 can have a rectangular planar shape, having a long side in the first direction DR1 and a short side in the second direction DR2. In the planar diagram, the first electrode AND of the third sub-pixel SP3 can also have a rectangular shape, having a short side in the first direction DR1 and a long side in the second direction DR2. The length of the first electrode AND of the third sub-pixel SP3 in the first direction DR1 can be less than the length of the first electrode AND of each of the first sub-pixels SP1 and SP2 in the first direction DR1. The length of the first electrode AND of the first sub-pixel SP1 in the second direction DR2 can be greater than the length of the first electrode AND of the second sub-pixel SP2 in the second direction DR2.

[0177] The first electrode AND of the light-emitting element can be connected to the reflective electrode layer RL via an electrode via VAP (e.g., see...). Figure 12 The electrode via VAP can be stacked on the third-direction DR3 with the first pixel limiting film PDL1, the second pixel limiting film PDL2, and the third pixel limiting film PDL3.

[0178] At least one trench TRC (e.g., see Figure 12 The structure can be a charge-generating layer used to cut off the light-emitting stack IL between adjacent light-emitting regions EA1, EA2, and EA3. At least one trench TRC can be disposed between the first light-emitting region EA1 and the second light-emitting region EA2, between the first light-emitting region EA1 and the third light-emitting region EA3, and between the second light-emitting region EA2 and the third light-emitting region EA3. More specifically, at least one trench TRC can be disposed between the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the second sub-pixel SP2, between the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the third sub-pixel SP3, and between the first electrode AND of the second sub-pixel SP2 and the first electrode AND of the third sub-pixel SP3.

[0179] Figure 11 This is a plan view illustrating a pixel-defining film of a plurality of sub-pixels disposed in a display area of ​​a display unit, a first electrode, and a light-emitting area, according to one or more embodiments.

[0180] Reference Figure 11 Except for the planar shapes of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3, which are similar to... Figure 10 Apart from the different embodiments, Figure 11Implementation examples and Figure 10 The implementation examples are basically the same, except that the following will be omitted: Figure 10 The description overlaps with the embodiments.

[0181] In the plan view, the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3 can be configured as a hexagonal structure. In this case, the first light-emitting area EA1 and the second light-emitting area EA2 can be adjacent to each other in the first direction DR1, while the second light-emitting area EA2 and the third light-emitting area EA3 can be adjacent to each other in the first diagonal direction DD1, and the first light-emitting area EA1 and the third light-emitting area EA3 can be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2. The second diagonal direction DD2 can be a direction perpendicular to the first diagonal direction DD1.

[0182] Despite Figure 10 and Figure 11 The diagram shows that each of the plurality of pixels PX includes three light-emitting regions EA1, EA2, and EA3, but this disclosure is not limited thereto. That is, each of the plurality of pixels PX may include four light-emitting regions.

[0183] Furthermore, the arrangement of the light-emitting regions of the multiple pixels PX is not limited to the arrangement shown in the accompanying drawings. For example, in a planar view, the light-emitting regions of the multiple pixels PX can be configured as a stripe structure in which the light-emitting regions are arranged along a first direction DR1, or as a pentile in which the light-emitting regions are arranged in a diamond shape. ® A structure, or a hexagonal structure in which hexagonal luminescent areas are arranged side by side. (PENTILE) ® It is a registered trademark of Samsung Display Co., Ltd. of South Korea.

[0184] Figures 12 to 14 It is a cross-sectional view showing a portion of the display area and a portion of the non-display area in a display unit according to one or more embodiments. Figures 12 to 14 A schematic cross-sectional structure of the display area DAA, the non-display area NA, and the pad area PDA is disclosed.

[0185] Reference Figures 12 to 14The display unit 200 may include a semiconductor backplane (SBP), a pixel circuit backplane (EBP), a display element layer (EML), a packaging layer (TFE), an adhesive layer (ADL), an optical layer (OPL) including a color filter layer (CFL), a lens layer (LNS), and a filler layer (FIL), and a cover layer (DCL). The semiconductor backplane (SBP) and pixel circuit backplane (EBP) of the display unit 200 may constitute a pixel circuit layer 220. The display element layer (EML), packaging layer (TFE), adhesive layer (ADL), optical layer (OPL) including a color filter layer (CFL), a lens layer (LNS), and a filler layer (FIL), and cover layer (DCL) of the display unit 200 may constitute a display layer 230. In one or more embodiments, the display unit 200 may further include a polarizing plate disposed on the cover layer (DCL). A connection wiring layer 500 may be disposed between the first single-crystal semiconductor substrate 110 and the second single-crystal semiconductor substrate 210 of the semiconductor backplane (SBP). Optionally, the connection wiring layer 500 may be disposed between the display element layer (EML) and the first single-crystal semiconductor substrate 110.

[0186] The semiconductor backplane (SBP) includes a second single-crystal semiconductor substrate 210 containing a plurality of second transistors PTR2, a plurality of semiconductor insulating films disposed on the plurality of second transistors PTR2, and a plurality of contact electrodes CTEs electrically connected to the plurality of pixel transistors respectively. The plurality of second transistors PTR2 can be configured as... Figure 6 The first transistor T1 to the sixth transistor T6 of the pixel circuit, or the scan transistors of the gate drivers 610 and 620.

[0187] The second single-crystal semiconductor substrate 210 can be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The second single-crystal semiconductor substrate 210 can be a substrate doped with impurities. Multiple well regions WA can be disposed on the top surface of the second single-crystal semiconductor substrate 210. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. For example, when the first type of impurity is a P-type impurity, the second type of impurity can be an N-type impurity. Optionally, when the first type of impurity is an N-type impurity, the second type of impurity can be a P-type impurity.

[0188] Similar to the first single-crystal semiconductor substrate 110, the second single-crystal semiconductor substrate 210 may include a plurality of second transistors PTR2. The structure of the second transistors PTR2 may be the same as that of the first transistor PTR1, therefore, its detailed description will be omitted.

[0189] In the display device 10, the wafer substrates on which the first transistor PTR1 formed on the first single-crystal semiconductor substrate 110 of the driving unit 100 and the second transistor PTR2 formed on the second single-crystal semiconductor substrate 210 of the display unit 200 are formed can be different. According to one or more embodiments, in the display device 10, the first transistor PTR1 formed on the first single-crystal semiconductor substrate 110 and the second transistor PTR2 formed on the second single-crystal semiconductor substrate 210 can have different sizes, linewidths, etc.

[0190] For example, in display device 10, the minimum linewidth of the first transistor PTR1 formed on the first single-crystal semiconductor substrate 110 can be smaller than the minimum linewidth of the second transistor PTR2 formed on the second single-crystal semiconductor substrate 210. Compared to the semiconductor process performed on the second wafer substrate used to form the second transistor PTR2, the semiconductor process performed on the first wafer substrate used to form the first transistor PTR1 is a high-resolution process, thus allowing for smaller dimensions of components such as the manufactured transistors. In other words, the semiconductor process performed on the first wafer substrate can be a more refined process than the semiconductor process performed on the second wafer substrate.

[0191] As described above, the first single-crystal semiconductor substrate 110 of the driving unit 100 can have a smaller area in a planar view than the second single-crystal semiconductor substrate 210 of the display unit 200, and can accommodate small-sized components with high integration density to reduce power consumption and improve manufacturing yield. On the other hand, compared to the first single-crystal semiconductor substrate 110, the second single-crystal semiconductor substrate 210 of the display unit 200 can have a larger area in a planar view, and can perform processes with relatively large linewidths. The second transistor PTR2 disposed in the second single-crystal semiconductor substrate 210 can be formed in a larger area than when formed in the first single-crystal semiconductor substrate 110, and the second transistor PTR2 constituting the pixel circuit does not require high integration density. Therefore, the semiconductor process performed on the first wafer substrate can be performed as a high-cost process with small linewidth, and the semiconductor process performed on the second wafer substrate can be performed as a low-cost process with relatively large linewidth.

[0192] In one or more embodiments, the channel regions CH of the plurality of transistors PTR1 and PTR2 may have different lengths than each other, and the minimum linewidth or length of the channel region CH of the first transistor PTR1 may be smaller than the minimum linewidth or length of the channel region CH of the second transistor PTR2. The minimum linewidth or length of the channel region CH of the first transistor PTR1 may be less than or equal to 100 nm, or may be in the range of 2 nm to 80 nm. The minimum linewidth or length of the channel region CH of the second transistor PTR2 may be greater than or equal to 100 nm, or may be in the range of 100 nm to 5 μm.

[0193] The second single-crystal semiconductor substrate 210 may include a plurality of vias TSV1, TSV2, TSV3, and TSV4 spaced apart from each other (e.g., spaced apart). The vias TSV1, TSV2, TSV3, and TSV4 can penetrate from the top surface of the second single-crystal semiconductor substrate 210 to its bottom surface, and can also penetrate a plurality of semiconductor insulating layers SINS3 and SINS4 and interlayer insulating layers INS3, INS4, and INS5 disposed on the second single-crystal semiconductor substrate 210. Conductive vias RVA1, RVA2, RVA3, and RVA4 for routing lines RM1, RM2, RM3, and RM4 can be disposed in the vias TSV1, TSV2, TSV3, and TSV4. The vias TSV1, TSV2, TSV3, and TSV4 can form connection paths for the routing lines RM1, RM2, RM3, and RM4 that electrically connect the driving unit 100 to the terminals DTD, GTD1, GTD2, and STD of the display unit 200. In one or more embodiments, the vias TSV1, TSV2, TSV3, and TSV4 of the second single-crystal semiconductor substrate 210 and the interlayer insulating layers INS3, INS4, and INS5 can be formed using a through-silicon via (TSV) process, in which holes penetrating the wafer substrate are formed. Through the vias TSV1, TSV2, TSV3, and TSV4 formed in the second single-crystal semiconductor substrate 210 and the interlayer insulating layers INS3, INS4, and INS5, the display layer 230 and the driving unit 100 can be electrically connected to each other via routing lines RM1, RM2, RM3, and RM4 without additional wiring.

[0194] A process to reduce the thickness of the second single-crystal semiconductor substrate 210 can be performed after the driving unit 100 is bonded to the silicon wafer substrate. The second single-crystal semiconductor substrate 210 can have a smaller thickness compared to the thickness of the wafer substrate to which processes for forming the conductive layer are performed. In one or more embodiments, the thickness of the second single-crystal semiconductor substrate 210 can be 100 μm or less, for example, in the range of 80 μm to 100 μm.

[0195] The pixel circuit layer 220 can be disposed on the second single-crystal semiconductor substrate 210. The pixel circuit layer 220 may include a pixel circuit backplane EBP and a semiconductor backplane SBP.

[0196] The third semiconductor insulating layer SINS3 can be disposed on the second single-crystal semiconductor substrate 210 and on the gate electrode of the second transistor PTR2. The third semiconductor insulating layer SINS3 can be made of silicon carbonitride (SiCN) and / or silicon oxide (SiO2). x ( ) Inorganic membrane formation, but not limited to this.

[0197] The fourth semiconductor insulating layer, SINS4, can be disposed on the third semiconductor insulating layer, SINS3. The fourth semiconductor insulating layer, SINS4, can be made of silicon oxide (SiO2). x ( ) Inorganic membrane formation, but not limited to this.

[0198] Each of the multiple contact electrodes CTEs can be connected to one of the gate electrode GE, source region SA, and drain region DA of each of the second transistors PTR2 through a hole penetrating the third semiconductor insulating layer SINS3 and the fourth semiconductor insulating layer SINS4. The multiple contact electrodes CTEs can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or alloys including one or more of them.

[0199] The pixel circuit backplane (EBP) may include a third interlayer insulating layer INS3, a fourth interlayer insulating layer INS4, a fifth interlayer insulating layer INS5, a sixth interlayer insulating layer INS6, and a seventh interlayer insulating layer INS7, as well as multiple interconnect conductive layers (RMTs). The interconnect conductive layers (RMTs) may include wiring electrically connected to multiple second transistors (PTR2) formed in the second single-crystal semiconductor substrate 210. The pixel circuit backplane (EBP) may include multiple scan lines GL1 and GL2, data lines DL, and multiple terminals DTD, GTD1, GTD2, and STD disposed in the display unit 200.

[0200] A third interlayer insulating layer INS3 can be disposed on multiple contact electrodes CTEs and a third semiconductor insulating layer SINS3 and a fourth semiconductor insulating layer SINS4. A fourth interlayer insulating layer INS4 can be disposed on the third interlayer insulating layer INS3. A fifth interlayer insulating layer INS5, a sixth interlayer insulating layer INS6, and a seventh interlayer insulating layer INS7 can be sequentially disposed on the fourth interlayer insulating layer INS4. Multiple connecting conductive layers RMTs can be disposed between the third interlayer insulating layers INS3 to the seventh interlayer insulating layers INS7. Each of the third interlayer insulating layers INS3 to the seventh interlayer insulating layer INS7 can be made of silicon carbonitride (SiCN) and / or silicon oxide (SiO2). xThe formation of inorganic films is permitted, but is not limited thereto. Although each of the third interlayer insulating layers INS3 to the seventh interlayer insulating layers INS7 is shown in the figures as a single layer, this disclosure is not limited thereto. Each of the third interlayer insulating layers INS3 to the seventh interlayer insulating layers INS7 may have a structure in which one or more layers are stacked on top of each other.

[0201] The connecting conductive layer RMT can have a structure similar to the multiple conductive layers ML1 to ML8 and vias VA1 to VA8 of the driving circuit layer 120. The connecting conductive layer RMT may include one or more conductive layers and vias disposed between them to form terminals DTD, GTD1, GTD2, and STD, or wiring disposed in the display unit 200. For example, the connecting conductive layer RMT disposed in the pixel circuit layer 220 in the display area DAA can be electrically connected to the second transistor PTR2. The connecting conductive layer RMT shown in the figures can be connected to multiple second transistors PTR2 to form... Figure 6 The pixel circuit. The connecting conductive layer RMT can be used as a connection line to connect the second transistor PTR2 to other circuit elements. In addition, in one or more embodiments, some of the connecting conductive layers RMT disposed in the display area DAA of the pixel circuit layer 220 can be scan lines GL1 and GL2 or data lines DL, or can be used as terminals DTD, GTD1, GTD2 and STD.

[0202] The pixel circuit layer 220 may include multiple terminals DTD, GTD1, GTD2, and STD disposed in the non-display area NA. The multiple terminals DTD, GTD1, GTD2, and STD may include a data terminal DTD electrically connected to the data line DL, gate terminals GTD1 and GTD2 connected to scan lines GL1 and GL2, and a pad signal terminal STD. The multiple terminals DTD, GTD1, GTD2, and STD may be connected to conductive vias RVA1, RVA2, RVA3, and RVA4 of the routing lines in via areas TSA1, TSA2, TSA3, and TSA4 of the non-display area NA, respectively.

[0203] The interconnect wiring layer 500 can be disposed on the bottom surface of the second single-crystal semiconductor substrate 210. The interconnect wiring layer 500 may include an interlayer insulating layer RINS and multiple interconnect lines RML1, RML2, RML3 and RML4.

[0204] An interlayer insulating layer (RINS) can be disposed on the bottom surface of the second single-crystal semiconductor substrate 210. The RINS can be made of silicon carbonitride (SiCN) or silicon oxide (SiO2). xThe inorganic film is formed, but is not limited to this. In the figures, the interlayer insulating layer RINS is shown as a single layer, but is not limited to this, and may have a structure in which one or more layers are stacked on top of each other, and they may be disposed between the connecting lines RML1, RML2, RML3 and RML4.

[0205] Connectors RML1, RML2, RML3, and RML4 can form routing lines RM1, RM2, RM3, and RM4 together with multiple conductive vias RVA1, RVA2, RVA3, and RVA4. Connectors RML1, RML2, RML3, and RML4 may include one or more conductive layers and one or more vias connecting them to each other. The connections and structure of connectors RML1, RML2, RML3, and RML4 can be the same as those described above for conductive layers ML1 to ML8 and vias VA1 to VA8. The connecting lines RML1, RML2, RML3 and RML4 can be electrically connected to multiple terminals DTD, GTD1, GTD2 and STD, multiple scan lines GL1 and GL2 and data lines DL provided in the display unit 200 through conductive vias RVA1, RVA2, RVA3 and RVA4 provided in the vias TSV1, TSV2, TSV3 and TSV4 of the second single crystal semiconductor substrate 210, and can also be electrically connected to the driving circuit layer 120 of the driving unit 100.

[0206] According to one or more embodiments, the display unit 200 of the display device 10 may include a first through-hole TSV1, a second through-hole TSV2, a third through-hole TSV3, and a fourth through-hole TSV4 penetrating the second single-crystal semiconductor substrate 210. The first through-hole to the fourth through-hole TSV1, TSV2, TSV3, and TSV4 may all be disposed in the non-display area NA. As described above, the first through-hole TSV1 may be disposed in the first through-hole region TSA1 located above the display area DAA, and the second through-hole TSV2 and the third through-hole TSV3 may be disposed in the second through-hole regions TSA2 and TSA3 located to the left and right of the display area DAA, respectively. The fourth through-hole TSV4 may be disposed in the fourth through-hole region TSA4 located between the display area DAA and the pad area PDA.

[0207] The first conductive via RVA1 of the first routing line RM1 can be disposed in the first through-hole TSV1. The first through-hole TSV1 can penetrate the second single-crystal semiconductor substrate 210, semiconductor insulating layers SINS3 and SINS4, and interlayer insulating layers INS3, INS4, and INS5 to extend from the bottom surface of the data terminal DTD to the bottom surface of the second single-crystal semiconductor substrate 210. The first conductive via RVA1 can be disposed from the bottom surface of the data terminal DTD to the bottom surface of the second single-crystal semiconductor substrate 210 to connect to each of the data terminal DTD and the first connection line RML1. The first connection line RML1 can be as described above. Figure 8 The data routing line RDL is described. The first routing line RM1 can connect the data terminal DTD connected to the data line DL to the data driver 700 or the driver circuit layer 120 of the driver unit 100.

[0208] The second conductive via RVA2 of the second route line RM2 can be disposed in the second via TSV2. The second via TSV2 can penetrate the second single-crystal semiconductor substrate 210, semiconductor insulating layers SINS3 and SINS4, and interlayer insulating layers INS3, INS4, and INS5 to extend from the bottom surface of the first gate terminal GTD1 to the bottom surface of the second single-crystal semiconductor substrate 210. The second conductive via RVA2 can be disposed from the bottom surface of the first gate terminal GTD1 to the bottom surface of the second single-crystal semiconductor substrate 210 to connect to each of the first gate terminal GTD1 and the second connection line RML2. The second connection line RML2 can be as described above. Figure 8 The first scan routing line GSL1 is described. The second routing line RM2 can connect the first gate terminal GTD1, which is connected to the first scan line GL1, to the scan driver 610 or the drive circuit layer 120 of the drive unit 100.

[0209] The third conductive via RVA3 of the third connection line RM3 can be disposed in the third via TSV3. The third via TSV3 can penetrate the second single-crystal semiconductor substrate 210, semiconductor insulating layers SINS3 and SINS4, and interlayer insulating layers INS3, INS4, and INS5 to extend from the bottom surface of the second gate terminal GTD2 to the bottom surface of the second single-crystal semiconductor substrate 210. The third conductive via RVA3 can be disposed from the bottom surface of the second gate terminal GTD2 to the bottom surface of the second single-crystal semiconductor substrate 210 to connect to each of the second gate terminal GTD2 and the third connection line RML3. The third connection line RML3 can be as described above. Figure 8 The second scan routing line GSL2 is described. The third routing line RM3 can connect the second gate terminal GTD2, which is connected to the second scan line GL2, to the emitter driver 620 or the drive circuit layer 120 of the drive unit 100.

[0210] The fourth conductive via RVA4 of the fourth connection line RM4 can be disposed in the fourth via TSV4. The fourth via TSV4 can penetrate the second single-crystal semiconductor substrate 210, semiconductor insulating layers SINS3 and SINS4, and interlayer insulating layers INS3, INS4, and INS5 to extend from the bottom surface of the pad signal terminal STD to the bottom surface of the second single-crystal semiconductor substrate 210. The fourth conductive via RVA4 can be disposed from the bottom surface of the pad signal terminal STD to the bottom surface of the second single-crystal semiconductor substrate 210 to connect to each of the pad signal terminal STD and the fourth connection line RML4. The fourth connection line RML4 can be as described above. Figure 8 The described signal routing line SCL. The fourth routing line RM4 can be electrically connected to the pad signal terminal STD of the circuit board 300 and to the signal terminal TPD of the drive unit 100.

[0211] In the display device 10, the circuit portions disposed in the driving unit 100 can be formed using high-cost microsemiconductor processes, and thus can be formed with high integration density on a first single-crystal semiconductor substrate 110 having a small area. The manufacturing process of the driving unit 100 can have a high yield per unit wafer substrate, and the circuit elements (e.g., the first transistor) can have a small size, thereby reducing power consumption. In addition, by providing wiring and pixel circuitry for light emission of light-emitting elements in the display unit 200, it is possible to prevent the integration density of the first single-crystal semiconductor substrate 110 from becoming too high. Furthermore, by determining an appropriate number (e.g., an optimized number) of vias TSV1, TSV2, TSV3, and TSV4 in which routing lines RM1, RM2, RM3, and RM4 connecting the driving unit 100 and the display unit 200 are disposed, the space in which vias TSV1, TSV2, TSV3, and TSV4 having (e.g., required) appropriate diameters (e.g., predetermined diameters) and spacing distances are disposed can be reduced or minimized.

[0212] The display layer 230 can be disposed on the second single-crystal semiconductor substrate 210 and the pixel circuit layer 220. The display layer 230 may include a display element layer EML, a packaging layer TFE, an optical layer OPL, and a cover layer DCL. The display layer 230 may include a light-emitting element electrically connected to the driving unit 100 and emitting light.

[0213] The display element layer (EML) can be disposed on the pixel circuit backplane (EBP) of the pixel circuit layer 220. The display element layer (EML) may include a light-emitting element, a reflective electrode layer (RL), an eighth interlayer insulating layer (INS8) and a ninth interlayer insulating layer (INS9), an electrode via (VAP), a pixel defining film (PDL), and multiple trenches (TRC). The light-emitting element has a first electrode (AND), a light-emitting stack (IL), and a second electrode (CAT).

[0214] The reflective electrode layer RL can be disposed on the seventh interlayer insulating layer INS7. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, as... Figure 12 As shown, the reflective electrode layer RL may include a first reflective electrode to a fourth reflective electrode RL1, RL2, RL3 and RL4.

[0215] Each of the first reflective electrodes RL1 may be disposed on the seventh interlayer insulating layer INS7 and may be connected to a via that partially penetrates the seventh interlayer insulating layer INS7. The first reflective electrodes RL1 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) and / or alloys including one or more of them. For example, the first reflective electrodes RL1 may include titanium nitride (TiN).

[0216] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrodes RL2 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) and / or alloys including one or more of them. For example, the second reflective electrode RL2 may include aluminum (Al).

[0217] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) and / or alloys including one or more of them. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0218] The fourth reflective electrode RL4 can be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) and / or alloys including one or more of them. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0219] Because the second reflective electrode RL2 is the electrode that substantially reflects light from the light-emitting element, its thickness can be greater than the thickness of each of the first, third, and fourth reflective electrodes RL1 and RL3. For example, the thickness of each of the first, third, and fourth reflective electrodes RL1 and RL3 can be approximately 100 Å, and the thickness of the second reflective electrode RL2 can be approximately 850 Å. In one or more embodiments, the thickness of the fourth reflective electrode RL4 can be greater than the thickness of each of the first, second, and third reflective electrodes RL1 and RL2.

[0220] The eighth interlayer insulating layer INS8 can be disposed on the seventh interlayer insulating layer INS7. The eighth interlayer insulating layer INS8 can be disposed between adjacent reflective electrode layers RL. The eighth interlayer insulating layer INS8 can be disposed on the reflective electrode layer RL in the first sub-pixel SP1. The eighth interlayer insulating layer INS8 can be made of silicon oxide (SiO2). x ( ) Inorganic membrane formation, but not limited to this.

[0221] The ninth interlayer insulating layer INS9 can be disposed on the eighth interlayer insulating layer INS8 and the reflective electrode layer RL. The ninth interlayer insulating layer INS9 can be made of silicon oxide (SiO2). x ( ) Inorganic membrane formation, but not limited to this.

[0222] In at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, taking into account the resonant distance of the light emitted from the light-emitting element LE, the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9 may not be disposed below the first electrode AND.

[0223] For example, the first electrode AND of the third sub-pixel SP3 can be directly disposed on the fourth reflective electrode RL4, and the first electrode AND of the third sub-pixel SP3 does not need to be superimposed on the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9. The first electrode AND of the second sub-pixel SP2 can be disposed on the ninth interlayer insulating layer INS9, and the ninth interlayer insulating layer INS9 can be directly disposed on the fourth reflective electrode RL4. That is to say, the first electrode AND of the second sub-pixel SP2 does not need to be superimposed on the eighth interlayer insulating layer INS8. The first electrode AND of the first sub-pixel SP1 can be disposed on the ninth interlayer insulating layer INS9, and can be superimposed on the eighth interlayer insulating layer INS8.

[0224] In one or more embodiments, the distance between the first electrode AND and the reflective electrode layer RL can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. To adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main peak wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of an eighth interlayer insulating layer INS8 and a ninth interlayer insulating layer INS9 can be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, in... Figure 12 In the first sub-pixel SP1, the distance between the first electrode AND and the reflective electrode layer RL can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the third sub-pixel SP3. The distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 can also be greater than the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3. However, this disclosure is not limited to this. The distance between the first electrode AND and the reflective electrode layer RL in each of the sub-pixels SP1, SP2, and SP3 can be modified and designed differently.

[0225] Additionally, although the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9 are shown in the accompanying drawings, the tenth interlayer insulating layer can also be disposed below the first electrode AND of the sub-pixel SP. In this case, the ninth interlayer insulating layer INS9 and the tenth interlayer insulating layer can be disposed below the first electrode AND of the second sub-pixel SP2, and the eighth interlayer insulating layer INS8, the ninth interlayer insulating layer INS9, and the tenth interlayer insulating layer can be disposed below the first electrode AND of the first sub-pixel SP1.

[0226] Each of the electrode vias (VAPs) can be connected to a fourth reflective electrode RL4 exposed in the first sub-pixel SP1 and the second sub-pixel SP2 through an eighth interlayer insulating layer INS8 and / or a ninth interlayer insulating layer INS9. The electrode vias (VAPs) can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys comprising one or more of these. The thickness of the electrode vias (VAPs) in the second sub-pixel SP2 can be less than the thickness of the electrode vias (VAPs) in the first sub-pixel SP1.

[0227] The first electrode AND of each of the light-emitting elements can be disposed on the ninth interlayer insulating layer INS9 or the reflective electrode layer RL, and can be connected to the fourth reflective electrode RL4 via an electrode via VAP or directly connected to the fourth reflective electrode RL4. The first electrode AND of each of the light-emitting elements LE can be connected to the second transistor PTR2 via the electrode via VAP, the first reflective electrode RL1 to the fourth reflective electrode RL4, the connecting conductive layer RMT, and the contact electrode CTE. The first electrode AND of each of the light-emitting elements can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or alloys including one or more of them. For example, the first electrode AND of each of the light-emitting elements can be titanium nitride (TiN).

[0228] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements. The PDL can cover the edge of the first electrode AND of each of the light-emitting elements. The PDL can be used to divide a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3.

[0229] The first light-emitting region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second light-emitting region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third light-emitting region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0230] The pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be disposed on the edge of the first electrode AND of each of the light-emitting elements (LEs). The second pixel-defining film (PDL2) may be disposed on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be disposed on the second pixel-defining film (PDL2). The first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may be made of silicon oxide (SiO2). x The formation of inorganic films can be categorized as follows, but is not limited to this. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 can each have a thickness of approximately 500 Å.

[0231] When the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 form a single pixel defining film, the height of this single pixel defining film increases, making the first inorganic encapsulation layer TFE1 potentially cut due to step coverage. Step coverage refers to the ratio of the degree of film coating on the inclined portion to the degree of film coating on the flat portion. The lower the step coverage, the more likely the film will be cut at the inclined portion.

[0232] To reduce or prevent the possibility of the first inorganic encapsulation layer TFE1 being cut due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure with stepped portions. For example, the width of the first pixel defining film PDL1 may be greater than the width of the second pixel defining film PDL2 and the width of the third pixel defining film PDL3, and the width of the second pixel defining film PDL2 may be greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1 refers to the horizontal length of the first pixel defining film PDL1 defined in the first direction DR1 and the second direction DR2.

[0233] Each of the multiple trench TRCs can penetrate the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3. In each of the multiple trench TRCs, a portion of the eighth interlayer insulating layer INS8 can be excavated and the ninth interlayer insulating layer INS9 can be penetrated.

[0234] At least one trench TRC can be set between adjacent sub-pixels SP1, SP2 and SP3. Figures 12 to 14 Two trench TRCs are shown positioned between adjacent sub-pixels SP1, SP2, and SP3, but this disclosure is not limited thereto.

[0235] The light-emitting stack IL can include multiple stacks. The accompanying drawings show a three-in-series structure of a light-emitting stack IL including a first light-emitting stack IL1, a second light-emitting stack IL2, and a third light-emitting stack IL3, but this disclosure is not limited thereto. For example, the light-emitting stack IL can have a two-in-series structure including two light-emitting stacks.

[0236] In a three-series structure, the light-emitting stack IL can have a series structure comprising multiple light-emitting stacks IL1, IL2, and IL3 that emit different colors of light. For example, the light-emitting stack IL may include a first light-emitting stack IL1 that emits light of a first color, a second light-emitting stack IL2 that emits light of a second color, and a third light-emitting stack IL3 that emits light of a third color. The first light-emitting stack IL1, the second light-emitting stack IL2, and the third light-emitting stack IL3 can be stacked sequentially.

[0237] The first light-emitting stack IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second light-emitting stack IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a second color, and a second electron transport layer are sequentially stacked. The third light-emitting stack IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a third color, and a third electron transport layer are sequentially stacked.

[0238] A first charge generation layer for supplying holes to the second light-emitting stack IL2 and electrons to the first light-emitting stack IL1 may be disposed between the first light-emitting stack IL1 and the second light-emitting stack IL2. The first charge generation layer may include an N-type charge generation layer that supplies electrons to the first light-emitting stack IL1 and a P-type charge generation layer that supplies holes to the second light-emitting stack IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0239] A second charge generation layer for supplying holes to the third light-emitting stack IL3 and electrons to the second light-emitting stack IL2 can be disposed between the second light-emitting stack IL2 and the third light-emitting stack IL3. The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second light-emitting stack IL2 and a P-type charge generation layer that supplies holes to the third light-emitting stack IL3.

[0240] A first light-emitting stack IL1 can be disposed on the first electrode AND and the pixel defining film PDL, and can be disposed on the bottom surface of each trench TRC. Due to the trench TRC, the first light-emitting stack IL1 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A second light-emitting stack IL2 can be disposed on the first light-emitting stack IL1. Due to the trench TRC, the second light-emitting stack IL2 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A cavity or empty space ESS can be disposed between the first light-emitting stack IL1 and the second light-emitting stack IL2. A third light-emitting stack IL3 can be disposed on the second light-emitting stack IL2. The third light-emitting stack IL3 is not cut by the trench TRC and can be configured to cover the second light-emitting stack IL2 in each of the trench TRCs. That is, in the three-series structure, each of the plurality of trench TRCs can be a structure for cutting off the display element layer EML, the first light-emitting stack IL1 and the second light-emitting stack IL2, the first charge generation layer and the second charge generation layer between adjacent sub-pixels SP1, SP2, and SP3. In addition, in the two-series structure, each of the multiple trench TRCs can be a structure for cutting off the charge generation layer disposed between the lower light-emitting stack and the upper light-emitting stack, as well as the lower light-emitting stack.

[0241] To stably cut off the first light-emitting stack IL1 and the second light-emitting stack IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel-defining film PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel-defining film PDL refers to the length of the pixel-defining film PDL in the third direction DR3. To cut off the first light-emitting stack IL1 and the second light-emitting stack IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, another structure can exist to replace the trench TRCs. For example, an inverted conical partition wall can be provided on the pixel-defining film PDL to replace the trench TRCs.

[0242] The number of light-emitting stacks IL1, IL2, and IL3 emitting different lights is not limited to the number shown in the figures. For example, the light-emitting stack IL may include two light-emitting stacks. In this case, one of the two light-emitting stacks may be substantially the same as the first light-emitting stack IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge-generating layer for supplying electrons to one light-emitting stack and holes to the other light-emitting stack may be disposed between the two light-emitting stacks.

[0243] in addition, Figures 12 to 14 The illustration shows that all three light-emitting stacks IL1, IL2, and IL3 are disposed within the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3; however, this disclosure is not limited thereto. For example, the first light-emitting stack IL1 may be disposed within the first light-emitting region EA1, but may not be disposed within the second and third light-emitting regions EA2 and EA3. Similarly, the second light-emitting stack IL2 may be disposed within the second light-emitting region EA2, but may not be disposed within the first and third light-emitting regions EA1 and EA3. Likewise, the third light-emitting stack IL3 may be disposed within the third light-emitting region EA3, but may not be disposed within the first and second light-emitting regions EA1 and EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL can be omitted.

[0244] The second electrode CAT can be disposed on the third light-emitting stack IL3. The second electrode CAT can be disposed on the third light-emitting stack IL3 in each of the multiple trench TRCs. The second electrode CAT can be formed of a transparent conductive material (TCO) that transmits light, such as ITO and / or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), and / or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, light emission efficiency can be improved in each of the first to third sub-pixels SP1, SP2, and SP3 due to the microcavity effect.

[0245] An encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic encapsulation layer TFE1 and TFE3 to reduce or prevent oxygen and / or moisture penetration into the display element layer EML. Additionally, the encapsulation layer TFE may include at least one organic film to protect the display element layer EML from foreign matter such as dust. For example, the encapsulation layer TFE may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3.

[0246] A first inorganic encapsulation layer TFE1 can be disposed on the second electrode CAT, an organic encapsulation layer TFE2 can be disposed on the first inorganic encapsulation layer TFE1, and a second inorganic encapsulation layer TFE3 can be disposed on the organic encapsulation layer TFE2. Both the first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 can be made of silicon nitride (SiN). x ) layer, silicon oxynitride (SiO) x N y ) layer, silicon dioxide (SiO) x ) layer, titanium dioxide (TiO) x ) layer and / or alumina (AlO) x Multiple films are formed by alternately stacking one or more inorganic films. The organic encapsulation layer TFE2 can be a monomer. Alternatively, the organic encapsulation layer TFE2 can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0247] The adhesive layer ADL can be disposed on the encapsulation layer TFE. The adhesive layer ADL can be a layer used to bond the encapsulation layer TFE to the layer disposed thereon. The adhesive layer ADL can be a double-sided adhesive component. Alternatively, the adhesive layer ADL can be a transparent adhesive component such as a transparent adhesive or a transparent adhesive resin.

[0248] The optical layer (OPL) may include a color filter layer (CFL), multiple lenses (LNS), and a filler layer (FIL). The color filter layer (CFL) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3). The first to third color filters (CF1, CF2, and CF3) may be disposed on the adhesive layer (ADL).

[0249] A first color filter CF1 can be superimposed on a first emitting region EA1. The first color filter CF1 can transmit light of a first color (i.e., light in the red band). The red band can be approximately 600nm to 750nm. The first color filter CF1 can transmit light of the first color emitted from the first emitting region EA1.

[0250] The second color filter CF2 can be superimposed on the second emitting region EA2. The second color filter CF2 can transmit light of a second color (i.e., light in the green band). The green band can be approximately 480nm to 560nm. The second color filter CF2 can transmit light of the second color emitted from the second emitting region EA2.

[0251] The third color filter CF3 can be superimposed on the third emitting region EA3. The third color filter CF3 can transmit light of the third color (i.e., light in the blue band). The blue band can be approximately 370nm to 460nm. The third color filter CF3 can transmit light of the third color emitted from the third emitting region EA3.

[0252] Multiple lenses LNS can be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the multiple lenses LNS can be a structure for increasing the ratio of light guided to the front of the display device 10. Each of the multiple lenses LNS can have a cross-sectional shape that convexes in the upward direction.

[0253] A filler layer (FIL) can be disposed on multiple lens lenses (LNS). The filler layer FIL can have a suitable refractive index (e.g., a predetermined refractive index) such that light travels in the third-direction DR3 at the interface between the filler layer FIL and the multiple lens lenses (LNS). Furthermore, the filler layer FIL can be a planarization layer. The filler layer FIL can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0254] A cover layer DCL can be disposed on a filler layer FIL. The cover layer DCL can be a glass substrate and / or a polymer resin. When the cover layer DCL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the cover layer DCL. When the cover layer DCL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer DCL is a polymer resin, it can be directly applied to the filler layer FIL.

[0255] In one or more embodiments, the display unit 200 may further include a polarizing plate disposed on the cover layer DCL. The polarizing plate may be disposed on one surface of the cover layer DCL. The polarizing plate may be a structure for reducing or preventing visibility degradation caused by reflection of external light. The polarizing plate may include a linear polarizing plate and a phase retardation film. For example, the phase retardation film may be a λ / 4 plate (quarter-wave plate), but is not limited thereto. However, the polarizing plate may be omitted when the visibility degradation caused by reflection of external light is sufficiently overcome by the first to third color filters CF1, CF2 and CF3.

[0256] Figure 15 This is a plan view showing the arrangement of signal terminals and heating wires disposed on a first single-crystal semiconductor substrate according to one or more embodiments. Figure 16 It is along Figure 15 The sectional view taken by line A1-A1' in the diagram.

[0257] Reference Figure 15 and Figure 16 The display device 10 according to one or more embodiments may include a plurality of bonding pads SPDs disposed on the driving unit 100 and heating wires HL disposed around the bonding pads SPDs. The bonding pads SPDs may be terminals or pads connected between the driving unit 100 and the display unit 200 when they are bonded together. For example, the bonding pads SPDs may be disposed on the first single-crystal semiconductor substrate 110 of the driving unit 100 and connected to the aforementioned routing lines RM1, RM2, RM3, and RM4. With the ends of the routing lines RM1, RM2, RM3, and RM4 of the connecting wiring layer 500 connected to the bonding pads SPDs, the driving unit 100 may be bonded to the display unit 200 to form a display device 10. Figure 15 The bonding pad SPD shown can be understood as illustrating the bonding portion connected to the routing lines RM1, RM2, RM3 and RM4 of the connection wiring layer 500.

[0258] In one or more embodiments, the bonding pad SPD may include the above reference. Figure 2The signal terminal TPD is described. Additionally, in one or more embodiments, multiple routing lines RM1, RM2, RM3, and RM4 can be connected to terminals included in the gate driver 600 and data driver 700 of the drive unit 100. The bonding pad SPD can also include terminals of the gate driver 600 and data driver 700. The bonding pad SPD can be formed with a structure substantially the same as the pad PD of the display unit 200 and can be connected to the timing control circuitry 400, gate driver 600, and data driver 700 of the drive unit 100. The drive unit 100 and the display unit 200 can be connected to each other via the bonding pad SPD. Electrical signals applied to the routing lines RM1, RM2, RM3, and RM4 can be transmitted to the drive unit 100 via the bonding pad SPD. In this case, the number of bonding pads SPD can be the same as the number of vias TSV1, TSV2, TSV3, and TSV4, and they can be arranged on the outer portion of the drive unit 100.

[0259] The driving unit 100 and the display unit 200 can be bonded to each other via a bonding pad SPD by applying pressure and heat while they are in contact with each other. They can be bonded by placing conductive balls on the bonding pad SPD, or by partially melting the bonding pad SPD. In the above bonding process, if heat is applied at the temperature used to melt the conductive balls or the bonding pad SPD, the light-emitting elements of the display layer 230 may be damaged. To prevent this, the display device 10 may include a heating wire HL that can locally apply heat to the bonding pad SPD where the driving unit 100 and the display unit 200 are bonded.

[0260] In one or more embodiments, a heating wire HL may be disposed around a bonding pad SPD. The heating wire HL may not overlap with the bonding pad SPD and may partially surround (partially encircle) the bonding pad SPD. For example, the heating wire HL may include portions extending in a first direction DR1 and a second direction DR2, and may be disposed between bonding pads SPDs spaced apart from each other (e.g., spaced apart). The heating wire HL may be configured to bypass the bonding pad SPD while extending in one direction. The two ends of the heating wire HL may be connected to heating contact portions HCT1 and HCT2, respectively. The first heating contact portion HCT1 and the second heating contact portion HCT2 may be disposed at the two ends of the heating wire HL, respectively, and may be connected to a signal application device that can apply external heat during the bonding process of the drive unit 100 and the display unit 200. In one or more embodiments, each of the heating wire HL and the heating contact portions HCT1 and HCT2 may be made of a metallic material such as copper (Cu), tungsten (W), tin (Sn), and / or aluminum (Al). However, this disclosure is not limited thereto.

[0261] Heating wires HL and heating contact portions HCT1 and HCT2 can be disposed on the first single-crystal semiconductor substrate 110 of the driving unit 100. For example, heating wires HL can be disposed on one of the semiconductor insulating layers SINS1 or SINS2 disposed on the first single-crystal semiconductor substrate 110. Heating wires HL can be disposed between the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. Heating contact portions HCT can be disposed on the first semiconductor insulating layer SINS1 without being covered by the second semiconductor insulating layer SINS2. Bonding pads SPD disposed on the second semiconductor insulating layer SINS2 can receive heat generated by applying an electrical signal to the heating wires HL disposed around the bonding pads SPD. The heat causes the bonding pads SPD to partially melt, or the conductive balls disposed thereon to melt, so that the driving unit 100 and the display unit 200 can be bonded to each other.

[0262] Heating contact portions HCT1 and HCT2 can be respectively disposed at two edges of the first single-crystal semiconductor substrate 110. For example, the first heating contact portion HCT1 can be disposed at the left edge corresponding to the first side of the first single-crystal semiconductor substrate 110. The second heating contact portion HCT2 can be disposed at the right edge corresponding to the second side of the first single-crystal semiconductor substrate 110. This makes it easy for a probe to apply heat to contact the heating contact portions HCT1 and HCT2.

[0263] Figure 17 This is a schematic diagram illustrating the bonding process of the driving unit and the display unit during the manufacturing process of the display device according to one or more embodiments.

[0264] Reference Figure 17 In the bonding process between the drive unit 100 and the display unit 200, the bonding pad SPD disposed on the drive unit 100 can be pressed while contacting the display unit 200 or the connection wiring layer 500. In this case, the signal application device 1000 can be connected to the heating contact portions HCT1 and HCT2 of the drive unit 100, and an electrical signal can be applied to them. Heat can be generated in the heating contact portions HCT1 and HCT2 and the heating wire HL by the applied electrical signal, and the drive unit 100 and the display unit 200 can be bonded to each other via the bonding pad SPD.

[0265] The display device 10 may include a drive unit 100 and a display unit 200 that can be joined to each other via bonding pads SPD. According to one or more embodiments, the display device 10 may include heating wires HL disposed around the bonding pads SPD, and thus heat can be locally transferred only to the bonding pads SPD. Therefore, the display device 10 is able to prevent the light-emitting elements from being damaged by heat that may be applied during the bonding process of the drive unit 100 and the display unit 200.

[0266] In the following description, various embodiments of the display device 10 will be described with reference to the other accompanying drawings.

[0267] Figure 18A and Figure 18B This is a cross-sectional view showing the arrangement of heating wires of a display device according to one or more embodiments.

[0268] Reference Figure 18A In the display device 10 according to one or more embodiments, the heating wire HL may be configured to be inserted into the first single-crystal semiconductor substrate 110. Because the heating contact portion HCT should (e.g., needs) be exposed to connect to the signal application device 1000, it may be disposed on the first single-crystal semiconductor substrate 110 and the first semiconductor insulating layer SINS1, and connected to the heating wire HL via the contact portion.

[0269] Reference Figure 18B In the display device 10 according to one or more embodiments, the heating wire HL can be disposed on the second semiconductor insulating layer SINS2 and disposed on the same layer (or in the same layer) as the bonding pad SPD. The heating contact portion HCT can also be disposed on the same layer (or in the same layer) as the bonding pad SPD, but can be disposed on the first semiconductor insulating layer SINS1, and is not limited thereto. In this case, the heating wire HL disposed on the upper layer (e.g., the second semiconductor insulating layer SINS2) and the heating contact portion HCT disposed on the lower layer (e.g., the first semiconductor insulating layer SINS1) can be connected to each other via a contact portion penetrating the second semiconductor insulating layer SINS2. The arrangement of the heating wire HL can be modified in various ways, as long as it is disposed around the bonding pad SPD to transfer heat to it. In addition, the planar shape and arrangement of the heating wire HL can also be modified in various ways.

[0270] Figures 19 to 23 This is a plan view showing the arrangement of heating wires of a display device according to one or more embodiments.

[0271] Reference Figure 19In the display device 10 according to one or more embodiments, the heating wire HL may have a plate shape and be stacked with a plurality of bonding pads SPD (e.g., on a third-direction DR3). The heating wire HL may have a vertical width larger than the width of the bonding pads SPD and a horizontal width large enough to be stacked with the plurality of bonding pads SPD. The heating wire HL can effectively transfer heat when it is formed to be stacked with the bonding pads SPD.

[0272] Reference Figure 20 and Figure 21 According to one or more embodiments, the heating wire HL may have a wire shape and be stacked with the bonding pad SPD. Figure 20 In one embodiment, multiple heating wires HL can be provided, such that the first heating wire HL1 and the second heating wire HL2 can both be stacked with the bonding pad SPD. Figure 21 In one embodiment, a heating wire HL can be stacked with multiple bonding pads SPD.

[0273] Reference Figure 22 According to one embodiment, the heating wire HL may have a linear shape and may not be stacked with the bonding pad SPD. Multiple heating wires HL may be configured such that both the first heating wire HL1 and the second heating wire HL2 may be spaced apart from the bonding pad SPD (e.g., spaced apart).

[0274] exist Figures 19 to 21 In the aforementioned embodiments, since the heating wire HL is stacked with the bonding pad SPD, it can be disposed on a different layer from the bonding pad SPD. On the other hand, in Figure 22 In one embodiment, since the heating wire HL is not stacked with the bonding pad SPD, it can be disposed on the same layer (or in the same layer) as the bonding pad SPD or on a different layer.

[0275] Reference Figure 23 The display device 10 according to one or more embodiments may include multiple heating wires HL, and may also include a ground wire GSB disposed across different heating wires HL1 and HL2. The ground wire GSB may be disposed on the same layer (or at the same layer) as the different heating wires HL for contact with them. The two ends of the ground wire GSB may be grounded, or may be connected to ground wiring. After the driving unit 100 and the display unit 200 are engaged with each other, the heating wires HL may be connected to the ground wire GSB for grounding. The ground wire GSB can prevent the heating wires HL from being short-circuited.

[0276] Figure 24 This is a plan view illustrating an example of a driving unit of a display device according to one or more embodiments. Figure 25 It is shown Figure 24 A plan view of an example display unit of a display device.

[0277] Reference Figure 24 and Figure 25 The display device 10 may include a pixel circuit 800 disposed in the driving unit 100, and the pixel circuit layer 220 may be omitted from the display unit 200. Therefore, the plurality of vias TSV1 and TSV2 formed in the second single-crystal semiconductor substrate 210 may include a plurality of first vias TSV1 configured to correspond to the respective sub-pixels SP1, SP2, and SP3 in the display area DAA, and a plurality of second vias TSV2 disposed in the via area TSA. In the following description, the description will be directed to... Figures 2 to 7 The differences between the embodiments.

[0278] The driving unit 100 may include a first single-crystal semiconductor substrate 110 and a timing control circuit 400, a gate driver 600, a data driver 700 and a pixel circuit 800 formed on the first single-crystal semiconductor substrate 110.

[0279] The accompanying drawings show that the pixel circuit 800 is disposed on the upper side of the driving unit 100, the data driver 700, the timing control circuit 400, and the signal terminal area TDA are disposed on the lower side of the pixel circuit 800, and the gate driver 600 is disposed on the right side of the pixel circuit 800 on the side that is the first direction DR1. However, this disclosure is not limited thereto. In the driving unit 100, the positions of the timing control circuit 400, the gate driver 600, the data driver 700, and the pixel circuit 800 can be changed in various ways depending on the design structure of the plurality of circuit elements formed on the first single-crystal semiconductor substrate 110.

[0280] The display unit 200 may include a second single-crystal semiconductor substrate 210 and a plurality of pixels PX formed on the second single-crystal semiconductor substrate 210. The display unit 200 may include a display area DAA on which the plurality of pixels PX are disposed and a non-display area NA surrounding the display area DAA (e.g., around the display area DAA). A via area TSA and a pad area PDA may be disposed in the non-display area NA.

[0281] According to one or more embodiments, the display unit 200 of the display device 10 may include a plurality of first vias TSV1 superimposed on the display area DAA. The first vias TSV1 may be formed to penetrate the second single-crystal semiconductor substrate 210 of the display unit 200. The first vias TSV1 may form a connection path between the pixel circuit 800 of the driving unit 100 and each of the sub-pixels SP1, SP2, and SP3 of the display unit 200. The plurality of first vias TSV1 may be formed to correspond to the sub-pixels SP1, SP2, and SP3 of the display unit 200, respectively. In one or more embodiments, the number of first vias TSV1 may be equal to the number of sub-pixels SP1, SP2, and SP3, and the first vias TSV1 may be formed to be superimposed on the sub-pixels SP1, SP2, and SP3, respectively. However, this disclosure is not limited thereto. The plurality of first vias TSV1 may correspond to each sub-pixel SP1, SP2, and SP3, but may not necessarily be superimposed on them. As will be described later, multiple sub-pixels SP1, SP2 and SP3 can be electrically connected to the pixel circuit of pixel circuit 800 via connecting lines disposed in the first through hole TSV1.

[0282] The non-display area NA can be set around the display area DAA (e.g., surrounding the display area DAA). The non-display area NA can be an area where no pixels PX are set and therefore no light is emitted. The via area TSA and the pad area PDA can be set in the non-display area NA.

[0283] The pad area PDA can be disposed on the lower side of the display area DAA, which is located in the second direction DR2. Multiple pad PDs arranged along the first direction DR1 can be disposed within the pad area PDA. The circuit board 300 can be attached to the multiple pad PDs. The pad PDs can be electrically connected to the circuit board 300 and can be used to transmit electrical signals applied from the circuit board 300 to the drive unit 100.

[0284] A via region TSA can be disposed between a pad region PDA and a display region DAA. Multiple second vias TSV2 can be formed in the via region TSA. The second vias TSV2 can be connection paths for electrically connecting the signal terminals TPD of the drive unit 100 to signal connection lines of the circuit board 300. The multiple second vias TSV2 can be formed to correspond to the signal terminals TPD of the drive unit 100, respectively. In one or more embodiments, the number of second vias TSV2 can be equal to the number of signal terminals TPD, and the second vias TSV2 can be formed to be stacked on top of the signal terminals TPD, respectively. However, this disclosure is not limited thereto. The circuit board 300 can be electrically connected to the signal terminals TPD of the drive unit 100 via multiple pads PD and signal connection lines disposed in the second vias TSV2.

[0285] Figure 26 yes Figure 24 and Figure 25 A schematic cross-sectional view of the display device. Figure 27 It is shown Figure 24 and Figure 25 A schematic diagram of the rear surface of the display device.

[0286] Reference Figure 26 and Figure 27 The display device 10 according to one or more embodiments may include: a driving unit 100, including a first single-crystal semiconductor substrate 110 and a driving circuit layer 120 disposed on the first single-crystal semiconductor substrate 110; and a display unit 200, including a second single-crystal semiconductor substrate 210 and a display layer 230 disposed on the second single-crystal semiconductor substrate 210. The display device 10 may include a connection wiring layer 500 disposed between the second single-crystal semiconductor substrate 210 of the display unit 200 and the driving circuit layer 120 of the driving unit 100.

[0287] The first routing line RM1 can be connected to sub-pixels SP1, SP2, and SP3 disposed in the display layer 230 of the display unit 200 and the pixel circuit 800 of the driving unit 100. In one or more embodiments, the display device 10 may include a plurality of first vias TSV1 configured to correspond to the sub-pixels SP1, SP2, and SP3 of the display unit 200, and the first routing line RM1 can connect each of the first vias TSV1 to the pixel circuit 800. Although the first vias TSV1 can be disposed throughout the display unit 200 having a large area, the pixel circuit 800 can have a relatively small area. The first routing line RM1 may include conductive vias disposed throughout the display unit 200 having a large area and connecting lines connecting them to the pixel circuit 800 having a small area. In a plan view, the distance between the first routing line RM1 and adjacent first routing lines RM1 may be narrower in the portion that overlaps with both the driving unit 100 and the display area DAA than in the portion that overlaps with the display area DAA but not with the driving unit 100.

[0288] In one or more embodiments, some of the first vias TSV1 may be stacked with the drive unit 100 in the thickness direction (e.g., third direction DR3), while others may not be stacked with the drive unit 100 in the thickness direction. For a first routing line RM1 disposed in a first via TSV1 that is not stacked with the drive unit 100, a portion of the connecting line may not be stacked with the drive unit 100. However, the arrangement of the first vias TSV1 may vary depending on the layer position of the connecting line of the first routing line RM1.

[0289] According to one or more embodiments, the number of first vias TSV1 can be equal to the number of sub-pixels SP1, SP2, and SP3 disposed in the display area DAA. For example, multiple sub-pixels SP1, SP2, and SP3 can be arranged in the display area DAA along a first direction DR1 and a second direction DR2. The first vias TSV1 can also be arranged along the first direction DR1 and the second direction DR2, and can correspond one-to-one with each sub-pixel SP1, SP2, and SP3. The first vias TSV1 can be formed to overlap with sub-pixels SP1, SP2, and SP3 respectively. The number of first routing lines RM1 can be equal to the number of sub-pixels SP1, SP2, and SP3.

[0290] Multiple second vias TSV2 can be disposed in the via area TSA of the display unit 200, and can be formed to overlap with the signal terminal area TDA of the driving unit 100. Second routing lines RM2 connected to the signal terminals TPDs of the driving unit 100 can be disposed in the second vias TSV2. Unlike the first via TSV1, the second vias TSV2 can be formed to overlap with each signal terminal TPD of the driving unit 100. Therefore, the second routing lines RM2 can also be configured to correspond to and overlap with each signal terminal TPD. The second routing lines RM2 can be wiring that transmits signals applied from the circuit board 300 to the driving unit 100.

[0291] As described above, the driving unit 100 may include a plurality of bonding pads SPDs, which have signal terminals TPDs of the driving unit 100 and terminals disposed in the pixel circuit 800. In this case, the number of bonding pads SPDs may be the same as the sum of the number of first vias TSV1 and the number of second vias TSV2. In particular, the number of bonding pads SPDs may be greater than the number of sub-pixels SP1, SP2, and SP3 of the display unit 200. The bonding pads SPDs may be disposed in the pixel circuit 800 and the signal terminal area TDA of the driving unit 100, or in the via area TSA. Most of the bonding pads SPDs may be disposed at the center of the driving unit 100.

[0292] Figure 28 and Figure 29 It is a schematic cross-sectional view of a display device according to one or more embodiments.

[0293] Reference Figure 28In the display device 10, the driving unit 100 may be disposed on the circuit board 300, and the heating wire HL may be disposed around the pad PD connecting the circuit board 300 to the display unit 200. In one or more embodiments, the driving unit 100 may be formed as a chip and may be attached to the circuit board 300. Again, in this case, the heating wire HL is disposed around the pad PD connecting the circuit board 300 to the display unit 200, thereby reducing or minimizing heat transfer to the light-emitting element when they are joined together.

[0294] Reference Figure 29 In the display device 10, the driving unit 100 can be formed in the form of a chip and can be directly disposed on the second single-crystal semiconductor substrate 210 of the display unit 200. In the same case, the driving unit 100 can be disposed on the pad PD of the display unit 200, and the heating wire HL can be disposed around the pad PD.

[0295] Figure 30 This is a perspective view showing a head-mounted display device according to one or more embodiments. Figure 31 It is shown Figure 30 An exploded perspective view of an example of a head-mounted display device.

[0296] Reference Figure 30 and Figure 31 A head-mounted display device 1000 according to one or more embodiments includes a first display device 11, a second display device 12, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, a control circuit board 1600, and a connector.

[0297] The first display device 11 provides an image to the user's left eye, and the second display device 12 provides an image to the user's right eye. This is because each of the first display device 11 and the second display device 12 is combined with... Figure 1 The descriptions of the display devices 10 are basically the same, so the descriptions of the first display device 11 and the second display device 12 will be omitted.

[0298] The first optical component 1510 may be disposed between the first display device 11 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 12 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0299] The intermediate frame 1400 can be disposed between the first display device 11 and the control circuit board 1600, and between the second display device 12 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 11, the second display device 12 and the control circuit board 1600.

[0300] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 11 and the second display device 12 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data DATA, and can transmit the digital video data DATA to the first display device 11 and the second display device 12 via connectors.

[0301] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 11, and can transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 12. Optionally, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 11 and the second display device 12.

[0302] The display device housing 1100 is used to house the first display device 11, the second display device 12, the intermediate frame 1400, the first optical component 1510, the second optical component 1520, the control circuit board 1600, and the connector. The housing cover 1200 is configured to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 positioned thereon for the user's left eye and a second eyepiece 1220 positioned thereon for the user's right eye. The first eyepiece 1210 and the second eyepiece 1220 are shown separately in the accompanying drawings, but this disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0303] The first eyepiece 1210 can be aligned with the first display device 11 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 12 and the second optical component 1520. Therefore, the user can view the image of the first display device 11 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 12 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0304] The headband 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned over the user's left and right eyes, respectively. When the display device housing 1100 is made lightweight and compact, the head-mounted display device 1000 may be equipped with eyeglass frames instead of the headband 1300.

[0305] Additionally, the head-mounted display device 1000 may also include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, and / or a Bluetooth module.

[0306] Figure 32 This is a perspective view showing a head-mounted display device according to one or more embodiments.

[0307] Reference Figure 32 The head-mounted display device 1000_1 according to one or more embodiments may be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display device 1000_1 according to one or more embodiments may include a display device 13, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, an optical path changing component 1070, and a display device housing 1200_1.

[0308] The display device housing 1200_1 can accommodate the display device 13, the optical component 1060, and the light path changing component 1070. The image displayed on the display device 13 can be magnified by the optical component 1060, and the light path can be changed by the light path changing component 1070 to provide the image to the user's right eye through the right eye lens 1020. As a result, the user can view an augmented reality image through their right eye, which combines the virtual image displayed on the display device 13 with the real image seen through the right eye lens 1020.

[0309] The accompanying drawings show the display device housing 1200_1 positioned at the right end of the support frame 1030, but this disclosure is not limited thereto. For example, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, in which case the image displayed on the display device 13 can be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be positioned at both the left and right ends of the support frame 1030, in which case the user can view the image displayed on the display device 13 through both their left and right eyes.

[0310] The foregoing is an illustration of some embodiments of this disclosure and should not be construed as limiting it. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications can be made to the embodiments without departing from the scope of this disclosure. It will be understood that, unless otherwise described, the description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, it will be apparent to those skilled in the art that, unless specifically indicated otherwise, features, characteristics, and / or elements described in connection with a particular embodiment can be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, it will be understood that the foregoing is an illustration of various exemplary embodiments and should not be construed as limiting to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, characterized in that, The display device includes: A first single-crystal semiconductor substrate, wherein a plurality of first transistors are formed in the first single-crystal semiconductor substrate; A second single-crystal semiconductor substrate is located on the first single-crystal semiconductor substrate, and a display element layer including a plurality of light-emitting elements is located on the second single-crystal semiconductor substrate; A wiring layer is provided between the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate; Multiple vias are located in the second single-crystal semiconductor substrate, and vias connected to the interconnect lines of the interconnect wiring layer are located in the multiple vias; Multiple bonding pads, on the first single-crystal semiconductor substrate, are connected to and spaced apart from the interconnects in the interconnect wiring layer; and Heating wires are arranged around the plurality of bonding pads, with each of the two ends of the heating wires connected to a heating contact portion.

2. The display device as claimed in claim 1, characterized in that, The heating wire is not overlapped with the plurality of bonding pads.

3. The display device as claimed in claim 2, characterized in that, The heating wires bypass the bonding pads and surround at least a portion of the plurality of bonding pads.

4. The display device as claimed in claim 2, characterized in that, The heating wires include multiple heating wires, and the multiple heating wires are spaced apart from the multiple bonding pads.

5. The display device as claimed in claim 1, characterized in that, The heating wire is stacked with the plurality of bonding pads.

6. The display device as claimed in claim 5, characterized in that, The heating wire has a plate shape and a width greater than the width of the plurality of bonding pads.

7. The display device as claimed in claim 5, characterized in that, The heating wire has a shape that extends in one direction and is positioned across the plurality of bonding pads.

8. The display device as claimed in claim 1, characterized in that, The display device further includes at least one semiconductor insulating layer on the first single-crystal semiconductor substrate. The plurality of bonding pads are located on at least one semiconductor insulating layer.

9. The display device as claimed in claim 8, characterized in that, The at least one semiconductor insulating layer comprises a plurality of semiconductor insulating layers, and The heating wire is located between the plurality of semiconductor insulating layers.

10. A head-mounted display device, characterized in that, The head-mounted display device includes: The frame is installed on the user's body and corresponds to the left and right eyes; Multiple display devices are located within the frame; and Lenses, on each of the plurality of display devices, Each of the plurality of display devices includes: A first single-crystal semiconductor substrate, wherein a plurality of first transistors are formed in the first single-crystal semiconductor substrate; A second single-crystal semiconductor substrate is located on the first single-crystal semiconductor substrate, and a display element layer including a plurality of light-emitting elements is located on the second single-crystal semiconductor substrate; A wiring layer is provided between the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate; Multiple vias are located in the second single-crystal semiconductor substrate, and vias connected to the interconnect lines of the interconnect wiring layer are located in the multiple vias; Multiple bonding pads, on the first single-crystal semiconductor substrate, are connected to and spaced apart from the interconnects in the interconnect wiring layer; and Heating wires are arranged around the plurality of bonding pads, with each of the two ends of the heating wires connected to a heating contact portion.

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