Transient enhanced quick response ldo circuit

Abstract

The utility model relates to the technical field of chips, in particular to a transient enhanced quick response ldo circuit, which comprises an operational amplifier, a buffer stage circuit, a super source follower circuit and a power transistor, an SSF super source follower framework is added to serve as a transient enhanced quick response branch circuit, and the circuit is ultra-large in bandwidth and high in reliability. When the load current jumps from 17ns to 12mA, the change of the output voltage is within 2%, and the recovery time is 20ns; the ldo circuit directly monitors and feeds back the output voltage, so that a sampling signal transmission path is effectively shortened, voltage signal transmission is accelerated, and the influence of parasitism, matching and the like on sampling accuracy is minimized; the operational amplifier circuit adopts an output current mirror structure, so that the output voltage swing of the operational amplifier can be effectively improved, and the input voltage range of the grid voltage of the power tube is effectively improved; the technical problems of minimum voltage jump and rapid recovery of an ldo output voltage value during abrupt load change are solved.

Description

Technical Field

[0001] This utility model relates to the field of chip technology, and in particular to a transient enhancement-type fast response LDO circuit. Background Technology

[0002] Low-dropout linear regulator (LDLO) circuits typically employ an operational amplifier paired with a large-size power transistor circuit. Current or voltage is sampled at the output node of the power transistor, and the sampled value is sent back to the input of the operational amplifier through a negative feedback loop. When the sampled value is not equal to the reference value, the output value of the operational amplifier is pulled up or down accordingly, thereby increasing or decreasing the gate voltage of the power transistor. This adjusts the conduction level of the power transistor to control the output current and thus stabilize the output voltage value.

[0003] However, traditional LDO circuits typically only have one negative feedback loop. When the negative feedback loop path is long and the load current jumps significantly, the LDO output voltage experiences a large instantaneous surge or descent, with a long recovery time. This leads to unstable power supply to subsequent loads, affecting their operation. Some LDO circuits also incorporate an output current mirror to monitor the output current. This transient enhancement structure is usually slow in monitoring speed, inaccurate in current replication, and also detrimental to output voltage stability.

[0004] Therefore, a transient enhanced fast response LDO circuit is provided to solve the problem of minimizing voltage jumps in the LDO output voltage value and quickly recovering it during load changes. Utility Model Content

[0005] The purpose of this invention is to provide a transient enhanced fast response LDO circuit, which solves the technical problem of minimizing voltage jumps and rapidly recovering the LDO output voltage value when the load changes abruptly.

[0006] To achieve the above objectives, this utility model provides a transient enhancement-type fast response LDO circuit, comprising:

[0007] An operational amplifier is used to receive feedback voltage VFB and reference voltage VREF, and to regulate the output voltage Vout through a negative feedback loop;

[0008] A buffer stage circuit, connected to the output of the operational amplifier, is used to isolate the high-impedance node of the operational amplifier output from the subsequent circuit.

[0009] A super source follower circuit is connected to the output of the buffer stage circuit to quickly respond to sudden changes in load current.

[0010] A power transistor, the gate of which is connected to the output of the buffer stage circuit and the super source follower circuit.

[0011] The super source follower circuit includes:

[0012] M2 and M3 constitute a dynamic bias circuit, which is used to quickly adjust the gate voltage of the power transistor when the load current changes abruptly.

[0013] M1, as a common-source amplifier, is used to invert and amplify the output voltage of the operational amplifier and output it to the gate of M3;

[0014] M4, whose gate is connected to the output terminal of the buffer stage circuit, is used in conjunction with M2 and M3 to quickly respond to changes in output voltage.

[0015] The operational amplifiers include M5 and M6, which adopt a current mirror output stage architecture to expand the output voltage swing of the operational amplifiers.

[0016] The power transistor is a large-size transistor used to adjust the output current according to changes in the gate voltage in order to stabilize the output voltage Vout.

[0017] The feedback voltage VFB is sampled from the output voltage Vout through a resistor divider network, and the sampled signal is directly transmitted to the input terminal of the operational amplifier.

[0018] This invention discloses a transient enhancement-type fast response LDO circuit. The LDO circuit incorporates an SSF super source follower architecture as the fast response branch of the transient enhancement stage. The circuit's ultra-wide bandwidth enables the output voltage to change by less than 2% and recover in 20ns when the load current jumps to 12mA in 17ns. The LDO circuit directly monitors and feeds back the output voltage, effectively shortening the sampling signal transmission path, accelerating voltage signal transmission, and minimizing the impact of parasitics and mismatch on sampling accuracy. The operational amplifier circuit adopts an output current mirror architecture, which can effectively improve the output voltage swing of the op-amp, thereby effectively improving the input voltage range of the power transistor gate voltage. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0020] Figure 1 This is a schematic diagram of the transient enhanced fast response LDO circuit structure of this utility model.

[0021] Figure 2 This is a schematic diagram of an embodiment of the transient enhanced fast response LDO circuit of this utility model.

[0022] Figure 3 This is a schematic diagram comparing the circuit effects of this utility model.

[0023] In the diagram: 1-Operational amplifier, 2-Buffer stage circuit, 3-Super source follower circuit, 4-Power transistor. Detailed Implementation

[0024] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, but should not be construed as limiting the present invention.

[0025] Please see Figures 1 to 3 ,in Figure 1 This is a schematic diagram of the transient enhancement-type fast response LDO circuit structure of this utility model. Figure 2 This is a schematic diagram of an embodiment of the transient enhancement-type fast response LDO circuit of this utility model. Figure 3 This is a schematic diagram comparing the circuit effects of this utility model.

[0026] This utility model discloses a transient enhancement-type fast response LDO circuit, which includes an operational amplifier 1, a buffer stage circuit 2, a super source follower circuit 3, and a power transistor 4.

[0027] In this embodiment, the operational amplifier 1 receives the feedback voltage VFB and the reference voltage VREF, and adjusts the output voltage Vout through a negative feedback loop; the buffer stage circuit 2 is connected to the output terminal of the operational amplifier 1 and is used to isolate the high-impedance node of the operational amplifier output from the subsequent circuit; the super source follower circuit 3 is connected to the output terminal of the buffer stage circuit 2 and is used to quickly respond to sudden changes in load current; the power transistor 4 has its gate connected to the output terminals of the buffer stage circuit 2 and the super source follower circuit 3; the power transistor 4 is a large-size transistor and is used to adjust the output current according to the change of the gate voltage to stabilize the output voltage Vout.

[0028] The operational amplifier 1, with its virtual short and virtual open characteristics and loop gain, clamps the feedback voltage VFB to equal VREF, generating an output voltage Vout = VREF(1 + R2 / R1). The buffer stage circuit 2, with its small input capacitance and output resistance, can push away the high-impedance node of the operational amplifier output and the two low-frequency poles generated by the large parasitic capacitance of the power transistor 4, ensuring circuit stability and possessing a certain driving capability to drive the subsequent super source follower circuit 3. The super source follower circuit 3 receives the inverted amplified voltage signal from the operational amplifier output of the buffer stage circuit 2 as its input. After passing through the circuit structure of the super source follower circuit 3 itself, it generates a voltage value with the same output effect as the buffer stage circuit 2, which together act on the gate of the power transistor. The power transistor 4 itself has a large area and a large driving capability. By controlling the gate voltage of the buffer stage circuit 2 and the super source follower circuit 3, the output current can be controlled.

[0029] Furthermore, M2 and M3 constitute a dynamic bias circuit, used to rapidly adjust the gate voltage of the power transistor 4 when the load current changes abruptly; M1, as a common-source amplifier, is used to invert and amplify the operational amplifier output voltage and output it to the gate of M3; M4, whose gate is connected to the output terminal of the buffer stage circuit 2, is used to work together with M2 and M3 to quickly respond to changes in output voltage; the operational amplifier 1 includes M5 and M6, adopting a current mirror output stage architecture, used to expand the output voltage swing of the operational amplifier; the feedback voltage VFB is sampled from the output voltage Vout through a resistor divider network, and the sampled signal is directly transmitted to the input terminal of the operational amplifier 1.

[0030] In this embodiment, the change in VFB voltage value is first detected and transmitted to the input terminal of the operational amplifier 1. After the output signal of the operational amplifier 1 passes through the buffer stage circuit 2 and the fast response circuit of the super source follower circuit 3, the signal is transmitted to the gate terminal of the power transistor 4, and finally the VFB voltage value is stabilized.

[0031] Please see Figure 2 , Figure 2 This is a schematic diagram of an embodiment of a transient enhanced fast response LDO circuit.

[0032] Example 1 of output voltage regulation and fast recovery in LDO circuit: First, the loop labeled 1 is part 3 of the super source follower circuit described in SSF. M1 serves as the output buffer stage of the pre-amplifier circuit. On one hand, it amplifies the output voltage of the operational amplifier 1 in phase and transmits it to the gate of the power transistor 4. On the other hand, M1 acts as a common-source inverting amplifier to amplify the output voltage value of the operational amplifier and serves as the input voltage of M3. When the load current suddenly becomes large, the output voltage of the operational amplifier 1 decreases. Since M1 itself has a large transconductance gm gain, the gate voltage of M3 is significantly pulled up. M3 instantly draws a large current, causing the current of M2 to increase rapidly, and its dynamic bias voltage Vgs to drop rapidly. Combined with the significantly reduced voltage directly transmitted from M1 to M4, the two work together on the gate of the power transistor 4, causing the MPT gate voltage to drop rapidly. The voltage Vgs of M4 increases rapidly, and a large current is instantly output to supply the output terminal, achieving rapid recovery and stabilization of the output voltage value.

[0033] Example 2 of output voltage regulation and fast recovery in the LDO circuit: The fb feedback loop (labeled 2) can quickly detect changes in the output node voltage value through resistor voltage division at the feedback voltage VFB node, and rapidly transmit this information to the input of operational amplifier 1. This voltage sampling method features a short signal transmission path, high speed, and high accuracy, greatly reducing the impact of parasitics and mismatch on sampling accuracy. When the load current suddenly decreases, the VFB voltage increases, causing the output voltage of operational amplifier 1 to increase. This voltage is amplified by M1 and transmitted to the gate of M4. The output current of M4 decreases as Vgs decreases, and the VFB voltage drops to its steady-state value. Conversely, when the load current suddenly increases, this fb loop, combined with the aforementioned SSF loop, rapidly causes the gate voltage of M4 to drop, instantly outputting a large current to compensate for the pulled-down voltage of VFB.

[0034] Example 3 of output voltage regulation and fast recovery in LDO circuit: Section 3 is the current mirror output stage circuit of the op-amp. M5 and M6 consume only two Vds voltages, resulting in a high voltage margin in this branch and significantly expanding the op-amp output voltage swing. This allows the gate voltage of M1 to be pulled down or raised to the maximum extent, further expanding the output voltage range of the drain and source stages of M1. Vb1 and Vb2 are bias voltages with opposite phase to the VFB voltage. This setting causes the gate voltages of M5 and M6 to rise when VFB drops, thereby increasing the pull-down current flowing through M6 and decreasing the pull-up current of M5. This can quickly reduce the gate input voltage of M1. The power transistor 4 outputs a large current as its gate voltage decreases, and the pulled-down VFB voltage quickly rises back to its normal value. Conversely, when the VFB voltage rises, the current of M5 is greater than that of M6, causing the voltage at this node to be rapidly boosted. The power transistor 4 outputs a smaller current as its gate voltage increases, causing the VFB voltage to drop and quickly return to its steady-state value.

[0035] Please see Figure 3 , Figure 3 The circuit performance comparison diagram shows that when the load current jumps from 6mA to 12mA in 17ns, the red dashed line represents the transient response curve of the LDO design. It can be seen that its output voltage change amplitude is significantly smaller than that of the traditional circuit, and the voltage recovery time is also much faster than that of the traditional circuit, demonstrating excellent voltage regulation performance and fast response characteristics.

[0036] When using the transient enhancement-type fast response LDO circuit of this invention, the LDO circuit incorporates an SSF super source follower architecture as a fast response branch of the transient enhancement stage. The circuit's ultra-large bandwidth enables the output voltage to change by less than 2% and recover in 20ns when the load current jumps to 12mA in 17ns. The LDO circuit directly monitors and feeds back the output voltage, effectively shortening the sampling signal transmission path, accelerating voltage signal transmission, and minimizing the impact of parasitics and matching on sampling accuracy. The operational amplifier 1 circuit adopts an output current mirror architecture, which can effectively improve the output voltage swing of the op-amp, thereby effectively improving the input voltage range of the power transistor gate voltage.

[0037] The above-disclosed embodiments are merely one or more preferred embodiments of this application and should not be construed as limiting the scope of this application. Those skilled in the art can understand that all or part of the processes for implementing the above embodiments and equivalent changes made in accordance with the claims of this application still fall within the scope of this application.

Claims

1. A transient enhancement-type fast response LDO circuit, characterized in that, include: An operational amplifier is used to receive feedback voltage VFB and reference voltage VREF, and to regulate the output voltage Vout through a negative feedback loop; A buffer stage circuit, connected to the output of the operational amplifier, is used to isolate the high-impedance node of the operational amplifier output from the subsequent circuit. A super source follower circuit is connected to the output of the buffer stage circuit to quickly respond to sudden changes in load current. A power transistor, the gate of which is connected to the output of the buffer stage circuit and the super source follower circuit.

2. The transient enhancement-type fast response IDO circuit as described in claim 1, characterized in that, The super source follower circuit includes: M2 and M3 constitute a dynamic bias circuit, which is used to quickly adjust the gate voltage of the power transistor when the load current changes abruptly. M1, as a common-source amplifier, is used to invert and amplify the output voltage of the operational amplifier and output it to the gate of M3; M4, whose gate is connected to the output terminal of the buffer stage circuit, is used in conjunction with M2 and M3 to quickly respond to changes in output voltage.

3. The transient enhancement-type fast response IDO circuit as described in claim 1, characterized in that, The operational amplifiers include M5 and M6, which employ a current mirror output stage architecture to extend the output voltage swing of the operational amplifiers.

4. The transient enhancement-type fast response IDO circuit as described in claim 1, characterized in that, The power transistor uses a large-size transistor to adjust the output current according to changes in the gate voltage in order to stabilize the output voltage Vout.

5. The transient enhancement-type fast response IDO circuit as described in claim 1, characterized in that, The feedback voltage VFB is sampled from the output voltage Vout through a resistor divider network, and the sampled signal is directly transmitted to the input terminal of the operational amplifier.

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